KR20050065066A - High performance serial bus bridge apparatus - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a high speed serial bus bridge device.

2. The technical problem to be solved by the invention

An object of the present invention is to provide a high speed serial bus bridge device capable of extending the number of IEEE 1394 devices through a high speed serial bus, while eliminating the length limitation of the transmission line and simplifying the configuration of the device.

3. Summary of the Solution of the Invention

The present invention provides a serial bus bridge apparatus, comprising: storage means for temporarily storing data received from one serial bus interface unit for transmission to another serial bus interface unit under management; Under the management of the management means, a depremer means for separating the header portion of the data received through the one serial bus interface unit, storing it in the control and state storage means, and storing the remaining data in the storage means; Multiplexing means for determining data to be transmitted by multiplexing the data stored in the storage means, under the management of the managing means; A primer means for adding a header portion to the determined data and managing the serial data through an interface of the management means; The control and state storage means for storing state and control information of each component of the bridge device, header information and state information of data received through the serial bus interface unit under management of the management means; Management means for managing stream processing of the bridge device, generation of route maps, generation and removal of nets, and management of global node IDs; And synchronizing means for synchronizing a cycle with the serial bus interface unit under management of the managing means.

4. Important uses of the invention

The present invention is used in home networks and the like.

Description

High performance serial bus bridge apparatus

The present invention relates to a bridge of a high speed serial bus, and more particularly, to a high speed serial bus bridge device capable of connecting a high speed serial bus IEEE1394 interface present on two different buses.

Recently, as the development and distribution of digital A / V devices is expanded, the demand for a home network system that enables various multimedia services is increasing rapidly. Network users are eager to connect digital home appliances such as digital camcorders, DVDs, HDTVs, and home theaters that can be connected to a single network so that high-quality multimedia data can be transmitted and received in real-time at all places in the home. In order to enable such a multimedia service, although the data transmission rate must be maintained at 20Mbps or more, the existing packet communication network has a limitation in transmitting such a large amount of multimedia data in high quality and real time.

However, IEEE1394 technology is a communication technology capable of isochronous transmission, and is a transmission technology that is very suitable for the transmission of a large amount of multimedia data. The IEEE1394 is a technology that can transmit high-speed large-capacity multimedia data, and is widely used in AV equipment. Currently, IEEE1394b can transmit data up to 3.2Gbps, and commercialized products can transmit data up to 800Mbps. . In addition, the maximum number of devices that can be connected to one bus is 63, and has the advantage that the operation of connecting or removing devices to the bus is simple, and thus it is highly useful as a backbone network of a home network.

However, although the number of devices that can be connected to one bus is 63, IEEE1394 has a transmission distance of 4.5m and remote transmission is impossible. In addition, although the wireless IEEE1394 describes a structure connecting the wired IEEE1394 and the wireless LAN scheme, the function as an actual wired bridge is not mentioned at all. Therefore, there is an urgent need to implement a bridge or the like function in IEEE1394 so that the number of IEEE1394 devices can be extended, while eliminating the length limitation of the transmission line and at the same time making the bridge simpler.

SUMMARY OF THE INVENTION The present invention has been proposed to meet the above-mentioned demands, and it is possible to extend the number of IEEE1394 devices through a high speed serial bus, while also eliminating the length limitation of the transmission line and simplifying the configuration of the devices. The object is to provide a bus bridge device.

Another object of the present invention is to provide a high speed serial bus bridge device that can be used as a wireless 1394 for home network configuration by replacing one of two IEEE 1394 interfaces with a wireless interface.

According to an aspect of the present invention, there is provided a serial bus bridge apparatus, comprising: storage means for temporarily storing data received from one serial bus interface unit for transmission to another serial bus interface unit under management; Under the management of the management means, a depremer means for separating the header portion of the data received through the one serial bus interface unit, storing it in the control and state storage means, and storing the remaining data in the storage means; Multiplexing means for determining data to be transmitted by multiplexing the data stored in the storage means, under the management of the managing means; A primer means for adding a header portion to the determined data and managing the serial data through an interface of the management means; The control and state storage means for storing state and control information of each component of the bridge device, header information and state information of data received through the serial bus interface unit under management of the management means; Management means for managing stream processing of the bridge device, generation of route maps, generation and removal of nets, and management of global node IDs; And synchronizing means for synchronizing a cycle with the serial bus interface unit under management of the managing means.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an embodiment of a high speed serial bus bridge device according to the present invention.

As shown in FIG. 1, the high speed serial bus bridge device according to the present invention, under management of the management unit 38, converts data received from the IEEE 1394 interface unit 10/20 into an IEEE 1394 interface unit (or a wireless 1394 interface unit). First-in-first-out (FIFO) memory unit 31, which is temporarily stored for transmission to 20/10, and under management of management unit 38, IEEE 1394 interface unit 10 / A deframer (36, 37) which separates the header portion of the data received through 20), stores it in the control and status register 39, and stores the remaining data in the FIFO memory section 31; Under the management of the management unit 38, multiplexers 32 and 33 for determining the data to be transmitted by multiplexing the data stored in the FIFO memory unit 31, and under the management of the management unit 38, the multiplexer 32 IEEE 1394 interface by adding a header part to the data determined by Framers 34 and 35 to be transmitted to the switch unit 20/10, and under the management of the management unit 38, the state and control information of each component of the bridge unit 30, and the IEEE1394 interface unit 10 Control and status registers 39 for storing header information and status information of the data received through / 20), stream processing of the bridge portion 30, generation of route maps, generation and removal of nets, A management unit 38 for managing global node IDs (ID), and a cycle timer 40 for synchronizing cycles with the IEEE1394 interface units 10 and 20 under the management of the management unit 38.

The high speed serial bus bridge device (bridge section 20) according to the present invention includes a high speed serial bus IEEE1394 interface section (10,20), a control section and a bus interface section (50) for controlling the data transmission of the bridge section (30). Works with

The bridge unit 30 is a part for transmitting subaction data by connecting two high-speed serial buses of the IEEE1394 interface unit 10 and 20 to each other. The bridge unit 30 can extend up to 63 devices connected to one bus. 1023 x 63 IEEE1394 devices can be connected, and the data flow between the IEEE1394 interface units 10 and 20 is controlled.

The FIFO memory unit 31 temporarily stores subaction data transmitted through each IEEE 1394 interface unit 10 or 20, and isochronous FIFO memory for real time transmission and asynchronous transmission for asynchronous transmission. It consists of two request FIFO memories and two response FIFO memories.

The multiplexers 32 and 33 multiplex the subaction data stored in six areas of the FIFO memory unit 31 and transmit the multiplexed subaction data to the frames 34 and 35.

Framers 34 and 35 receive subaction data from multiplexers 32 and 33 and attach header information stored in control and status registers 39 to transmit them to IEEE1394 interface units 10 and 20.

The deframers 36 and 37 receive subaction data from the IEEE 1394 interface units 10 and 20, separate header information of the subaction data, and store the header information in the control and status registers 39.

The management unit 38 transmits the subaction data transmitted through the IEEE1394 interface units 10 and 20 to the multiplexers 33 and 32 and the primers 35 through the deprers 36 and 37 and the FIFO memory unit 31. 34) processes stream data transmitted to the IEEE1394 interface unit 20, 10, generates route maps, creates and removes nets, configures global node IDs, and cycles with control and status registers 39. A timer (cycle timer) 40 is managed and associated with the control unit and the bus interface unit 50 to manage the overall operation of the high speed serial bus bridge unit 30.

The control and status register 39 stores status information and control information of each block configured in the bridge unit 30 and header information and status information of subaction data transmitted from the IEEE 1394 interface units 10 and 20. The input / output of the register data is operated by being connected to the signal, the controller, and the bus interface unit 50 configured in each block.

The IEEE 1394 interface units 10 and 20 perform transmission and reception of the IEEE 1394 subaction data with the bridge unit 30 through an interface with a chip compliant with IEEE 1394.

The cycle timers 40 synchronize with each other when the cycle synchronization of subaction data between the IEEE 1394 interface unit 10 and the IEEE 1394 interface unit (or wireless 1394 interface unit 20) is disrupted. Let's match.

The control unit and bus interface unit 50 are connected to the control and status register 39 and the management unit 38 to grasp the overall operating state of the bridge unit 30 and to control the flow of data.

The high speed serial bus bridge device (bridge section 30) configured as described above operates in compliance with IEEE1394, satisfies all transmission speeds supported by IEEE1394, and connects up to 63 IEEE1394 devices to 1023 x 63 devices. Can be extended.

For the sake of understanding, we will look at the basic and detailed structure of the bridge, the bridge net topology, and the structure of the bridge prototype.

IEEE1394 can deliver 100, 200 and 400Mbps data rates depending on the mode. In recent years, IEEE1394b is basically 800Mbps and can deliver up to 3.2Gbps. Currently available products are available up to IEEE1394b which can support up to 800Mbps. At this speed, it is enough to transmit digital audio or video information, so you can connect a digital camcorder, HDTV, etc. to transmit data in real time. In addition, the IEEE1394 protocol can be connected and operated immediately without changing the overall topology even if there is a conversion such as connection or removal of a device connected to each node.

IEEE1394 can connect up to 63 nodes on a single bus. The bridge is the bridge that connects these 63 nodes. The bridge can consist of 1023 bridges, in which case the device can be connected to a total of 1023 x 63 nodes. 2 shows a general structure of a bridge.

In FIG. 2, an IEEE 1394 physical layer (Bridge PHY) block is electrically and physically connected between an IEEE 1394 device and a cable, and serves to actually transmit data. Provides initialization and arbitration functions for data transmission and reception.

In addition, the bridge link layer block is responsible for the transmission and reception of all packets, and also performs cycle control for the isochronous channel.

IEEE1394 transmits data divided into asynchronous and isochronous. Thus, asynchronous data is transmitted to a higher layer via a Bridge TR layer block, while isochronous data is transmitted directly to a higher layer.

Here, the Bridge TR layer block performs "read", "write", and "lock" of an asynchronous protocol as a transaction layer. "write" sends data from the sending side to the receiving side, "read" sends the data to the sending side, and "lock" is a combination function of "write" and "read". Performs a function of retransmission after the completion of other send side communication.

In FIG. 2, the "Bridge Management & Internal Fabric" block is to be implemented as a real bridge, and serves as a bridge connecting two Bridge PHY + Link.

As shown in FIG. 3, the bridge has a 2-portal structure, and each portal is connected to an IEEE1394 PHY & Link, and up to 63 IEEE1394 devices can be connected to the PHY. The IEEE 1394 device connected to each portal is identified through a global ID. Here, the global ID is composed of 16 bits, the upper 10 bits are the bus ID, and the lower 6 bits are the node ID.

The bridge has three types of FIFOs. That is, it is composed of two FIFO blocks capable of transmitting isochronous data, two request FIFO blocks capable of transmitting asynchronous data, and two response FIFO blocks.

In addition, the Route Maps block controls the operation of the bridge when transmitting and receiving data on response and request subactions.

In addition, the CSR register block controls the state information and the bridge operation of each portal through a register according to IEEE Std 1212-2001, a bus dependent register of IEEE1394, a register required by a bridge, and the like.

In addition, the cycle clock block is a part for synchronizing the clock of the isochronous data.

Each portal has a Configuration ROM defined by IEEE1394. The Configuration ROM stores information such as EUI_64, Vendor_ID, node capability, bus dependent information, bridge capability, and the like.

4 shows a simple bridge net topology.

In FIG. 4, when attempting to send Rq to Rsp based on a request subaction, the destination_ID field routes a subaction toward bus 17.

The initial entry portal 42 then transforms the source_ID field into a universal node ID corresponding to the local node ID sent by Rq.

Next, when a subaction is sent to bus 941, there is no change of source_ID or destination_ID, and when the request subaction arrives at the destination bus, terminal exit portal 17 is general purpose. Transform the destination_ID field from the node ID to the local node ID recognized by Rsp. In response to this, when the Rsp responds, the universal node ID of the source_ID field of the request subaction is used as a destination of the response subaction.

Table 1 below shows the change of the universal ID that is changed during the transmission of subaction data between Rq and Rsp.

The prototype of the high speed serial bus bridge is implemented in two ways.

The first method for implementing wired high speed serial bus bridges is to embed two IEEE1394-related chips in the system. In this case, one IEEE 1394 chip becomes one portal and another IEEE 1394 chip becomes another portal.

At this time, the IEEE1394 chip uses a chip that conforms to the IEEE1394-1995 and IEEE1394a standards, and uses a chip having a host bus interface and a bulky data interface instead of a PCI interface.

The basic structure of such a bridge is the same as the block described in FIG. In this case, the devices with the upper 10-bit part of the universal ID attached to each portal must be different.

The second configuration method is to configure one IEEE1394 chip as one portal and the other to connect wirelessly. In this case, the radio may be IEEE802.11a / e (WiFi) or IEEE802.15.3 (UWB). In this case, the wireless portion may consist of one portal, which may be referred to as a wireless 1394.

5 shows the structure of the bridge prototype.

In FIG. 5, the left block is a portal portion connecting the IEEE1394 chip, and the right block is a portal connecting IEEE802.11a / e.

In addition, the processor and the firmware portion represented in the upper block play a role of controlling initialization and data transmission of the IEEE1394 chip, IEEE802.11a / e, and the bridge. For example, the processor uses Altera's Excalibur chip, including the ARM9 family, and the operating system is designed using Linux.

The IEEE1394 bridge and IEEE802.11a / e have different data transfer protocols, and since the basic network is IEEE1394, IEEE802.11a / e should look like IEEE1394. The part that plays this role is PAL (Protocol Adaptation Layer). The PAL is not really IEEE1394, but when viewed from the bridge it should behave as if IEEE1394 is connected.

The IEEE1394 subaction data is mainly implemented in hardware to pass through the bridge, and the operations to be performed on the high speed serial bus bridge are implemented in software. At this time, the parts to be implemented in hardware are FIFO and registers, and the parts to be implemented in software are Configuration ROM, CSR register, transaction operation, stream operation control, and net update management. And so on.

6 is an explanatory diagram showing a high speed serial bus bridge prototype board according to an embodiment of the present invention.

In Fig. 6, at the bottom, an IEEE1394 port is for a wired high speed serial bus bridge test, and two chips are connected to an Excalibur chip. For example, the Excalibur chip uses the EPXA10F1020, which has one million gates inside the FPGA. In this portion of the FPGA, the hardware logic of the bridge is coded and implemented in VHDL. The bridge also works with Excalibur's AMBA bus to monitor and control the bridge hardware.

In addition, the right part is the wireless implementation part and consists of Xilinx FPGA XC2V4000. This part is mainly implemented by coding the OFDM circuit in VHDL. In addition, the circuit of the lower right part consists of an A / D and a D / A converter. The RF part is designed separately.

The test of the high speed serial bus bridge prototype connects an IEEE1394 device to an IEEE1394 port and verifies topology changes, initialization, and data transfer on the first connection.

As a wireless 1394 test, two bridge prototype boards are used to wirelessly transfer between the bridge prototype boards, and an IEEE1394 device can be connected at both ends to verify data transmission.

As described above, the high speed serial bus bridge of the present invention is a bridge between IEEE1394 wired wires, and can be used by extending the IEEE1394 device to 1023 x 63.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention can extend the number of IEEE1394 devices that can be conventionally connected through the high speed serial bus bridge, while eliminating the length limitation of the transmission line, and can more easily configure the high speed serial bus bridge. .

In addition, the present invention has the effect that can be utilized as a wireless 1394 for home network configuration by replacing one of the two IEEE1394 interface with a wireless interface.

1 is a configuration diagram of an embodiment of a high speed serial bus bridge device according to the present invention;

2 is an explanatory diagram showing a basic structure of a general bridge;

3 is a diagram illustrating an example of a detailed bridge structure of a high speed serial bus bridge device according to the present invention;

4 is an exemplary diagram illustrating a bridge net topology of a high speed serial bus bridge device according to the present invention;

5 is a diagram illustrating an exemplary structure of a bridge prototype of a high speed serial bus bridge device according to the present invention;

Figure 6 illustrates one embodiment of a bridge prototype board in accordance with an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing

31: FIFO memory section 32, 33: multiplexer

34,35: primer 36,37: deprema

38: management unit 39: control and status register

40: cycle timer

Claims (3)

In the serial bus bridge device, Storage means for temporarily storing data received from one serial bus interface unit for transmission to another serial bus interface unit under management of the management means; Under the management of the management means, a depremer means for separating the header portion of the data received through the one serial bus interface unit, storing it in the control and state storage means, and storing the remaining data in the storage means; Multiplexing means for determining data to be transmitted by multiplexing the data stored in the storage means, under the management of the managing means; A primer means for adding a header portion to the determined data and managing the serial data through an interface of the management means; The control and state storage means for storing state and control information of each component of the bridge device, header information and state information of data received through the serial bus interface unit under management of the management means; Management means for managing stream processing of the bridge device, generation of route maps, generation and removal of nets, and management of global node IDs; And Synchronization means for synchronizing cycles with the serial bus interface unit under management of the management means. High speed serial bus bridge device comprising a. The method of claim 1, The one serial bus interface unit is an IEEE1394 interface unit, And the other serial bus interface unit is one of an IEEE 1394 interface unit and a wireless 1394 interface unit. The method according to claim 1 or 2, The storage means, Temporarily stores the subaction data transmitted through each serial bus interface, including at least two isochronous first-in-first-out (FIFO) memories for real-time transmission, and at least two requests for asynchronous transmission. (request) A high speed serial bus bridge device comprising a FIFO memory and at least two response FIFO memories.