KR20050064709A - Data input/output circuit of semiconductor memory device - Google Patents

Abstract

A data input / output circuit of a semiconductor memory device is disclosed. The data input / output circuit includes a plurality of pairs of bit lines (BL, BLB) connected to each of the plurality of memory banks, a plurality of bit line sense amplifiers for amplifying data of each of the plurality of bit line pairs, and a plurality of block selections. In response to the signals BDCAi, BDCAj, BDCAiB, and BDCAjB, a plurality of self-boosting circuits and a column decoder signal line outputting the signal of the column selection line CSL to the column decoder signal CDi and CDj lines are provided. A plurality of transistors are configured to output data of four bit line signal pairs BL and BLB to a local data input / output line LIO pair. The data input / output circuit according to the present invention can minimize the layout area when designing a semiconductor through a circuit structure using a self-boosted column select line signal, and can reduce the number of transistors to which data moves, thereby increasing data input / output speed. do.

Description

Data input / output circuit of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device having a sense amplifier which speeds up the input / output speed of data while minimizing the layout area.

One of the fastest parts of DRAM's operating characteristics is the circuits associated with columns. Typically, circuits associated with a row require operating speeds of tens of ns. However, the timing constant in the circuit associated with the column requires a few ns.

The operation related to the column is output from a plurality of memory banks and the data of a predetermined column among the data amplified through the bit line (B / L) sense amplifier (S / A) is connected to a local data input / output line (LIO) pair through a column select switch. And output to a global data input / output line (GIO) pair and related to a process of converting the data input / output sense amplifier (I / OS / A) from the CMOS level to the data RD.

1 shows a schematic block diagram of a semiconductor memory device having a conventional hierarchical column select line circuit.

In a semiconductor memory device having a memory array structure having a plurality of memory banks, a row decoder driving a word line and a column decoder driving a bit line When arranging (Column Decoder), a low decoder and a column decoder are arranged for each bank, or a low decoder and a column decoder having block information for each bank are designed.

A semiconductor memory device using a row decoder having a block information for each bank and a column decoder has a hierarchical column selection line circuit using a column selection line circuit having block information.

Referring to FIG. 1, a semiconductor device having a conventional hierarchical column select line circuit includes memory banks 110 and 140, bit lines BLSi, BLSiB, BLSj, and BLSjB, a global column select line GCSL, and a power supply line. (VSSL), and a column decoder 170.

The bit lines BLSi and BLSiB are for enabling the global column select line GCSL circuit with respect to the memory bank 110.

The bit lines BLSj and BLSjB are for enabling the global column select line GCSL circuit with respect to the memory bank 110.

The column decoder 170 inputs a column address CAi to enable the corresponding global column selection line among the global column selection lines GCSL,...

The global column select line GCSL has information on the memory cell array blocks constituting the memory banks 110 and 140. That is, the global column select line GCSL is for enabling a local column select line LCSLi corresponding to a specific memory cell array block among the memory cell array blocks constituting the memory banks 110 and 140, respectively. .

The power line VSS is to apply the ground power VSS to a circuit configuring the global column selection line GCSL separately from the memory cell array blocks forming the memory banks 110 and 140.

The memory bank 110 includes memory cell arrays 112 and 122, sensing blocks 114, 116, 124 and 126, word lines WL,..., A local column select line LCSLi, and a low decoder 100.

The row decoder 100 inputs a low address input from the outside and thus enables the corresponding word line among the word lines WL,...

The memory cell arrays 112 and 122 are constituted by a plurality of memory cells connected between word lines WL,... And bit lines BLi and BLiB, respectively. Each memory cell is composed of one cell transistor and one cell capacitor. Each of the memory cells is accessed by a corresponding address and holds data in the form of a charge amount charged in the corresponding cell capacitor. The cell transistor has the function of switching the charge stored in the cell capacitor and gated by the corresponding word line to the corresponding bit line.

The bit lines BLi and BLiB serve as bit lines BL and inverted bit lines / BL with respect to the corresponding memory cells. That is, when a memory cell selected for reading information is connected to the bit line BLi, the bit line BLi becomes a bit line BL and the bit line BLiB becomes an inverted bit line / BL. When the memory cell selected for reading information is connected to the bit line BLiB, the bit line BLiB becomes the bit line BL and the bit line BLi becomes the inverted bit line / BL.

The sensing blocks 114, 116, 124, and 126 sense the level difference between the corresponding bit lines BLi and BLiB and amplify and transmit the level differences.

The local column select line LCSLi is enabled by the corresponding global column select line GCSL and transmits data of a corresponding memory cell on the corresponding bit lines BLi and BLiB to the input / output line IO. .

The memory bank 140 includes memory cell arrays 142 and 152, sensing blocks 144, 146, 154 and 156, word lines WL,..., A local column select line LCSLj, and a low decoder 130. The memory cell arrays 142 and 152, the sensing blocks 144, 146, 154, 156, the word lines WL,..., The local column select line LCSLj, and the row decoder 130 each constitute a memory bank 110. The memory cell arrays 112, 122, the sensing blocks 114, 116, 124, 126, the word lines WL,..., The local column select line LCSLi, and the row decoder 100 have the same configuration.

It is an object of the present invention to provide a data input / output circuit in a semiconductor memory device having a plurality of independent memory banks for minimizing the layout area.

Another object of the present invention is to provide a data input / output circuit of a semiconductor memory device having excellent data input / output speed by reducing the number of switches for outputting data.

According to an aspect of the present invention, a data input / output circuit of a semiconductor memory device for inputting / outputting corresponding data from a plurality of memory banks is connected to each of the plurality of memory banks. A plurality of bit line BL, BLB pairs, a plurality of bit line sense amplifiers for amplifying data of each of the plurality of bit line pairs, and a plurality of block selection signals BDCAi, BDCAj, BDCAiB, and BDCAjB. In response, the data of the plurality of bit line signal pairs BL and BLB in response to the signals of the column decoder signal line and the self-boosting circuit outputting the signal of the column selection line CSL to the column decoder signal CDi and CDj lines. Is provided with a plurality of transistors for outputting to a local data input / output line (LIO) pair.

Preferably, the self-boosting circuit of the semiconductor memory device data input / output circuit according to the present invention outputs a column select line (CSL) signal to the first column decoder (CDi) line in response to the first block select (BDCAi) signal. In response to the second block selection BDCAj signal, the column selection line CSL signal is output to the second column decoder CDj line.

More preferably, the self-boosting circuit of the semiconductor memory device data input / output circuit according to the present invention outputs a ground voltage level to the first column decoder CDi line in response to a first inverted block select signal BDCAiB. The ground voltage level is output to the second column decoder CDj line in response to the two inverted block select signal BDCAjB.

Preferably, the semiconductor memory device data input / output circuit according to the present invention further comprises a plurality of transistors for connecting the local data input / output line pair and the global data input / output line pair in response to a first or second block selection (BDCAij) signal. Equipped.

Preferably, the semiconductor memory device data input / output circuit according to the present invention includes an input / output sense amplifier (I / OS / A) for amplifying data of a global data line pair, and an input / output for driving input data to a global data line pair. The driver may further include an I / O DRV.

Preferably, in the semiconductor memory device data input / output circuit according to the present invention, each block select signal line input to the boosting circuit may be shared with another adjacent memory bank.

Preferably, each of the plurality of transistors constituting the semiconductor memory device data input / output circuit according to the present invention may be composed of NMOS.

More preferably, in the semiconductor memory device data input / output circuit according to the present invention, the first inverted block select signal BDCAiB and the second inverted block select signal BDCAjB may use the same signal.

In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 2 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line at a CMOS level in FIG. 1.

Referring to FIG. 2, data output from the plurality of memory banks 201i and 201j is amplified by corresponding sense amplifiers 203i and 203j, respectively. However, there are a plurality of memory banks corresponding to one local data input / output line (LIO) pair. Therefore, block select switches 205i and 205j and column select switch 207 are required to output only data of a predetermined column among data output from the plurality of memory banks.

When the first block select signal BDCAi is transitioned to the high level and the second block select signal BDCAj is at the low level, the switch 205i is turned on and the switch 205j is turned off. Therefore, data stored in the memory bank 201i existing above the local data input / output line pair (LIO pair) is selected. The column select switch 207 outputs only data of a desired column among data output from the plurality of memory banks existing in the upper portion of the local input / output data line pair in response to the column select line (CSL) signal.

The data output as the local data input / output line (LIO) pair is output to the global input / output line GIO through the data input / output switch 209. The data input / output switch 209 is controlled by the bank select signal BDDAij.

As shown in FIG. 2, data output from the memory bank is transferred from the bit line sense amplifier (B / LS / A) to the data input / output sense amplifier (I / OS / A) and converted into CMOS level data. Pass through series-connected switches 205ij, 207, 209. The speed at which weak analog data propagates in the memory bank through the above operation is determined by the number of switches connected in series and the size of the switch transistor.

As described above, the circuit related to the column among the operating characteristics of the DRAM requires a timing constant of several ns, thereby limiting the data input / output speed.

Of the three series-connected switches described above, the block select switches 205i and 205j and the column select switch 207 have to be drawn according to a predetermined pitch of the cell array. Therefore, the transfer of the signals from the bit line sense amplifiers 103i and 103j to the data input / output sense amplifiers I / O S / A is considerably delayed.

In addition, the number of prefetch bits is increasing in order to increase the bandwidth, so that data must be simultaneously transmitted to 4 to 8 I / O pairs in one column select (CSL) signal. It is also quite complicated.

For example, when eight data input / output lines I / O are connected to one column select line CSL, a series transistor of two types of block select signals BDCAi and BDCAj and a column select line CSL is illustrated. It is not easy to design eight in a narrow area. If the two bit line sense amplifiers (B / LS / A) shown in FIG. 2 do not share a local data input / output line (LIO), the connection may be easy, but space for the local input / output line (LIO) may be increased. The problem is that the area is consumed and the capacitive loading of charging the capacitor of the column select line CSL also doubles.

3 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line of a CMOS level according to an embodiment of the present invention.

Referring to FIG. 3, a data input / output circuit according to the present invention includes a self-boosting circuit 300 that controls data thrust from a memory bank according to a column select line CSL signal and a block select signal BDCAij.

In addition, the data input / output circuit according to the present invention has column decoder lines CDi and CDj for outputting a column select line CSL signal output from the self-boosting circuit 300 as a bit line pair. Also, column decoder switches 305i and 305j are configured to output data of a predetermined column among data output from the memory bank in response to the column decoder line signal as a pair of local data input / output lines (LIO).

Looking at the configuration of the self-boosting circuit 300, the column select line (CSL) signal is input to the node (31). The NMOS transistor 37 controlled in response to the first block selection signal BDCAi is connected between the node 31 and the node 32. The first block selection signal BDCAi is connected to the gate of the transistor 37 through the NMOS transistor 35.

An NMOS transistor 38 controlled in response to the second block select signal BDCAj is connected between the node 31 and the node 33. The second block select signal BDCAj is connected to the gate of the transistor 38 through the NMOS transistor 36. A power supply voltage is connected to the gates of the transistors 35 and 36.

An NMOS transistor 39 controlled in response to the first inverted block select signal BDCAiB is connected between the node 32 and the node 34. An NMOS transistor 40 controlled in response to the second inversion block select signal BDCAjB is connected between the node 33 and the node 34. The node 34 is connected to a ground power source.

The first column decoder line CDi connected to the node 32 transfers the column select line CSL signal to the column decoder switch 305i in response to the first block select signal BDCAi.

The second column decoder line CDj connected to the jode 33 transfers the column select line CSL signal to the column decoder switch 305j in response to the second block select signal BDCAj.

The column decoder switches 305i and 305j are composed of two pairs of NMOS transistors connected to a pair of bit lines. The column decoder switches 305i and 305j receive data corresponding to the corresponding column decoder signals CDi and CDj.

Referring to the operation of the self-boosting circuit 300, when the first block selection signal BDCAi transitions to a high level and the second block selection signal BDCAj is at a low level, the transistor 37 is turned on and the transistor 38 is turned on. ) Is turned off, so that the column select line (CSL) signal of node 31 is transmitted to node 32. If the column select line signal is at the low level, the self-boosting circuit 300 outputs a low level signal, and data of the memory bank corresponding to the column select line signal is not read or written.

That is, when the column select line signal CSL is at a high level and the first block select signal BDCAi is at a high level, the node 32 transitions to a high level. Then, the first column decoder line CDi is at a high level, and the first column decoder switch 305i is turned on. Then, data from the memory bank 301i corresponding to the first block selection signal BDCAi is output to the local data input / output line LIO pair.

When the column select line signal CSL is at a high level and the second block select signal BDCAj is at a high level, the node 33 transitions to a high level. Then, the second column decoder line CDj is at a high level, and the second column decoder switch 305j is turned on. Then, data from the memory bank 301j corresponding to the second block selection signal BDCAj is output to the local data input / output line LIO pair.

In addition, when the first block selection signal BDCAi is at a low level, the first inversion block selection signal BDCAiB is at a high level to maintain the node 32 at a low level, and the second block selection signal BDCAj is at a low level. If the level is high, the second inverted block select signal BDCAjB goes high and keeps the node 33 low.

If the first block selection signal BDCAi or the second block selection signal BDCAj is at a high level, the data input / output switch 307 is turned on to transfer data from the local data input / output line LIO to the global data input / output line GIO pair. Output

The global data input / output line (GIO) pair further includes a data input / output sense amplifier (I / O S / A) for amplifying the output data and an input / output driver circuit for driving the input data to the global data line pair.

The data input / output circuit having the self-boosting circuit 300 according to the present invention may output data of a predetermined memory bank to the outside of the semiconductor memory device in response to a signal for selecting a column and a block.

In addition, using the self-boosting circuit proposed in the present invention, the data path is reduced from two conventional switches to two switches, that is, the column decoder switches 305i and 305j and the data input / output switch 307, thereby providing a data input / output speed. Will increase.

In addition, when eight data input / output circuits are connected to one column select line (CSL) signal, four pairs of data input / output circuits are connected to the upper portion of the memory bank because of the shared local data input / output line (LIO). The pairs are connected down. According to the data input / output circuit according to the present invention, two transistors are reduced in each of the four pairs of data input / output circuits, and a self-boosting circuit including six transistors is added to reduce the number of transistors as a whole. As a result, as the number of transistors is reduced, a faster data transfer rate can be obtained, and at the same time, the layout area of the semiconductor memory device can be minimized.

4 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line at a CMOS level according to another exemplary embodiment of the present invention.

Referring to FIG. 4, the data input / output circuit includes a self-boosting circuit 400 in which the first inversion block selection signal BDCAiB and the second inversion block selection signal BDCAjB are combined into one.

Since other components of the data input / output circuit according to another embodiment of the present invention are the same as those shown in FIG. 3, other descriptions thereof will be omitted.

The number of local drivers in the conjuctin region is also reduced by combining the first inverted block selection signal BDCAiB and the second inverted block selection signal BDCAjB as one inverted block selection signal BDCAijB. In addition, due to the reduced signal line has the effect of reducing the busing (busing) generated in the input and output circuit.

FIG. 5 is a diagram illustrating a layout of the self-boosting circuit shown in FIG. 4.

Referring to FIG. 5, referring to a layout of a self boosting circuit 400 of a data input / output circuit according to another exemplary embodiment of the present disclosure, the self boosting circuit 400 may include a first N connected to a first block selection signal BDCAi. A second N well region 503 connected to the well region 501 and the second block selection signal BDCAj is formed.

A first gate region 521 is formed on the first and second N well regions to be connected to the power supply voltage VDD.

A third N well region 505 is formed below the first and second N well regions, and is connected to a region past the first gate 521 at the other end of the first N well region 501. A second gate 523 is formed across the N well region 505.

In addition, at the other end of the second N well region 503, the third gate 525 is formed across the third N well region 505. The third gate 525 is formed across the third N well region 505.

A fourth N well region 507 is formed below the third N well region 505 to be connected to the ground voltage VS, and one end of the third N will region 505 and one end of the fourth N well region (505). A fifth N well region 509 connecting 507, and a sixth N well region 511 connecting the other end of the third N well region 505 and the other end 507 of the fourth N well region 505. do.

A fourth gate region 527 is formed to receive the inverted block selection signal BDCAijB across the fifth N well region 509 and the sixth N well region 511.

The column select line signal CSL is input to a region between the second gate region 523 and the third gate region 525 of the third N well region 505 and the second gate region 523 The first column decoder line CDi is connected to the left side, and the second column decoder line CDj is connected to the right side of the third gate region 525.

In the self-boosting circuit layout of the data input / output circuit according to an embodiment of the present invention, when the sense amplifier is shared with an adjacent memory cell array block, the data loading across the sense amplifier is balanced and data busing is performed. ) Will be reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the data input / output circuit of the semiconductor memory device according to the present invention, a circuit structure using a self-boosted column select line signal can minimize the layout area when designing a semiconductor and can reduce the number of transistors to which data moves. Speed of input / output is increased.

1 shows a schematic block diagram of a semiconductor memory device having a conventional hierarchical column select line circuit.

FIG. 2 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line at a CMOS level in FIG. 1.

3 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line of a CMOS level according to an embodiment of the present invention.

4 is a partial circuit diagram illustrating a data input / output path from a bit line to a data input / output line at a CMOS level according to another exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a layout of the self-boosting circuit shown in FIG. 4.

Claims (16)

In a data input / output circuit of a semiconductor memory device for inputting and outputting corresponding data from a plurality of memory banks, A plurality of pairs of bit lines (BL, BLB) connected to each of the plurality of memory banks; A plurality of bit line sense amplifiers for amplifying data of each of the plurality of bit line pairs; A self-boosting circuit for outputting a signal of the column selection line CSL to the column decoder signal CDi and CDj lines in response to the plurality of block selection signals BDCAi, BDCAj, BDCAiB, and BDCAjB; And And a plurality of transistors for outputting data of the plurality of bit line signal pairs (BL, BLB) to a local data input / output line (LIO) pair in response to the signals of the column decoder signal line. The method of claim 1, The self boosting circuit, Outputting the column select line CSL signal to a first column decoder CDi line in response to a first block select signal BDCAi; And outputting the column selection line (CSL) signal to a second column decoder (CDj) line in response to a second block selection (BDCAj) signal. The method of claim 2, The self boosting circuit, Outputs a ground voltage level to the first column decoder CDi line in response to a first inverted block select signal BDCAiB; And outputting the ground voltage level to the second column decoder (CDj) line in response to a second inverted block selection (BDCAjB) signal. The method of claim 1, The data input and output circuit, And a plurality of transistors for connecting the local data input / output line pair and the global data input / output line pair in response to the first or second block selection (BDCAij) signal. The method of claim 4, wherein The data input and output circuit, An input / output sense amplifier (I / O S / A) for amplifying data of the global data line pair; And And an input / output driver (I / O DRV) for driving input data to the global data line pair. The method of claim 1, Each block select signal line input to the boosting circuit is shared with another adjacent memory bank. The method of claim 1, And each of the plurality of transistors is an NMOS. The method of claim 3, And the first inverted block select signal and the second inverted block select signal are the same signal. In a data input / output circuit of a semiconductor memory device for inputting and outputting corresponding data from a plurality of memory banks, A self boosting circuit generating a column decoder signal in response to the plurality of control signals; A plurality of bit line sense amplifiers for amplifying data output from each of the memory banks; A first transistor connected to the bit line output from the first bit line sense amplifier and configured to connect data output from the first memory bank to a local data input / output line; A second transistor connected to an inverted bit line output from the first bit line sense amplifier and configured to connect inverted data output from the first memory bank to an inverted local data input / output line; A third transistor connected to the bit line output from the second bit line sense amplifier and for connecting data output from the second memory bank to the local data input / output line; A fourth transistor connected to an inversion bit line output from the second bit line sense amplifier and for connecting inversion data output from the second memory bank to the inversion local data input / output line, The first transistor and the third transistor are connected to the local data input / output line, The second transistor and the fourth transistor are connected to the inverted local data input / output line, Gates of the first transistor and the second transistor are connected to a first column decoder line CDi, Gates of the third transistor and the fourth transistor are connected to a second column decoder line CDj, The self boosting circuit, A fifth transistor for transmitting a first block selection signal; A sixth transistor for conveying a second block selection signal; A seventh transistor configured to transfer a column select line (CSL) signal to the first column decoder line in response to the signal output from the fifth transistor; An eighth transistor configured to transfer the column select line (CSL) signal to the second column decoder line in response to a signal output from the sixth transistor; A ninth transistor configured to connect the first column decoder line and ground in response to a first inversion block selection signal; And And a tenth transistor for connecting the second column decoder line and ground in response to a second inversion block selection signal. The method of claim 9, The data input / output circuit is An eleventh transistor connecting the local data input / output line and the global data input / output line in response to the first or second block selection (BDCAij) signal; And And a twelfth transistor configured to connect the inverted local data input / output line and the inverted global data input / output line in response to the first or second block selection (BDCAij) signal. The method of claim 9, And the first inversion block selection signal and the second inversion block selection signal are the same signal. A plurality of memory banks; Multiple sense amplifiers; Local data input / output line pairs; A self-boosting circuit outputting a plurality of column decoder signals in response to the plurality of control signals; Each of the plurality of sense amplifiers senses and amplifies a data pair output from a corresponding memory bank among the memory banks, A first transmission circuit configured to transmit output signals of a corresponding sense amplifier to the local data input / output line pairs in response to a first column decoder signal among the plurality of column decoder signals; And And a second transmission circuit configured to transmit output signals of a corresponding sense amplifier to the local data input / output line pairs in response to a second column decoder signal among the plurality of column decoder signals. The method of claim 12, The plurality of memory banks includes a group of memory banks and a group of memory banks, the plurality of sense amplifiers having a group of sense amplifiers and a group of sense amplifiers, The group of memory banks and the group of memory banks are symmetrically arranged around the local data input / output line pair, And the group 1 sense amplifiers and the group 2 sense amplifiers are symmetrically arranged around the local data input / output line pair. The method of claim 12, The self boosting circuit, Outputting the column decoder signal to a first column decoder (CDi) line in response to a first block selection (BDCAi) signal, And outputting the column decoder signal to a second column decoder (CDj) line in response to a second block selection (BDCAj) signal. The method of claim 14, The self boosting circuit, Outputs a ground voltage level to the first column decoder CDi line in response to a first inverted block select signal BDCAiB; And outputting the ground voltage level to the second column decoder (CDj) line in response to a second inverted block selection (BDCAjB) signal. In a data input / output circuit of a semiconductor memory device for amplifying and outputting data output from a plurality of independent memory banks, A first N well region connected with the first block selection signal; A second N well region connected with a second block selection signal; A first gate region formed on the first and second N well regions and connected to a power supply voltage; A second gate region connected to the first N well region and formed across the third N well region; A third gate region connected to the second N well region and formed across the third N well region; A fourth N well region connected with a ground voltage; A fifth N well region connecting one end of the third N well region and one end of the fourth N well region; A sixth N well region connecting the other end of the third N well region and the other end of the fourth N well region; And A fourth gate region formed on the fifth N well region and the sixth N well region, and having an inverted block selection signal input thereto; A column select line signal is input to the third N well region between the second gate region and the third gate region, A first column decoder line connected to a pair of bit lines output from the memory bank, in the third N well region between the second gate region and the fourth gate region; A data boosting circuit configured to be connected to a second column decoder line connected to a pair of bit lines output from the memory bank in the third N well region between the third gate region and the fourth gate region; Circuit.