KR20050064389A - Driving unit of liquid crystal display - Google Patents

Abstract

The present invention relates to a driving unit of a liquid crystal display device, wherein the driving unit of the liquid crystal display device of the present invention receives image information except the least significant bit (LSB) and outputs a signal corresponding to the image information, and outputs from the decoder. A data selector for selectively outputting at least one drive signal according to the received signal and the least significant bit of the image information, and at least one switch is driven by the drive signal of the data selector to selectively apply a gradation voltage to the image signal. It is configured to include an output switching unit, since the area of the decoder is reduced while processing the same amount of image information as in the prior art, the area of the liquid crystal display drive unit is also reduced, making it easy to apply to small products such as mobile phones.

Description

DRIVING UNIT OF LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive unit of a liquid crystal display, and more particularly, to a drive unit of a liquid crystal display device which reduces the area of a circuit while processing the same image information as in the prior art.

In general, a liquid crystal display device is a thin film transistor array substrate and a color filter substrate are bonded to each other at regular intervals, the liquid crystal layer in the space between the thin film transistor array substrate and the color filter substrate. The formed liquid crystal panel and a driving unit for driving the liquid crystal panel.

In the thin film transistor array substrate, a plurality of gate lines that are uniformly spaced apart laterally and a plurality of data lines that are regularly spaced apart longitudinally intersect each other, and in the region where the gate lines and the data lines cross each other. Pixels are provided. The pixel is separately provided with a switching device such as a thin film transistor and a pixel electrode, and the switching device is electrically connected to the gate line and the data line.

In addition, a color filter layer of red, green, and blue is formed at a position corresponding to the pixels on the color filter substrate, to prevent light leakage between the color filter layers, and to prevent color interference of light passing through the pixels. A black matrix is formed between the color filter layers. In addition, a common electrode for applying an electric field to the liquid crystal is formed by a voltage difference from the pixel electrode of the thin film transistor array substrate.

The driver includes a gate driver and a data driver.

First, the data driver converts digital image information supplied from the outside into analog image information and applies it to the data line.

The gate driver sequentially applies a scan signal to the gate line every frame period. The switching elements electrically connected to the gate line to which the scan signal is applied are turned on, and the image is applied from the data driver. Information is applied to the pixel electrode through the switching element. In this way, the image information applied to the pixel electrode applies an electric field to the liquid crystal due to the voltage difference from the common electrode, and the liquid crystal is driven by the electric field to display an image.

Hereinafter, the data driver will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically showing the configuration of a data driver of a liquid crystal display device.

Referring to FIG. 1, the shift register unit 2 sequentially outputs the sampling signal SS1 by the control signal CS1, and the image information DATA according to the sampling signal SS1 of the shift register unit 2. ), A latch unit 4 for sequentially sampling and storing, a digital-analog converter 6 for converting and outputting image information received from the latch unit 4 into analog image information, and the digital-analog conversion. And a buffer unit 8 for buffering and outputting the image information applied from the unit 6.

A plurality of shift registers are provided in the shift register part 2, and the shift register sequentially shifts the control signal CS1 applied to the shift register part 2 and outputs the sampling signal SS1.

The latch unit 4 sequentially samples and stores image information corresponding to the sampling signal SS1 applied from the shift register unit 2, and when the data output signal SOE1 is applied, the latch unit 4 stores the stored image information. Output at the same time.

The digital-analog converter 6 receives image information of the latch unit 4 and receives a gamma voltage GMA1 from a gamma voltage generator (not shown). Accordingly, the digital-to-analog converter 6 forms a plurality of gray voltages through the applied gamma voltage GMA1 to sample the gamma voltage GMA1 corresponding to the input image information, thereby obtaining the image information. Convert to analog image information.

Usually, 6-bit image information is used in the liquid crystal display device. The number of gradations that can be displayed by this 6-bit image information is 2 ⁶ = 64. The digital-analog converter 6 voltage drops the gray voltage applied from the gamma voltage generator a plurality of times to form 64 voltages, and outputs the 64 gray voltages corresponding to the digital image information.

The image information converted by the digital-analog converter 6 is signal-buffered by the buffer 8 and output to the data line.

The configuration and driving of the digital-to-analog converter 6 in the data driver as described above will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a configuration of a general digital-analog converter.

In recent years, a small screen image display device and a large screen image display device have exceptions, but usually 6-bit signals are mainly used for image signals that are compressed and transmitted in digital form.

Referring to FIG. 2, the digital-to-analog converter is configured to selectively output one signal in response to the image information received, and the applied gamma voltage is dropped through a plurality of resistors to obtain a plurality of gray voltages. A gray level voltage is selectively outputted as an image signal through a resistor array 30 forming G1 to G64 and one switch SW1 to SW64 driven according to the output signal of the decoder 10. It is composed of a switching unit (40).

The decoder 10 selectively outputs any one of 64 signals of '000000' to '111111' according to the applied 6-bit digital image information. That is, the signal output from the decoder 10 selectively turns on any one of the switches SW1 to SW64 of the switching unit 40 electrically connected to the decoder 10. The gray scale voltages G1 to G64 corresponding to the image information are output as image signals via the switches SW1 to SW64.

That is, the conventional digital-to-analog converting unit selectively outputs a signal according to the digital image information applied to the decoder 10, and according to the signal of the decoder 10 of the switching unit 40. The switches SW1 to SW64 are selectively turned on, and a gray scale voltage having an analog form corresponding to the turned on switches SW1 to SW64 is outputted as an image signal through the switches SW1 to SW64.

Recently, liquid crystal displays have been applied to many products due to advantages such as clear image quality and low power consumption. Liquid crystal displays are also widely used in small mobile products such as mobile phones. Since these small products are continuously developed as miniaturized and light weight products, the liquid crystal display devices mounted therein must also be miniaturized. However, as described above, since the conventional digital-to-analog converter needs to output 64 signals from the decoder in order to convert 6-bit digital image information into analog image information, the internal structure of the decoder is complicated and the circuit area becomes large. There was this. Therefore, there is a limitation in miniaturization of the product.

The present invention has been devised to solve the conventional problems as described above, and an object of the present invention is to reduce the area to be applied to small products such as mobile phones while processing the same amount of image information as in the prior art. To provide.

The driving unit of the liquid crystal display device for achieving the object of the present invention as described above is to receive the image information excluding the least significant bit (LSB) and to selectively output a signal corresponding to the image information; A data selector configured to output at least one driving signal according to the signal output from the decoder and the least significant bit of the image information; A resistance array unit for forming an applied gamma voltage into a plurality of gray voltages through a plurality of resistors; It is composed of a plurality of switches, and at least one switch is selectively driven by a drive signal of the data selection unit is configured to include a switching unit for receiving at least one gray voltage from the resistance array unit to output an image signal.

The characteristics of the present invention as described above is to achieve the same performance as the conventional state in the state easily mounted in the small product by reducing the overall area while allowing the driving unit of the liquid crystal display device to process the same image information as the conventional.

Hereinafter, the driving unit of the liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

3 is a diagram showing the configuration of a digital-analog converter according to the present invention.

Referring to FIG. 3, the digital-to-analog converter receives the image information except the least significant bit and selectively outputs a signal corresponding to the image information, and the lowest level of the signal and the image information of the decoder 110. A data selector 120 for outputting at least one driving signal PS1 to PS32 according to a bit, a resistor array unit 130 for forming a gamma voltage applied through a plurality of resistors into a plurality of gray voltages, and a plurality of At least one switch SW1 to SW32 is selectively driven by the driving signals PS1 to PS32 of the data selector 120 to receive the gray voltage of the resistor array 130. It is configured to include a switching unit 140 for outputting.

The decoder 110 receives 5-bit digital image information excluding the least significant bit (LSB) and selectively outputs one of 32 signals. Here, 32 different pieces of information may be represented as 5 bit image information except the least significant bit of the 6 bit image information. As described above, since the decoder 110 processes image information of which 1 bit is reduced as compared with the conventional process of 6-bit image information, half the data amount is reduced, thereby simplifying the internal configuration of the decoder 110.

By the way, the 32 signals selectively output from the decoder 110 cannot display the same 64 gradation image as before. Accordingly, the data selector 120 is provided to enable the display of 64 gray levels by the organic operation with the decoder 110. Here, the least significant bit is the last bit for displaying digital image information, and the data selector 120 is operated by receiving the least significant bit.

The data selector 120 receives the signal input from the decoder 110 and the least significant bit of the image information and transmits at least one driving signal PS1 to PS32 to the switches SW1 to SW32 of the switching unit 140. Is optionally applied. At this time, one or the plurality of switches SW1 to SW32 are driven by the driving signals PS1 to PS32. The switches SW1 to SW32 may use a device such as a thin film transistor.

As described above, the switches SW1 to SW32 that are turned on are applied with corresponding gray voltages G1 to G32 and output as image signals. If there are a plurality of drive signals PS1 to PS32 outputted from the data selector 120, the same number of switches SW1 to SW32 as the number of the drive signals PS1 to PS32 is driven to generate a plurality of gray levels. As the voltages G1 to G32 are applied through the switches SW1 to SW32, the plurality of gray voltages G1 to G32 applied through the electrically conductive switches SW1 to SW32 are adjusted to one voltage level. Is output. That is, when different voltages are applied through the same line, they are output as one voltage having an intermediate level.

The internal configuration and operation of the data selection unit 120 as described above are described in detail.

4A is a diagram showing a logic configuration of a data selection unit according to the present invention, and FIG. 4B is a truth table showing operation results according to the logic configuration of FIG. 4A.

Referring to the drawing, the data selector 220 may include a first NAND-gate 251 that operates according to a least significant bit of an image signal and a signal of a decoder separately applied, and is output from the decoder. An inverter 253 for inverting and outputting a signal, and a second NAND-gate 252 operating according to the output signal of the first NAND-gate 251 and the output signal of the inverter 253.

The operation of the data selector 220 configured as described above is as follows. Here, the description of the individual operation of each gate will be omitted.

First, only the N-1th signal D _n-1 is applied with a high potential from the decoder, and the Nth signal D _n and the N + 1 _th signal D _{n + 1} are low potential LOW. When the least significant bit LSB of the image signal is applied at a low potential, only the N-1th driving signal PS _n-1 is output at high potential in the data selection unit 220, and the remaining Nth driving signal is output. PS _n and the N + 1th driving signal PS _{n + 1} are output at a low potential. At this time, the high potential is displayed as '1' on the truth table, the low potential is displayed as '0' on the truth table.

The N-1 _th switch SW _n-1 is driven by the high potential N-1 _th driving signal PS _n-1 output from the data selector 220 to generate the N-1 _th gray voltage G _{n. -1)} for outputting an image signal, which is applied over the low-potential N-th drive signal (PS _n) and (N + 1) driving signal (the N-th switches (SW _n) and a (N + 1) switch in accordance with the PS _{n + 1)} (SW _{n + 1} ) remains turned off. This operation is shown in the truth table of FIG. 4B.

Next, only the N- _th signal D _n-1 is applied at a high potential HIGH, and the N- _th signal D _n and the N- _{th +1} signal D _{n + 1} are low-potential LOW. When the least significant bit LSB of the image signal is applied at a high potential, the data selector 220 is operated by the operations of the first NAND gate 251, the second NAND gate 252, and the inverter 253. In this case, the N- _th driving signal PS _n-1 and the N _-th driving signal PS _n are output at high potential, and only the N + 1th driving signal PS _{n + 1} is output at low potential. The N- _th switch SWn-1 and the N- _th switch of the switching unit by the high potential N-1 driving signal PS _n-1 and the N _th driving signal PS _n output from the data selection unit 220. The N switch SWn is turned on. At this time, the N-1 gray voltage Gn-1 and the Nth gray voltage Gn applied through the turned-on N-1 switch SWn-1 and the N-th switch SWn are intermediate voltages. Level is adjusted so that the voltage of the gray level higher than the N-th gray voltage Gn-1 and lower than the N-th gray voltage Gn is output as an image signal.

Next, the N signal (D _n) only is applied to the high potential (HIGH), the N-1 signals (D _n-1) and (N + 1) signals (D _{n + 1)} is applied at a low potential (LOW) When the least significant bit LSB of the image signal is applied at a low potential, the data selector 220 operates by the first NAND-gate 251, the second NAND-gate 252, and the inverter 253. The Nth driving signal PS _n is output at high potential, and the N-1th driving signal PS _n-1 and the N + 1th driving signal PS _{n + 1} are output at low potential. In addition, only the N _th switch SWn of the switching unit is turned on by the high potential N _th driving signal PS _n output from the data selector 220 so that the N _th gray voltage G _n is set to the N _th gray level voltage G _n . It is output as an image signal via the switch SWn.

As described above, the data selector 220 may include a driving signal (D _{n-1 to} D _{n + 1} ) selectively applied from the decoder and a driving signal applied to the switching unit according to the least significant bit LSB of the image signal. PS _{n-1 to} PS _{n + 1} ) is determined. That is, the signal D _{n-1 to} D _{n + 1} selectively applied from the decoder outputs only one driving signal PS _{n-1 to} PS _{n + 1 at high} potential through the data selector 220. By selectively driving one switch SW _{n-1 to} SW _{n + 1} , one gray voltage Gn-1 to Gn + 1 is applied. At this time, since the decoder processes image information excluding the least significant bit, the number of selectable gradations is half the conventional one.

The data selector 220 is provided to process the same amount of image information as conventionally by supplementing the number of gray levels selectable by the decoder, and a plurality of high potential driving signals depending on the potential of the image signal least significant bit (LSB). by outputting the _{(PS n-1 ~PS n +} 1), turned ondoen plurality of switches to output the intermediate gray level voltages of a plurality of gray scale voltages is applied via the receiving _{(SW n-1 ~SW n +} 1) into an image signal Can be.

Accordingly, the decoder outputs a signal by processing the reduced image information than before, and the data selector 220 outputs a driving signal based on the least significant bit LSB of the image information and the signal output from the decoder, thereby providing a plurality of gray levels. The halftone voltage is formed through the voltage. In this case, through a plurality of gray scale voltage to be applied through a combination of the switches _{(SW n-1 ~SW n +} 1) the gray scale voltages and the switches _{(SW n-1 ~SW n +} 1) it is applied separately over The halftone voltages formed can be obtained.

On the other hand, when the image information to be processed in the decoder is reduced, the circuit configuration of the decoder is simplified by that amount, so that the circuit area is also reduced. The data selector 220 provided in the present invention has a simple configuration and does not significantly increase the area of the driver of the liquid crystal display.

In addition, the two NAND-gates 251 and 252 and one inverter 253 in the data selector 220 are presented as one embodiment. The data selector may be a combination of gates other than the NAND-gates 251 and 252. 220 may be configured.

As described above, the driving unit of the liquid crystal display device of the present invention selects a gradation voltage based on image information excluding the least significant bit, and selects a plurality of gradation voltages selected by the decoder to form an intermediate gradation voltage. The same image information as the conventional one can be processed.

In addition, since the decoder having reduced image information to be processed has a simple circuit configuration and a reduced area, the decoder can reduce the area of the liquid crystal display driver and can be easily mounted on small products such as mobile phones.

1 is a block diagram schematically showing the configuration of a data driver of a liquid crystal display device.

2 is a diagram showing a configuration of a general digital-analog converter.

3 is a diagram showing the configuration of a digital-analog converter according to the present invention;

4A is a diagram showing the logic configuration of a data selection unit according to the present invention;

4B is a truth table showing operation results according to the logic configuration in FIG. 4A.

** Description of the symbols for the main parts of the drawings **

110: decoder 120: data selection unit

130: resistance array unit 140: switching unit

LSB: least significant bit PS1 to PS32 of image information: drive signal

G1 to G32: Gray voltage SW1 to SW32: Switch

Claims (8)

A decoder which receives image information except the least significant bit (LSB) and selectively outputs a signal corresponding to the image information; A data selector configured to output at least one driving signal according to the signal output from the decoder and the least significant bit of the image information; A resistance array unit for dropping the gamma voltage through a plurality of resistors to form a plurality of gray voltages; Comprising a plurality of switches, and at least one switch is selectively driven by a drive signal of the data selector, comprising a switching unit for receiving at least one gray voltage from the resistor array unit to output an image signal A drive unit of a liquid crystal display device characterized in that. The liquid crystal display driver of claim 1, wherein the data selector comprises a combination of a NAND gate and an inverter. The driving unit of claim 1, wherein the number of driving signals to be output is determined according to the potential of the least significant bit of the image information. 4. The driving unit of claim 3, wherein the data selection unit outputs one driving signal when the least significant bit is low potential. 4. The driving unit of claim 3, wherein the data selection unit outputs a plurality of driving signals when the least significant bit is high potential. 4. The driving unit of claim 3, wherein the plurality of switches are electrically connected when a plurality of driving signals are output from the data selection unit. 7. The liquid crystal display driver of claim 6, wherein a plurality of gray voltages are formed as one intermediate gray voltage through the plurality of conductive switches. The liquid crystal display driver of claim 1, wherein the switch is a thin film transistor.