KR20050060292A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same for compensating for variations in parasitic capacitance according to divided exposures and to improve image quality. First and second symmetrical patterns formed on the gate electrode branched from the wiring, the gate insulating film formed on the entire surface including the gate wiring, and on the predetermined portion of the gate wiring and the gate insulating film above the gate electrode, respectively; And a second semiconductor layer, data wirings perpendicular to the gate wirings, first and second source / drain electrodes symmetrical with each other in the up and down directions on the first and second semiconductor layers, and the data wirings. And a pixel electrode simultaneously connected to the first and second drain electrodes on the passivation layer. It is characterized by.

Description

Liquid crystal display device and manufacturing method thereof {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly to a liquid crystal display device and a manufacturing method thereof.

Recently, the liquid crystal display device, one of the flat panel display devices that are attracting attention, is an element that changes the optical anisotropy by applying an electric field to a liquid crystal that combines the liquidity and the optical properties of the crystal, which is applied to a conventional cathode ray tube. Compared with its low power consumption, small volume, large size, and high definition, it is widely used.

The LCD has a structure in which a color filter substrate as an upper substrate and a thin film transistor (TFT) substrate as a lower substrate are disposed to face each other, and a liquid crystal having dielectric anisotropy is formed therebetween. By switching the TFTs attached to the hundreds of thousands of pixels through the pixel selection address wiring, the voltage is applied to the corresponding pixels, and is driven in such a manner that the voltage charged to the corresponding pixels is maintained by the capacitor until the next address. do.

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to the related art will be described with reference to the accompanying drawings.

1A to 1C are process plan views of a liquid crystal display device according to the prior art, FIG. 2 is a plan view of a liquid crystal display device according to the prior art, and FIGS. 3A and 3B are enlarged thin film transistors in areas A and B of FIG. It is also.

As described above, the TFT substrate and the color filter substrate are bonded to each other with the liquid crystal layer interposed therebetween, and as illustrated in FIG. 2, the plurality of gate wirings 12 for transmitting a scan signal to the TFT substrate. ), A gate insulating film (not shown) formed on the entire surface including the gate wiring 12, insulated from the gate wiring, a semiconductor layer 14 formed on the gate insulating film at a predetermined portion of the gate wiring 12, A data line 15 formed on the semiconductor layer 14 to transmit an image signal, a thin film transistor TFT formed at an intersection point of the gate line 12 and the data line 15, and the thin film transistor. A protective film (not shown) formed on the front surface including the TFT and a pixel electrode 17 electrically connected to the thin film transistor are formed on the protective film.

In this case, the thin film transistor includes a gate electrode 12a which is a predetermined portion of the gate wiring 12, a gate insulating film formed on the gate electrode 12a, a semiconductor layer 14 formed on the gate insulating film, A source electrode 15a branched from the data line 15 and formed on the semiconductor layer 14, and a drain electrode 15b spaced apart from the source electrode 15a on the semiconductor layer 14 by a predetermined distance. It is composed. Here, a U-shaped TFT is suitable for a device having a large Cgs variation because the width and length (W / L) of the channel region change due to the misalignment of the pattern.

In this case, the semiconductor layer 14 may be formed in an island-shaped independent pattern on the gate electrode 12a or as shown in FIG. 2, not only above the gate electrode 12a but also below the data line 15. It may be extended.

The manufacturing method of the liquid crystal display device as described above is as follows.

First, as shown in FIG. 1A, a low resistance metal layer such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Cr) is deposited on a substrate, and then patterned to form a plurality of gate wirings 12. ) And the gate electrode 12a are formed.

Next, an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited at a high temperature on the entire surface including the gate wiring 12 to form a gate insulating film (not shown).

Subsequently, an amorphous silicon (a-Si: H) and an amorphous silicon (n + a-Si) doped with impurities are sequentially deposited on the gate insulating layer and then patterned to form a semiconductor layer overlapping the gate electrode 12a. 14). At this time, the semiconductor layer 14 may be extended so as to overlap the data line formed in a later step.

Subsequently, as shown in FIG. 1B, a low resistance metal such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and chromium (Cr) is deposited and patterned on the entire surface including the semiconductor layer 14. The data line 15 crossing the gate line 12 to define a unit pixel region, the source electrode 15a and the drain electrode 15b overlapping the semiconductor layer 14 above the gate electrode, and the A capacitor electrode 19 is formed on the gate wiring 12 to form a storage capacitor.

The source electrode 15a is branched from the data line 15 to have a U-shaped pattern, and the drain electrode 15b is inserted into the U-shape of the source electrode while maintaining a constant distance from the source electrode 15a. It is formed to have a pattern.

In this case, the semiconductor layer is formed under the data line 15, the source electrode 15a and the drain electrode 15b as described above.

Here, the laminated film of the gate electrode 12a, the gate insulating film, the semiconductor layer 14, and the source / drain electrodes 15a and 15b forms a thin film transistor.

Next, as shown in FIG. 1C, an organic insulating material such as BCB is coated on the entire surface including the data line 15 to form a protective film (not shown), and a portion of the protective film is removed to remove the drain electrode ( A first contact hole 18 exposing 15b) and a second contact hole 20 exposing the capacitor electrode 19 are formed.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the entire surface including the passivation layer to contact the drain electrode 15b through the first contact hole 18. The TFT substrate is completed by forming the pixel electrode 17.

In this case, the pixel electrode 17 extends to overlap the capacitor electrode 19 and contacts the capacitor electrode 19 through the second contact hole 20.

As described above, in order to drive the liquid crystal display device, various patterns such as a transistor and a capacitor are required. In order to form such a pattern, photo-lithography is generally used.

Photolithography technology uses a principle that changes a property by causing a chemical reaction when a specific photo-resist receives light, specifically, the step of depositing a film on a substrate and applying a photoresist thereon, Selectively exposing the photoresist using ultraviolet wavelengths, developing the exposed photoresist, etching the film using the developed photoresist as a mask, and A process consisting of peeling off the resist should be performed.

However, in the case where the liquid crystal display device is a large display device or a mother glass is large, a plurality of shots are performed by dividing the substrate into several zones due to the size of the exposure mask in the exposure process. Split exposure should be done. That is, the entire substrate is exposed by dividing the substrate into several zones and sequentially irradiating light to all the zones.

Therefore, a deviation occurs in the degree of overlap between the lower layer and the upper layer for each of the divided exposure regions, so that a stitch defect occurs in the exposure boundary portion (6 in FIG. 2), which is a boundary between the photo shot and the photo shot.

Specifically, the pattern alignment degree of the left region and the right region of the exposure boundary portion during the divided exposure may be different from each other. As a result, as shown in FIGS. 3A and 3B, a variation in the channel region length of the TFT occurs. . In FIG. 3A, the length of the area where the drain electrode 15b overlaps with the channel region of the semiconductor layer 14 is L, whereas in FIG. 3B, the source / drain electrode shifts upward and the drain electrode 15b becomes the semiconductor layer 14. L 'is the length of the area overlapping with the channel region.

This variation in channel region length causes variation in the on-current of the thin film transistor, resulting in a difference in charge rate of the pixel electrode.

Furthermore, the parasitic capacitance Cgs is different for each exposure zone, which causes a difference in the kick back voltage (ΔVp) of the pixel voltage, resulting in a difference in the voltage charged in the pixel electrodes of the left and right regions of the exposure boundary. Since the luminance of the left and right exposure areas is slightly different, a problem occurs in the stitch staining in which the exposure boundary is observed when the screen is driven. This is a major cause of deterioration of image quality when driving the device.

The present invention has been made to solve the above problems, and provides a liquid crystal display device and a method of manufacturing the same to improve the image quality by compensating for the parasitic capacitance variation of each region and the on-current variation of the thin film transistor according to the split exposure. Its purpose is.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a gate wiring formed on a substrate, a gate electrode branched from the gate wiring, a gate insulating film formed on the entire surface including the gate wiring, and a predetermined portion of the gate wiring. First and second semiconductor layers which are respectively formed on the gate insulating layer on the portion and the gate electrode and are symmetrical with each other in an up and down direction, a data line perpendicular to the gate wiring, and the first and second semiconductor layers First and second source / drain electrodes that are symmetrical to each other in the up and down directions, a passivation layer formed on the entire surface including the data line, and a pixel electrode simultaneously connected to the first and second drain electrodes on the passivation layer. Characterized in that the configuration.

That is, the first TFT channel is formed using the gate wiring as the gate electrode, and the second TFT channel is formed on the gate electrode extending from the gate wiring so as to be symmetrical with the first TFT channel in the up and down directions. Even if the pattern alignment degree of the source / drain electrodes of the left region and the right region of the substrate is different from each other, the area of the overlapping region of the gate electrode and the source / drain electrode for determining the Cgs is equalized to compensate for the Cgs deviation in each divided exposure region. It is characterized by.

According to another aspect of the present invention, there is provided a liquid crystal display device including a gate wiring formed on a substrate and having a concave groove at regular intervals, a gate insulating film formed on the front surface including the gate wiring, and the gate wiring on the gate insulating film. The first and second semiconductor layers symmetrically left and right symmetrical with respect to the concave grooves of the first and second semiconductor layers, the data wires perpendicular to the gate wirings, and the concave grooves of the gate wirings on the first and second semiconductor layers First and second source / drain electrodes that are symmetrical to each other, a passivation layer formed on the entire surface including the data line, and a pixel electrode that is simultaneously connected to the first and second drain electrodes through the passivation layer. It is characterized in that the configuration.

That is, the first and second TFT channels are formed using the gate wiring as the gate electrode, and the first and second TFT channels are formed in a symmetrical structure in the left and right directions with respect to the concave groove of the gate wiring. Even if the pattern alignment degree of the source / drain electrodes of the left region and the right region of the divided exposure boundary are different from each other, the area of the overlapping region of the gate electrode and the source / drain electrode to determine the Cgs is equal to the Cgs in each divided exposure region. It is characterized by compensating for the deviation.

Such a technical feature is applicable to liquid crystal display devices of various modes such as TN mode and IPS mode.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

The following description mainly relates to a thin film array substrate of a liquid crystal display device.

First embodiment

4 is a plan view of a liquid crystal display device according to a first exemplary embodiment of the present invention, FIGS. 5A and 5B are plan views and cross-sectional views of a thin film transistor in region C of FIG. 4, and FIGS. 6A and 6B are regions D of FIG. 4. Is a plan view and a cross-sectional view of a thin film transistor.

7A to 7C are process plan views of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 8 is a plan view of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention.

In the thin film array substrate of the liquid crystal display according to the present invention, as shown in FIG. 4, a plurality of gate lines 112 arranged in a line and perpendicularly intersect the gate lines 112 to define a unit pixel. A plurality of data lines 115 and first and second thin film transistors (first and second TFTs) formed at intersection points of the two lines in the unit pixel and symmetric with each other in the data line direction; The pixel electrode 117 is simultaneously connected to the first and second drain electrodes 135a and 135b of the first and second thin film transistors.

At this time, although not shown, a gate insulating film in which inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiOx) are deposited by PECVD is further formed between the gate wiring 112 and the data wiring 115. An inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited between the data line 115 and the pixel electrode 117, or an organic insulating material such as benzocyclobutene (BCB) or acrylic material is coated. A protective film is further formed.

On the other hand, the first and second thin film transistors (TFT) are formed to have a structure symmetrical with each other to compensate for the deviation of the Cgs for the entire panel, specifically, as shown in Figure 5a and 5b The first thin film transistor includes a gate insulating layer 113 formed on a predetermined portion of the gate wiring 112, the entire surface including the gate wiring 112, amorphous silicon (a-Si), and the like on the gate insulating film 113. A first semiconductor layer 114a formed by sequentially depositing n + a-Si implanted with impurities into amorphous silicon, and branched from the data line 115 to the first semiconductor layer 114a above the gate line 112. Each of the first source / drain electrodes 125a and 135a formed on the upper and lower electrodes is configured to control on / off of the voltage applied to the unit pixel. Here, a predetermined portion of the gate wiring 112 is used as the first gate electrode.

The second thin film transistor is a gate insulating film formed on the entire surface including the second gate electrode 112b formed by branching from the gate line 112 toward the data line 115 and the second gate electrode 112b. And a second semiconductor layer 114b formed by sequentially depositing amorphous silicon (a-Si) and n + a-Si ion-implanted with impurities on the gate insulating layer 113, and the data. The second source / drain electrodes 125b and 135b branched off the wiring 115 and formed on the second semiconductor layer 114b on the second gate electrode 112b respectively turn on / off the voltage applied to the unit pixel. Control off.

That is, a first TFT channel is provided by using a part of the gate wiring as a gate electrode, and a second TFT channel is formed on the gate electrode extending from the gate wiring so as to be symmetrical with the first TFT channel in the data wiring direction. Characterized in that.

The first and second semiconductor layers 114a and 114b may extend to overlap the data line 115, but are not formed between the gate line 112 and the second gate electrode 112b. This prevents exposure to light incident from the backlight. Otherwise, a fine current leaks at turn-off.

The first and second source electrodes 125a and 125b are U-shaped, respectively, and the first and second drain electrodes 135a and 135b are respectively formed of the first and second source electrodes 125a and 125b. It is formed into a shape that is inserted into the U-shape of the ends thereof are connected to each other and branched to the pixel electrode 117 side is connected to the pixel electrode. Therefore, the first and second drain electrodes 135a and 135b have a T shape.

For reference, the U-shaped TFT has a characteristic of maximizing on-current and improving the compensation of on-current variation and Cgs deviation due to the overlay variation.

As described above, the first thin film transistor formed on the gate wiring 112 and the second thin film transistor formed on the second gate electrode 112b branched from the gate wiring have a symmetrical structure in the up and down directions, and thus, in each divided exposure region. Compensate for the Cgs deviation of.

Specifically, as illustrated in FIGS. 5A and 5B, the first and second drain electrodes 135a and 135b of the first and second thin film transistors formed on the left side of the split exposure boundary unit 106 are L1. The first and second thin film transistors overlapping the gate wiring 112 and the second gate electrode 112b by the length of + L2 and formed on the right side with respect to the divisional exposure boundary part 106 (FIG. 4). As illustrated in FIGS. 6A and 6B, the second drain electrodes 135a and 135b overlap the gate wiring 112 and the second gate electrode 112b by the length of L1 '+ L2'.

Therefore, since L1 + L2 = L1 '+ L2', the area of the overlapping region of the gate electrode and the drain electrode for determining Cgs is the same even if the position of the source / drain electrode in each divided exposure area is shifted upward. Therefore, Cgs in each divided exposure area is compensated.

In addition, since the length of the channel region between the source electrode and the drain electrode is also compensated, the voltage charging rate for the pixel electrode 117 in each divided exposure region is also the same.

The gate wiring is used as the gate electrode of the first thin film transistor, and the first and second thin film transistors are disposed in the data wiring direction to fully utilize the data wiring to minimize the loss of the aperture ratio due to the TFT element.

Looking at the manufacturing method of the liquid crystal display device as follows.

First, as shown in FIG. 7A, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and chromium (Cr) having low specific resistance to prevent signal delay on a substrate. ), Metals such as titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) are deposited and patterned to form a plurality of gate wirings 112 and second gate electrodes 112b.

A predetermined portion of the gate wiring 112 is used as the first gate electrode, and the second gate electrode 112b is formed to branch from the gate wiring 112 in the data wiring direction.

Next, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is generally deposited on the entire surface including the gate wiring 112 by a plasma enhanced chemical vapor deposition (PECVD) method. A gate insulating film (not shown) is formed.

Subsequently, amorphous silicon (a-Si: H) is deposited on the entire surface including the gate insulating film at a high temperature and then patterned to form independent island-shaped first and second semiconductor layers 114a and 114b on the gate insulating film. The first semiconductor layer 114a is formed on a predetermined portion of the gate wiring 112, and the second semiconductor layer 114b is formed on the second gate electrode 112b.

The first and second semiconductor layers 114a and 114b may be formed to be limited to a predetermined portion of the gate wiring 112 and the second gate electrode 112a, and may be extended to overlap the data wiring to be formed later. It is okay. However, it is not formed between the gate wiring 112 and the second gate electrode 112b so as not to be exposed to incident light in the backlight.

Meanwhile, an overcoat layer doped with impurities may be further formed on the first and second semiconductor layers 114a and 114b to reduce contact resistance with a source / drain electrode to be formed later.

Subsequently, as shown in FIG. 7B, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), and molybdenum (Mo) are formed on the front surface including the first and second semiconductor layers 114a and 114b. ), Metals such as chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) are deposited and patterned to form a plurality of data lines 115, first and second source / drain electrodes ( 125a, 125b / 135a, 135b and capacitor electrodes 119 are formed.

The first source / drain electrodes 125a and 135a are formed on the first semiconductor layer 114a, and the second source / drain electrodes 125b and 135b are formed on the second semiconductor layer 114b. The first and second source electrodes 125a and 125b may be U-shaped, respectively, and the first and second drain electrodes 135a and 135b may be formed of the first and second source electrodes 125a and 125b. It is formed into a shape that is inserted into the U-shape.

As a result, first and second thin film transistors having a vertically symmetrical structure in the data wiring direction are completed. The first thin film transistor includes a predetermined portion of the gate wiring 112, a gate insulating layer 113, and a first semiconductor layer. 114a and U-shaped first source / drain electrodes 125a and 135a, and the second thin film transistor includes a second gate electrode 112b, a gate insulating film 113, and a second semiconductor layer ( 114b) and U-shaped second source / drain electrodes 125b and 135b.

Therefore, even if the source / drain electrodes are shifted for each of the divided exposure regions, the areas of the gate wiring and the second gate electrode overlapping with the drain electrodes become the same, thereby compensating for the Cgs variation of each divided exposure region.

In addition, the capacitor electrode 119 is formed in an independent pattern so as to overlap a predetermined portion of the gate line 112 to form a storage capacitor together with the gate line.

Next, as shown in FIG. 7C, an organic insulating material such as BCB (Benzocyclobutene) or an acrylic resin (acryl resin) is coated on the entire surface including the data line 115, or an inorganic insulating material such as SiNx or SiOx is deposited. To form a protective film (not shown). A portion of the passivation layer is removed to form a first contact hole 118 through which the first and second drain electrodes are integrated and a second contact hole 120 through which the capacitor electrode 119 is exposed. .

Thereafter, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface including the passivation layer and patterned to form first and second drain electrodes 135a through the first contact hole 118. A pixel electrode 117 is electrically connected to the 135b.

Ends of the first and second drain electrodes 135a and 135b are integrally connected to each other, branched toward the pixel electrode 117, and connected to the pixel electrode 117. It will have the shape of a child.

In this case, the pixel electrode 117 is formed to overlap the upper portion of the capacitor electrode, and is formed to be connected to the capacitor electrode 119 through the second contact hole 120 to apply a voltage to the capacitor electrode.

Meanwhile, as shown in FIG. 8, the thin film array substrate of the transverse electric field type liquid crystal display device according to the first embodiment includes a plurality of gate lines 212 arranged in a line and a plurality of gate lines 212 to define unit pixels. First and second thin film transistors having a vertically and symmetrical structure in the data wiring direction in the unit pixel in order to compensate for a plurality of vertically crossing data lines 215 and Cgs in each divided exposure area. TFTs, a common wiring 250 arranged in parallel with the gate wiring 212, and a plurality of common electrodes branched from the common wiring 220 and formed in parallel to the data wiring 215 in each pixel region. 251 and the first and second drain electrodes 235a and 235b of the first and second thin film transistors TFTs are simultaneously connected through the first contact hole 218 and the common electrode 251 in each pixel region. Pixel electrode 2 formed parallel to 53 is provided to control the liquid crystal array by the transverse electric field generated between the common electrode 251 and the pixel electrode 253 in the unit pixel.

Here, the first thin film transistor TFT may include a predetermined portion of the gate line 212 used as the first gate electrode, a gate insulating film (not shown) formed on the entire surface including the gate line 212, and the gate. A first U-shaped source / drain electrode formed on the insulating layer and the first semiconductor layer 214a formed on the first semiconductor layer 214a on the gate line 212 by branching from the data line 215. 225a and 235a, and the second thin film transistor includes a gate insulating film formed on the entire surface including the second gate electrode 212b and the second gate electrode 212b branched from the gate wiring 212; A second U-shaped second semiconductor layer 214b formed on the gate insulating layer and the second semiconductor layer 214b formed on the second semiconductor layer 214b on the second gate electrode 212b by branching from the data line 215. Source / Drain It consists of electrodes 225b and 235b to control the on / off of the voltage applied to the unit pixel.

Here, the first and second drain electrodes 235a and 235b are formed in a shape of being inserted into the U-shape of the first and second source electrodes 225a and 225b, and the ends thereof are connected to each other and branched to the pixel electrode side. And is connected to the pixel electrode 253. Accordingly, the first and second drain electrodes 235a and 235b have a T shape.

That is, a first TFT channel is provided by using a part of the gate wiring as a gate electrode, and a second TFT channel is formed on the gate electrode extending from the gate wiring so as to be symmetrical with the first TFT channel in the data wiring direction. Characterized in that.

In the above structure, even if a misalignment occurs because the shifted degree of the source / drain electrodes in each divided exposure region is different, the overlapping area of the drain electrode and the gate wiring is the same for the entire panel so that no stitch unevenness occurs.

Second embodiment

9 is a plan view of a liquid crystal display device according to a second exemplary embodiment of the present invention, FIGS. 10A and 10B are plan views and cross-sectional views of a thin film transistor in region E of FIG. 9, and FIGS. 11A and 11B are views of FIG. 9F. A plan view and a cross-sectional view of the thin film transistor in the region.

12A to 12C are process plan views of a liquid crystal display device according to a second embodiment of the present invention, and FIG. 13 is a plan view of a transverse electric field type liquid crystal display device according to a second embodiment of the present invention.

In the thin film array substrate of the liquid crystal display device according to the present invention, as shown in FIG. 9, a plurality of gate wirings 312 having concave grooves 312a arranged in a row at regular intervals and for defining unit pixels A plurality of first and second thin film transistors (first and second thin film transistors) having a structure in which the plurality of data lines 315 perpendicular to the gate lines and the unit pixel are formed at intersection points of the two lines in the unit pixel and are symmetrical in the gate wiring direction The second TFT and the first and second drain electrodes 335a and 335b of the first and second thin film transistors (first and second TFTs) are integrally formed and simultaneously connected to the pixel electrode 317. Is provided. Here, the concave groove 312a of the gate wiring is for forming two thin film transistors in the gate wiring.

In this case, although not shown, a gate insulating film in which inorganic insulating materials such as silicon nitride (SiNx) and silicon oxide (SiOx) are deposited by PECVD is further formed between the gate wiring 312 and the data wiring 315. Between the data line 315 and the pixel electrode 317, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited or an organic insulating material such as benzocyclobutene (BCB) or acrylic material is coated. A protective film is further formed.

In addition, a capacitor electrode 319 is further provided on the gate line 312 to form a storage capacitor along with the gate line and the gate insulating layer formed therebetween, and the capacitor electrode 319 has a second contact hole 320. Contacts the pixel electrode 317 to receive a voltage.

Meanwhile, the first and second thin film transistors TFT are formed to have symmetrical structures to compensate for the deviation of Cgs between the divided exposure regions, and the first and second thin film transistors are formed on the gate line 312. It is symmetrical with respect to the concave groove (312a) of.

Specifically, as shown in FIGS. 10A and 10B, the first thin film transistor may include a gate formed on a predetermined portion of the gate wiring 312 on the left side of the concave groove 312a and on the front surface including the gate wiring 312. An insulating film 313, a first semiconductor layer 314a formed by sequentially depositing amorphous silicon (a-Si) and n + a-Si ion-implanted with impurities on the gate insulating film 313, and The first source / drain electrodes 325a and 335a which are branched from the data line 315 and formed on the first semiconductor layer 314a on the gate line 312, respectively, turn on / off the voltage applied to the unit pixel. To control. Here, a predetermined portion of the gate wiring 312 on the left side of the concave groove 312a is used as the first gate electrode.

The second thin film transistor may include a predetermined portion of the gate line 312, a gate insulating layer 313 formed on the entire surface including the gate line 312, and amorphous silicon (a−) on the gate insulating layer 313. A second semiconductor layer 314b formed by sequentially depositing n + a-Si ion-implanted with impurity into Si) and amorphous silicon, and formed on the second semiconductor layer 314b branched from the data line 315. The second source / drain electrodes 325b and 335b control the on / off of the voltage applied to the unit pixel. Here, a predetermined portion of the gate wiring 312 is used as the second gate electrode.

That is, the first TFT channel is provided by using a part of the gate wiring as the gate electrode, and the second TFT channel is provided by using the gate wiring at the other position as the gate electrode based on the concave groove 312a of the gate wiring. The first TFT channel and the second TFT channel may be symmetrical in the gate wiring direction. Accordingly, the first and second thin film transistors are symmetrical with respect to the concave groove 312a of the gate wiring 312.

Here, the first and second semiconductor layers 314a and 314b may extend to overlap the data line 315, but are not formed between the first and second thin film transistors so that light incident from the backlight is generated. Not to be exposed to. That is, the first and second semiconductor layers 314a and 314b are formed so as not to protrude out of the concave groove 312a of the gate wiring. Otherwise, a fine current leaks at turn-off.

The first and second source electrodes 325a and 325b are each U-shaped, but are integrally connected to each other to transmit data signals, and the first and second drain electrodes 335a and 335b are respectively connected to the first. The second source electrodes 325a and 325b are formed in a shape of being inserted into the U-shape and their ends are connected to each other and branched to the pixel electrode 317 to be connected to the pixel electrode 317. Accordingly, the first and second drain electrodes 335a and 335b have a T shape.

For reference, the U-shaped TFT has a characteristic of maximizing on-current and improving the compensation of on-current variation and Cgs deviation due to the overlay variation.

As described above, the first and second thin film transistors formed on the right and left sides of the concave groove 312a of the gate wiring 312 and having a symmetrical structure compensate for the Cgs variation in each divided exposure area.

Specifically, as illustrated in FIGS. 10A and 10B, the first and second drain electrodes 335a and 335b of the first and second thin film transistors formed on the left side of the split exposure boundary unit 306 may be L3. The first and second drain electrodes 335a and 335b of the first and second thin film transistors overlapping the gate wiring 312 by the length of + L4 and formed on the right side with respect to the divided exposure boundary part 306 of FIG. 9. 11A and 11B overlap the gate wiring 312 by the length of L3 '+ L4'.

Therefore, since L3 + L4 = L3 '+ L4', even if the position of the source / drain electrodes in each divided exposure region is shifted, the area of the overlap region of the gate electrode and the drain electrode for determining Cgs becomes the same. Cgs in each divided exposure area are compensated.

In addition, since the channel region length between the source electrode and the drain electrode is also compensated, the voltage charging rate for the pixel electrode 317 in each divided exposure region is also the same.

Since the gate wiring is used as the gate electrode of the first and second thin film transistors, the structure of the wiring is simplified because there is no protruding structure of the gate electrode, and the first and second thin film transistors are arranged in the gate wiring direction so that the gate wiring is arranged. By utilizing it sufficiently, the area occupied by the TFT element is not necessary, and the aperture ratio is improved.

Looking at the manufacturing method of the liquid crystal display device as follows.

First, as shown in FIG. 12A, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and chromium (Cr) having low specific resistance to prevent signal delay on a substrate. ), Titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) metals are deposited and then patterned to form a plurality of gate wirings 312. At this time, the recessed portion 312a is formed at a predetermined interval by removing a predetermined portion of the gate wiring 312.

A predetermined portion of the gate wiring 312 on the left side is used as the first gate electrode based on the concave groove 312a, and a predetermined portion of the gate wiring on the right side of the gate wiring is used as the second gate electrode.

Next, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is generally deposited on the entire surface including the gate wiring 312 by a plasma enhanced chemical vapor deposition (PECVD) method. A gate insulating film (not shown) is formed.

Subsequently, amorphous silicon (a-Si: H) is deposited on the entire surface including the gate insulating film at a high temperature and then patterned to form independent island-shaped first and second semiconductor layers 314a and 314b on the gate insulating film. The first semiconductor layer 314a is formed at a predetermined portion of the gate wiring 312 on the left side based on the concave groove 312a, and the second semiconductor layer 314b is formed at a predetermined portion of the gate wiring on the right side. do.

The first and second semiconductor layers 314a and 314b may be formed only on the gate lines 312 on both sides of the concave groove 312a, and may be extended to overlap the data lines to be formed later. . However, it is not formed in the concave groove 312a of the gate wiring 312 so as not to be exposed to incident light from the backlight.

Meanwhile, an overcoat layer doped with impurities may be further formed on the first and second semiconductor layers 314a and 314b to reduce contact resistance with a source / drain electrode to be formed later.

12B, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), and molybdenum (Mo) are formed on the entire surface including the first and second semiconductor layers 314a and 314b. ), Metals such as chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW) are deposited and patterned to form a plurality of data lines 315, first and second source / drain electrodes ( 325a, 325b / 335a, and 335b and the capacitor electrode 319 are formed.

The first source / drain electrodes 325a and 335a are formed on the first semiconductor layer 314a, and the second source / drain electrodes 325b and 335b are formed on the second semiconductor layer 314b. The first and second source electrodes 325a and 325b have a U-shape, respectively, and the first and second drain electrodes 335a and 335b are formed of the first and second source electrodes 325a and 325b. It is formed into a straight shape inserted into the U-shape.

As a result, first and second thin film transistors having a symmetrical structure in the gate wiring direction are completed. The first thin film transistor includes a predetermined portion of the gate wiring 312 on the left side of the concave groove 312a and a gate insulating film 313. ), A first semiconductor layer 314a, and U-shaped first source / drain electrodes 325a and 135a, and the second thin film transistor is formed on the gate wiring 312 on the right side of the concave groove 312a. A predetermined portion, a gate insulating film 313, a second semiconductor layer 314b, and a U-shaped second source / drain electrodes 325b and 335b are formed.

Therefore, even if the source / drain electrodes are shifted for each divided exposure area, the area of the gate wiring overlapping the drain electrode becomes the same, thereby compensating for the Cgs variation of each divided exposure area.

In addition, the capacitor electrode 319 is formed in an independent pattern so as to overlap a predetermined portion of the gate line 312 to form a storage capacitor together with the gate line.

Next, as shown in FIG. 12C, an organic insulating material such as benzocyclobutene (BCB), an acrylic resin (acryl resin), or the like is deposited on the entire surface including the data line 315, or an inorganic insulating material such as SiNx or SiOx is deposited. To form a protective film (not shown). A portion of the passivation layer is removed to form a first contact hole 318 exposing the integrated first and second drain electrodes and a second contact hole 320 exposing the capacitor electrode 319. .

Thereafter, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the entire surface including the passivation layer to form first and second drain electrodes 335a through the first contact hole 318. A pixel electrode 317 is electrically connected to 335b.

Ends of the first and second drain electrodes 335a and 335b are integrally connected to each other, branched toward the pixel electrode 317, and connected to the pixel electrode 317. It has a shape.

In this case, the pixel electrode 317 is formed to overlap the upper portion of the capacitor electrode 319 and is formed to be connected to the capacitor electrode 319 through the second contact hole 320 to apply a voltage to the capacitor electrode. do.

Meanwhile, the thin film array substrate of the transverse electric field type liquid crystal display device according to the second embodiment has a structure as shown in FIG. 13, wherein the plurality of gate lines 412 and the plurality of gate lines 412 having concave grooves 412a at regular intervals are arranged in a row. A plurality of data lines 415 perpendicular to the gate lines to define unit pixels, and a plurality of data lines 415 perpendicular to the gate lines, and the gate lines in the unit lines in the direction of the gate lines within the unit pixels to compensate for the deviation of Cgs for each divided exposure area. The first and second thin film transistors TFT having a symmetrical structure with respect to the concave groove 412a, the common wiring 450 arranged in parallel with the gate wiring 412, and the common wiring 450. A plurality of common electrodes 451 branched in parallel to the data line 415 in each pixel region, and first and second first and second thin film transistors TFTs through the first contact hole 418. 2 drain electrode A pixel electrode 453 which is simultaneously connected to the 435a and 435b and formed to be parallel to the common electrode 451 in each pixel region, and is formed between the common electrode 451 and the pixel electrode 453 in the unit pixel. The liquid crystal array is controlled by the electric field.

Here, the first thin film transistor TFT may include a predetermined portion of the gate line 412 used as the first gate electrode, a gate insulating film (not shown) formed on the entire surface including the gate line 412, and the gate. U-shaped first and second sources formed on the insulating film and the first semiconductor layer 414a formed on the insulating film and on the first semiconductor layer 414a above the gate wiring 412. The second thin film transistor includes drain electrodes 425a and 435a, and the second thin film transistor includes a gate insulating film formed on a predetermined portion of the gate wiring 412, a front surface including the gate wiring 412, and a second insulating film formed on the gate insulating film. 2 semiconductor layers 414b and U-shaped second source / drain electrodes 425b and 435b branched from the data line 415 and formed on the second semiconductor layer 414b to be applied to the unit pixel. Voltage / Off controls.

Here, the first and second drain electrodes 435a and 435b are formed in a shape that is inserted into the U-shape of the first and second source electrodes 425a and 425b and the ends thereof are connected to each other to branch to the pixel electrode side. And connected to the pixel electrode 453. Therefore, the first and second drain electrodes 435a and 435b have a T shape.

In the above structure, even if a misalignment occurs because the shifted degree of the source / drain electrodes in each divided exposure region is different, the overlapping area of the drain electrode and the gate wiring is the same for the entire panel so that no stitch unevenness occurs.

Although not shown, the thin film array substrate having the structure has a liquid crystal layer bonded to the opposite substrate and disposed between the two substrates. The opposite substrate includes a black matrix for preventing light leakage and an R, G between the black matrix. And a color filter layer in which B color resists are formed in a predetermined order, an overcoat layer for protecting the color filter layer on the color filter layer and planarizing the surface of the color filter layer, and a pixel electrode formed on the overcoat layer. In addition, a common electrode for forming an electric field is formed.

In this case, when the liquid crystal display device is driven in a transverse electric field method, the common electrode is formed in parallel with the pixel electrode formed on the thin film array substrate to generate a horizontal electric field to control the alignment direction of the liquid crystal.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The liquid crystal display device and its manufacturing method according to the present invention as described above has the following effects.

First, the first and second thin film transistors respectively formed on the gate wiring or the gate electrode have symmetrical structures in the up, down direction, or the left and right directions, so that the position of the source / drain electrodes in each divided exposure area is shifted. Even if the overlap area of the gate electrode and the drain electrode which determines Cgs becomes the same, Cgs in each divided exposure area are compensated.

Second, since the channel region length between the source electrode and the drain electrode is also compensated, the voltage charging rate for the pixel electrode in each divided exposure region is also the same.

Therefore, the stitch defect in the divisional exposure boundary part is eliminated, and the image quality of the display element is improved.

Third, when arranging the first and second thin film transistors in the data wiring direction, the loss of the aperture ratio due to the TFT element is minimized by fully utilizing the data wiring.

Fourth, in the case of forming the first and second thin film transistors using the gate wiring as the gate electrode, the structure of the wiring is simplified because there is no protrusion structure of the gate electrode, and the first and second thin film transistors are arranged in the gate wiring direction. By making full use of the gate wiring, the occupancy area due to the TFT element is not necessary, and the aperture ratio is improved.

1A to 1C are process plan views of a liquid crystal display device according to the prior art.

2 is a plan view of a liquid crystal display device according to the prior art.

3A and 3B are enlarged views of a thin film transistor in areas A and B of FIG.

4 is a plan view of a liquid crystal display device according to a first embodiment of the present invention.

5A and 5B are plan views and cross-sectional views of a thin film transistor in region C of FIG.

6A and 6B are plan views and cross-sectional views of a thin film transistor in region D of FIG.

7A to 7C are process plan views of a liquid crystal display device according to a first embodiment of the present invention.

8 is a plan view of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention.

9 is a plan view of a liquid crystal display device according to a second embodiment of the present invention.

10A and 10B are plan views and cross-sectional views of a thin film transistor in region E of FIG.

11A and 11B are plan views and cross-sectional views of a thin film transistor in region F of FIG.

12A to 12C are process plan views of a liquid crystal display device according to a second embodiment of the present invention.

13 is a plan view of a transverse electric field type liquid crystal display device according to a second embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

106: exposure boundary portion 112: gate wiring

112b: second gate electrode 113: gate insulating film

114a and 114b: first and second semiconductor layers 115: data wiring

116: protective film 117: pixel electrode

118,120: first and second contact holes 119: capacitor electrode

125a, 125b: first and second source electrodes

135a, 135b: first and second drain electrodes

Claims (32)

A gate wiring formed on the substrate and a gate electrode branched from the gate wiring; A gate insulating film formed on the entire surface including the gate wiring; First and second semiconductor layers that are symmetrical with each other in a vertical direction on a predetermined portion of the gate wiring and the gate insulating layer on the gate electrode; A data line perpendicular to the gate line and first and second source / drain electrodes symmetrical with each other in the vertical direction on the first and second semiconductor layers; A protective film formed on an entire surface including the data line; And a pixel electrode connected to the first and second drain electrodes at the same time on the passivation layer. The liquid crystal display of claim 1, wherein the first and second semiconductor layers on the gate line and the gate electrode are not exposed to the outside of the gate line and the gate electrode. The liquid crystal display device according to claim 1, wherein the sum of the lengths of the first and second drain electrodes overlapping the first and second semiconductor layers is always constant. The semiconductor device of claim 1, further comprising: a first TFT including a predetermined portion of the gate wiring, a first semiconductor layer, and a first source / drain electrode; And the second TFT including the gate electrode, the second semiconductor layer, and the second source / drain electrode has a vertically and symmetrical structure in the data wiring direction. The method of claim 1, wherein the first and second source electrodes each have a U shape, and the first and second drain electrodes have a shape that is inserted into the U shape of the first and second source electrodes. A liquid crystal display device characterized by the above-mentioned. 6. The liquid crystal display device according to claim 5, wherein the first and second drain electrodes are connected to each other to form a T shape. The liquid crystal display device of claim 1, further comprising a semiconductor layer under the data line. The liquid crystal display of claim 1, further comprising a common electrode facing the pixel electrode on an inner surface of the counter substrate facing the substrate. The liquid crystal display of claim 1, further comprising a common electrode parallel to the pixel electrode to generate a transverse electric field. A gate wiring formed on the substrate and having concave grooves at regular intervals; A gate insulating film formed on the entire surface including the gate wiring; First and second semiconductor layers which are symmetrical with each other on the gate insulating layer with respect to the concave groove of the gate wiring; First and second source / drain electrodes symmetrically arranged with respect to the data line perpendicular to the gate line and the left and right symmetry with respect to the concave groove of the gate line on the first and second semiconductor layers; A protective film formed on an entire surface including the data line; And a pixel electrode penetrating through the passivation layer and simultaneously connected to the first and second drain electrodes. The liquid crystal display device of claim 10, wherein the first and second semiconductor layers are not exposed to the outside of the concave groove of the gate wiring. The liquid crystal display device according to claim 10, wherein the sum of the lengths of the first and second drain electrodes overlapping the first and second semiconductor layers is always constant. The semiconductor device of claim 10, further comprising: a first TFT including a predetermined portion of the gate wiring, a first semiconductor layer, and a first source / drain electrode; And a second TFT including a predetermined portion of the gate wiring, a second semiconductor layer, and a second source / drain electrode are symmetrical to each other in left and right directions with respect to the concave groove of the gate wiring. Display element. The method of claim 10, wherein the first and second source electrodes have a U shape, and the first and second drain electrodes have a shape inserted into the U shape of the first and second source electrodes. A liquid crystal display device characterized by the above-mentioned. 15. The liquid crystal display device according to claim 14, wherein the first and second drain electrodes are connected to each other to form a T shape. Forming a gate wiring and a gate electrode extending from the gate wiring on a substrate; Forming a gate insulating film on the entire surface including the gate wiring; Forming first and second semiconductor layers on a predetermined portion of the gate wiring and the gate insulating layer on the gate electrode; A data line perpendicular to the gate line, first and second source electrodes having a structure symmetrical with each other on the first and second semiconductor layers, and spaced apart from the first and second source electrodes at regular intervals. Forming a first and a second drain electrode; Forming a protective film on the entire surface including the data line; And forming a pixel electrode connected to the first and second drain electrodes on the passivation layer. 17. The method of claim 16, wherein the first and second semiconductor layers on the gate line and the gate electrode are formed so as not to be exposed to the outside of the gate line and the gate electrode. The method of claim 16, wherein the sum of the lengths of the first and second drain electrodes overlapping the first and second semiconductor layers is always constant. 17. The first TFT of claim 16, wherein the first TFT including a predetermined portion of the gate wiring, a first semiconductor layer, and a first source / drain electrode, And a second TFT including the gate electrode, the second semiconductor layer, and the second source / drain electrode, and having a vertically and symmetrical structure in the data wiring direction. . The method of claim 16, wherein the first and second source electrodes are formed to be U-shaped, and the first and second drain electrodes are formed to be inserted into the U-shaped portions of the first and second source electrodes. A method of manufacturing a liquid crystal display device, characterized in that. 21. The method of claim 20, wherein the first and second drain electrodes are connected to each other to form a T shape. The method of claim 16, wherein the first and second semiconductor layers are formed to be limited to only a predetermined portion of the gate wiring and an upper portion of the gate electrode, or extend to overlap the data wiring. . 17. The method of claim 16, further comprising a common electrode facing the pixel electrode on an inner surface of the counter substrate facing the substrate. 17. The method of claim 16, further comprising a common electrode parallel to the pixel electrode to generate a transverse electric field. Forming a gate wiring having concave grooves at regular intervals on the substrate; Forming a gate insulating film on the entire surface including the gate wiring; Forming first and second semiconductor layers on the gate insulating layer, the first semiconductor layer being symmetrical with respect to the concave groove of the gate wiring; Forming data lines perpendicular to the gate lines and first and second source electrodes and first and second drain electrodes on the first and second semiconductor layers so as to be symmetrical to each other; Forming a protective film on the entire surface including the data line; And forming a pixel electrode connected to the first and second drain electrodes on the passivation layer. 27. The method of claim 25, wherein the first and second semiconductor layers are formed in the concave grooves of the gate wiring so as not to be exposed. 27. The method of claim 25, wherein the sum of the lengths of the first and second drain electrodes overlapping the first and second semiconductor layers is always constant. The first TFT of claim 25, wherein the first TFT including a predetermined portion of the gate wiring, a first semiconductor layer, and a first source / drain electrode is formed. A second TFT including a predetermined portion of the gate wiring, a second semiconductor layer, and a second source / drain electrode may be formed to have left and right symmetry with respect to the concave groove of the gate wiring. Method of manufacturing a liquid crystal display device. 27. The method of claim 25, wherein the first and second source electrodes are formed to be U-shaped, and the first and second drain electrodes are formed to be inserted into the U-shaped portions of the first and second source electrodes. A method of manufacturing a liquid crystal display device, characterized in that. 30. The method of claim 29, wherein the first and second drain electrodes are connected to each other to form a T-shape. 27. The method of claim 25, wherein the first and second semiconductor layers are formed to be limited to only a predetermined portion of the gate wiring or extend so as to overlap the data wiring. 26. The method of claim 25, further comprising a common electrode parallel to the pixel electrode to generate a transverse electric field.