KR20050055946A - A method for forming a storage node of a semiconductor device - Google Patents
A method for forming a storage node of a semiconductor device Download PDFInfo
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- KR20050055946A KR20050055946A KR1020030089010A KR20030089010A KR20050055946A KR 20050055946 A KR20050055946 A KR 20050055946A KR 1020030089010 A KR1020030089010 A KR 1020030089010A KR 20030089010 A KR20030089010 A KR 20030089010A KR 20050055946 A KR20050055946 A KR 20050055946A
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- 238000003860 storage Methods 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000000231 atomic layer deposition Methods 0.000 claims description 28
- 238000004140 cleaning Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 235000011007 phosphoric acid Nutrition 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 239000002002 slurry Substances 0.000 description 3
- 238000005108 dry cleaning Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 or using NO Chemical compound 0.000 description 1
- 239000010909 process residue Substances 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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Abstract
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, The present invention relates to a method of forming a storage electrode of a semiconductor device,
반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 캐패시터를 형성하기 위하여, 저장전극용 도전층 상에 ALD 질화막을 증착하고 저장전극 영역을 매립하는 평탄화된 감광막을 도포한 다음, CMP 공정을 실시하며 상기 ALD 질화막 및 감광막을 제거하여 상기 저장전극 영역 내에 잔류물이 남지 않도록 함으로써 결함없이 예정된 크기의 저장전극을 형성할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다. In order to form a capacitor so as to secure a sufficient capacitance for high integration of the semiconductor device, an ALD nitride film is deposited on the storage electrode conductive layer, a planarized photoresist film filling the storage electrode region is applied, and then a CMP process is performed. By removing the ALD nitride film and the photoresist film so that no residue remains in the storage electrode region, a storage electrode having a predetermined size can be formed without defects, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device. Technology.
Description
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 특히 삼차원적 구조를 갖는 캐패시터를 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보하는데 있어서, 높은 에스펙트비 ( aspect ratio ) 에 따른 공정 잔류물로 인하여 유발되는 결함을 방지할 수 있도록 하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a storage electrode of a semiconductor device. In particular, in forming a capacitor having a three-dimensional structure to secure a sufficient capacitance for high integration of a semiconductor device, a process residue according to a high aspect ratio It relates to a technology that can prevent the defects caused by.
반도체소자가 고집적화되어 셀 크기가 감소됨에 따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell sizes are reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위 셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, ( Eo × Er × A ) / T ( 단, 상기 Eo 는 진공유전율, 상기 Er 은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량을 증가시키기 위하여, 하부전극인 저장전극의 표면적을 증가시켜 캐패시터를 형성하거나, 유전체막의 두께를 감소시켜 캐패시터를 형성하였다.Thus, the capacitance of the capacitor represented by (Eo × Er × A) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to achieve this, a capacitor is formed by increasing the surface area of the storage electrode, which is a lower electrode, or a capacitor is formed by decreasing the thickness of the dielectric film.
도 1 은 종래기술에 따라 형성된 반도체소자의 저장전극을 도시한 평면 셈사진으로서, 제조 공정 중에 사용된 감광막 및 화학기계연마 ( CMP ) 공정의 슬러리성 잔류물로 인한 결함이 유발된 것을 도시한다. FIG. 1 is a planar image showing a storage electrode of a semiconductor device formed according to the prior art, showing that defects are caused by a slurry residue of a photoresist film and a chemical mechanical polishing (CMP) process used during a manufacturing process.
도 1을 참조하면, 소자분리막, 게이트전극 및 비트라인과 같은 하부구조물이 구비되는 반도체기판 상에 저장전극 콘택플러그가 구비되는 하부절연층을 형성한다.Referring to FIG. 1, a lower insulating layer including a storage electrode contact plug is formed on a semiconductor substrate including lower structures such as an isolation layer, a gate electrode, and a bit line.
상기 하부절연층 상부에 식각장벽층 및 저장전극용 산화막을 적층한다. 이때, 상기 식각장벽층은 질화막으로 형성한다. An etch barrier layer and an oxide film for a storage electrode are stacked on the lower insulating layer. In this case, the etching barrier layer is formed of a nitride film.
그 다음, 저장전극 마스크를 이용한 사진식각공정으로 상기 저장전극용 산화막 및 식각장벽층을 식각하여 상기 저장전극 콘택플러그를 노출시키는 저장전극 영역을 형성한다.Then, the oxide layer and the etching barrier layer for the storage electrode are etched by the photolithography process using the storage electrode mask to form the storage electrode region exposing the storage electrode contact plug.
상기 저장전극 영역을 포함한 전체표면상부에 저장전극용 도전층을 일정두께 형성한다. 이때, 상기 저장전극용 도전층은 폴리실리콘으로 형성한다. A conductive layer for a storage electrode is formed to have a predetermined thickness on the entire surface including the storage electrode region. In this case, the storage electrode conductive layer is formed of polysilicon.
그 다음, 상기 저장전극 영역을 매립하는 감광막을 전체표면상부에 형성한다. Then, a photoresist film filling the storage electrode region is formed over the entire surface.
그리고, 상기 저장전극용 산화막을 노출시키는 평탄화식각공정인 CMP 공정을 실시한다. 이때, 셀 영역의 저장전극 영역 내에 저장전극으로 사용될 저장전극용 도전층이 남는다.A CMP process, which is a planar etching process for exposing the storage electrode oxide layer, is performed. At this time, the conductive layer for the storage electrode to be used as the storage electrode remains in the storage electrode region of the cell region.
그 다음, 상기 저장전극 영역 내의 감광막을 건식 세정방법으로 제거하고, 상기 저장전극용 산화막을 습식 세정방법으로 제거한다. Then, the photoresist film in the storage electrode region is removed by a dry cleaning method, and the oxide film for the storage electrode is removed by a wet cleaning method.
그러나, 상기 건식 세정 방법에 의하여 완전히 제거되지 않은 슬러리에 감광막 성분이 혼합되어 상기 습식 세정 공정시 저장전극 영역을 따고 상부로 올라와 결함을 발생시키게 된다. However, the photoresist component is mixed with the slurry that is not completely removed by the dry cleaning method, so as to pick up the storage electrode region in the wet cleaning process and move upwards to generate a defect.
또한, 상기 감광막 성분을 제거하기 위하여 습식 세정을 이용하는 경우는 상기 저장전극 영역의 크기가 작아 습식 세정액이 저장전극 영역 저부까지 침투하지 못하게 되는 모세관 현상이 유발된다. In addition, when wet cleaning is used to remove the photoresist component, the size of the storage electrode region is small, thereby causing a capillary phenomenon in which the wet cleaning liquid does not penetrate to the bottom of the storage electrode region.
이상에서 설명한 바와 같이 종래기술에 반도체소자의 저장전극 형성방법은, 저장전극의 분리를 위하여 사용되는 감광막의 완전한 제거가 어렵고 상기 저장전극의 분리를 위한 CMP 공정에 의한 슬러리성 결함이 유발되어 저장전극의 사용을 어렵게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시키며 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. As described above, the method of forming a storage electrode of a semiconductor device in the related art is difficult to completely remove the photoresist film used for separation of the storage electrode, and the slurry electrode is caused by a CMP process for separation of the storage electrode. Has a problem of making it difficult to use, lowering the characteristics and reliability of the semiconductor device, and making it difficult to integrate the semiconductor device.
본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 저장전극 영역에 매립되는 물질의 제거를 용이하게 실시할 수 있도록 하여 매립 물질로 인한 결함 유발을 억제할 수 있도록 함으로써 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems according to the related art, the present invention enables the removal of a material embedded in a storage electrode region to be easily performed to suppress the occurrence of defects caused by the buried material. And to provide a method of forming a storage electrode of the semiconductor device to improve the reliability and thereby high integration of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 저장전극 형성방법은, In order to achieve the above object, a method of forming a storage electrode of a semiconductor device according to the present invention includes:
반도체기판 상에 저장전극 콘택플러그가 구비되는 하부절연층을 형성하는 공정과,Forming a lower insulating layer having a storage electrode contact plug on the semiconductor substrate;
전체표면상부에 저장전극 콘택플러그를 노출시키는 저장전극 영역이 정의된 저장전극용 산화막을 형성하는 공정과,Forming an oxide film for a storage electrode having a storage electrode region in which a storage electrode contact plug is exposed on an entire surface thereof;
상기 저장전극 콘택플러그에 접속되는 저장전극용 도전층을 전체표면상부에 형성하는 공정과,Forming a conductive layer for a storage electrode connected to the storage electrode contact plug on an entire surface thereof;
상기 저장전극용 도전층 상에 ALD ( atomic layer deposition ) 질화막을 증착하는 공정과,Depositing an atomic layer deposition (ALD) nitride film on the conductive layer for the storage electrode;
상기 저장전극 영역을 매립하는 감광막을 전체표면상부에 형성하는 공정과,Forming a photoresist film filling the storage electrode region on the entire surface;
상기 저장전극용 산화막을 노출시키는 CMP 공정을 실시하고 상기 ALD 질화막 및 감광막을 제거하는 공정을 포함하는 것과,Performing a CMP process of exposing the oxide film for the storage electrode and removing the ALD nitride film and the photosensitive film;
상기 ALD 질화막은 10 ∼ 50 Å 두께로 형성하는 것과,The ALD nitride film is formed to a thickness of 10 to 50 mm 3,
상기 ALD 질화막은 NO, NO3 가스 및 TEOS를 이용하여 형성하거나 NO, NO3 가스 및 SiH4를 이용하여 형성하는 것과,The ALD nitride film is formed using NO, NO3 gas and TEOS, or using NO, NO3 gas and SiH4,
상기 ALD 질화막의 형성공정은 100 ∼ 200 ℃ 의 온도, 50 ∼ 200 mTorr 의 압력, 200 ∼ 1000 와트(watt)의 전력과 같은 조건을 갖는 Ar 및 N2 가스가 첨가된 플라즈마에서 를 형성하며 실시하는 것과,The process of forming the ALD nitride film is performed by forming in a plasma to which Ar and N2 gas are added, having conditions such as a temperature of 100 to 200 ° C., a pressure of 50 to 200 mTorr, and a power of 200 to 1000 watts. ,
상기 ALD 질화막과 감광막의 제거 공정은 습식세정방법을 실시하는 것과,The removal process of the ALD nitride film and the photoresist film is to perform a wet cleaning method,
상기 ALD 질화막과 감광막의 제거 공정은 H3PO4를 이용하여 5 ∼ 120 초 동안 실시하고, R(H2SO4+H2O2), BOE 및 N(NH4OH+H2O2+H2O) 의 혼합 용액을 이용하여 2 ∼ 60 초 동안 실시하는 습식 세정 방법으로 실시하는 것과,The removal process of the ALD nitride film and the photoresist film is performed for 5 to 120 seconds using H 3 PO 4, and for 2 to 60 seconds using a mixed solution of R (H 2 SO 4 + H 2 O 2), BOE, and N (NH 4 OH + H 2 O 2 + H 2 O). With the wet washing method to say,
상기 ALD 질화막과 감광막의 제거 공정은 H3PO4 용액으로 120 ∼ 600 초 동안 습식 세정하는 것을 특징으로 한다. The removal process of the ALD nitride film and the photosensitive film is characterized in that the wet cleaning for 120 to 600 seconds with H 3 PO 4 solution.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 저장전극 형성방법을 도시한다. 2A to 2F illustrate a method of forming a storage electrode of a semiconductor device according to an embodiment of the present invention.
도 2a 를 참조하면, 소자분리막(도시안됨), 게이트전극(도시안됨), 비트라인(도시안됨) 및 저장전극 콘택플러그와 같은 하부구조물이 구비되는 반도체기판(11) 상에 식각장벽층(도시안됨) 및 저장전극용 산화막(13)을 적층한다. Referring to FIG. 2A, an etch barrier layer (not shown) is formed on a semiconductor substrate 11 having substructures such as an isolation layer (not shown), a gate electrode (not shown), a bit line (not shown), and a storage electrode contact plug. No) and the oxide film 13 for the storage electrode are laminated.
이때, 상기 식각장벽층은 질화막으로 형성한다. In this case, the etching barrier layer is formed of a nitride film.
그 다음, 저장전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 저장전극용 산화막(13) 및 식각장벽층을 식각하여 상기 저장전극 콘택플러그를 노출시키는 저장전극 영역(50)을 형성한다.Next, the storage electrode region 50 exposing the storage electrode contact plug is formed by etching the storage electrode oxide layer 13 and the etching barrier layer by a photolithography process using a storage electrode mask (not shown).
도 2b를 참조하면, 상기 저장전극 영역(50)을 포함한 전체표면상부에 저장전극용 도전층(도시안됨)을 일정두께 형성한다. 이때, 상기 저장전극용 도전층은 폴리실리콘으로 형성한다.Referring to FIG. 2B, a conductive layer for a storage electrode (not shown) is formed on the entire surface including the storage electrode region 50 at a predetermined thickness. In this case, the storage electrode conductive layer is formed of polysilicon.
도 2c를 참조하면, 전체표면상부에 ALD ( atomic layer deposition ) 질화막(17)을 10 ∼ 50 Å 두께로 형성한다. Referring to FIG. 2C, an ALD (atomic layer deposition) nitride film 17 is formed on the entire surface with a thickness of 10 to 50 GPa.
이때, 상기 ALD 질화막(17)은 NO, NO3 가스 및 TEOS를 이용하여 형성하거나 NO, NO3 가스 및 SiH4를 이용하여 형성한다. In this case, the ALD nitride film 17 is formed using NO, NO 3 gas and TEOS, or is formed using NO, NO 3 gas and SiH 4.
또한, 상기 ALD 질화막(17)의 형성공정은 100 ∼ 200 ℃ 의 온도, 50 ∼ 200 mTorr 의 압력, 200 ∼ 1000 와트(watt)의 전력과 같은 조건에 Ar 및 N2 가스를 첨가하여 플라즈마를 형성하며 실시한 것이다. In addition, the ALD nitride film 17 is formed by adding Ar and N2 gas under conditions such as a temperature of 100 to 200 ° C., a pressure of 50 to 200 mTorr, and a power of 200 to 1000 watts to form a plasma. It was done.
도 2d를 참조하면, 상기 저장전극 영역(50)을 매립하는 감광막(19)을 전체표면상부에 평탄화시켜 형성한다. Referring to FIG. 2D, the photoresist film 19 filling the storage electrode region 50 is planarized on the entire surface.
도 2e를 참조하면, 상기 저장전극용 산화막(13)을 노출되도록 평탄화식각공정을 실시한다. 이때, 상기 평탄화식각공정은 CMP ( chemical mechanical polishing ) 공정으로 실시한다.Referring to FIG. 2E, a planarization etching process is performed to expose the oxide layer 13 for the storage electrode. In this case, the planarization etching process is performed by a chemical mechanical polishing (CMP) process.
연속적으로, 상기 감광막(19) 및 ALD 질화막(17)을 습식 세정 방법으로 제거한다. 이때, 상기 ALD 질화막(17)의 제거 공정은 상기 저장전극 영역(50)에서의 모세관 현상을 없애는 통로를 형성하는 역할을 한다. Subsequently, the photosensitive film 19 and the ALD nitride film 17 are removed by a wet cleaning method. At this time, the removal process of the ALD nitride film 17 serves to form a passage to eliminate the capillary phenomenon in the storage electrode region (50).
여기서, 상기 ALD 질화막(17) 및 감광막(19)의 습식 세정 공정은 다음과 같은 방법으로 실시한다. Here, the wet cleaning process of the ALD nitride film 17 and the photosensitive film 19 is performed by the following method.
첫째, H3PO4를 이용하여 5 ∼ 120 초 동안 실시하고, R(H2SO4+H2O2), BOE 및 N(NH4OH+H2O2+H2O) 의 혼합 용액을 이용하여 2 ∼ 60 초 동안 실시하는 습식방법으로 실시하는 것이다. First, it is carried out for 5 to 120 seconds using H3PO4, it is carried out by a wet method for 2 to 60 seconds using a mixed solution of R (H2SO4 + H2O2), BOE and N (NH4OH + H2O2 + H2O). .
둘째, H3PO4 용액 단독으로 120 ∼ 600 초 동안 실시하는 것이다. Second, the H3PO4 solution alone is performed for 120 to 600 seconds.
도 2f를 참조하면, 상기 저장전극용 산화막(13)을 제거하여 저장전극(21)을 형성한다. Referring to FIG. 2F, the storage electrode 21 is removed to form the storage electrode 21.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, ALD 질화막을 저장전극용 도전층 상에 형성하고 저장전극 영역을 매립하는 감광막을 형성한 다음, CMP 공정과 ALD 질화막 및 감광막 세정공정으로 상기 저장전극 영역에 잔류물을 남기지 않고 후속 공정을 실시함으로써 공정의 안정성을 향상시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키며 반도체소자의 고집적화에 따른 정전용량을 확보할 수 있도록 하는 효과를 제공한다. As described above, in the method of forming the storage electrode of the semiconductor device according to the present invention, the ALD nitride film is formed on the conductive layer for the storage electrode, and the photoresist film is formed to fill the storage electrode region. Then, the CMP process and the ALD nitride film and the photoresist film are cleaned. By performing a subsequent process without leaving a residue in the storage electrode region as a process, it is possible to improve the stability of the process, thereby improving the characteristics and reliability of the semiconductor device and to secure the capacitance due to the high integration of the semiconductor device. to provide.
도 1 은 종래기술에 따라 형성된 반도체소자의 저장전극들을 도시한 평면도.1 is a plan view showing the storage electrodes of a semiconductor device formed according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 반도체소자의 저장전극 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11 : 반도체기판 13 : 저장전극용 산화막11: semiconductor substrate 13: oxide film for storage electrode
15 : 저장전극용 도전층 17 : ALD 질화막15 conductive layer for storage electrode 17 ALD nitride film
19 : 감광막 21 : 저장전극 19 photosensitive film 21 storage electrode
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