KR20050054594A - Input buffer circuit having direct current voltage detecting circuit - Google Patents

Abstract

An input buffer circuit having a direct current voltage detection circuit and a direct current voltage detection circuit is disclosed. The DC voltage detection circuit according to the embodiment of the present invention includes a receiver, a first controller, a second node, and a second controller. The receiver receives an input signal and controls the voltage level of the first node. The first controller removes the DC current flowing through the receiver when the voltage level of the input signal is greater than or equal to a predetermined voltage level. The second node has a voltage level opposite to the voltage level of the first node. The second control unit controls the voltage characteristic of the second node to have a hysteresis characteristic. The first controller is a diode-type transistor having a source connected to a power supply voltage and a gate and a drain connected to each other. The input buffer circuit including the DC voltage detection circuit and the DC voltage detection circuit according to the present invention has the advantage of reducing unnecessary DC current and removing the influence of noise to some extent even when the voltage level of the input signal is changed by noise. There is this.

Description

Input buffer circuit having a direct current voltage detecting circuit and a direct current voltage detecting circuit.

The present invention relates to an input buffer circuit having a direct current voltage detection circuit and a direct current voltage detection circuit, and more particularly, to an input buffer circuit having a direct current voltage detection circuit capable of reducing current consumption and reducing the influence of noise.

In the case of the input buffer circuit used in the semiconductor chip, the initial operation is set to be performed by a power up sequence. That is, a time sufficient to allow a DC voltage level such as a power supply voltage VDD, an output driver power supply voltage VDDQ, and a reference voltage VREF used inside the semiconductor chip to reach a predetermined voltage level (about After 200us), the input buffer circuit accepts a clock signal or a command to perform an internal operation.

However, according to the internal circuit of the input buffer circuit, before the DC voltage levels such as the power supply voltage VDD, the output driver power supply voltage VDDQ, and the reference voltage VREF reach a predetermined voltage level. The input buffer circuit may receive a clock signal or command to increase the internal DC current or generate an invalid output value and cause a malfunction.

In order to eliminate this phenomenon, a method of configuring the CMOS input buffer and the SSTL input buffer separately according to the input signal applied to the input buffer circuit and allowing the input buffer circuit to operate regardless of the voltage level of the reference voltage is used.

Alternatively, a method of recognizing a voltage level of an input signal applied to an input buffer circuit using a DC voltage detection circuit capable of adjusting a size ratio of a PMOS transistor and an NMOS transistor is also used.

1 is a circuit diagram showing an input buffer circuit including a conventional DC voltage detection circuit.

FIG. 2 is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 1 and the second node voltage level.

Referring to FIG. 1, the input buffer circuit 100 includes a DC voltage detection circuit 110, a buffer signal generator 120, and a buffer unit 130.

The DC voltage detection circuit 110 measures the voltage level of the input signal DC_IN and outputs an input control signal INCTRL. The buffer signal generator 120 generates a buffer signal BUFS for turning on or off the buffer 130 in response to the input control signal INCTRL and the buffer control signal BUFCTRL.

The buffer unit 130 receives the command CMD and outputs the command CMD in response to the buffer signal BUFS (OUT_CMD).

The DC voltage detection circuit 110 may include a first resistor R connected to the power supply voltage VDD, a first connection between the resistor R, and the ground voltage VSS, and receiving an input signal DC_IN through a gate. An inverter INV for inverting the voltage levels of the second transistors TR1 and TR2 and the first node N1 and outputting it as an input control signal INCTRL is provided.

The first node N1 is a node in which the first transistor TR1 and the second transistor TR2 are connected to each other. The output terminal of the inverter INV is the second node N2.

The DC voltage detection circuit 110 controls the voltage level of the first node N1 by adjusting the size of the resistor R and the size of the first and second transistors TR1 and TR2. The voltage level of the second node N2 fluctuates inversely depending on the voltage level of the first node N1.

It is assumed that the voltage level of the input signal DC_IN for the input buffer circuit 100 to operate normally is the first voltage level. When the voltage level of the input signal DC_IN is equal to or less than the first voltage level, the first transistor TR1 is turned on, the second transistor TR2 is turned off, and the first node N1 is at a high level.

Then, the second node N2 is at a low level. In FIG. 2, the low voltage level of the input signal DC_IN indicates that the voltage level of the second node N2 is low.

When the voltage level of the input signal DC_IN is equal to or greater than the first voltage level, the second transistor TR2 is turned on so that the first node N1 becomes a low level. Then, the second node N2 is at a high level. In FIG. 2, the voltage level of the input signal DC_IN indicates that the voltage level of the second node N2 is high.

The signal output from the second node N2 is the input control signal INCTRL. The buffer control signal BUFCTRL is a signal for controlling the operation of the buffer unit 130. When the input control signal INCTRL is at a high level and the buffer control signal BUFCTRL is at a high level, the buffer signal BUFS is at a low level, and the buffer unit 130 is turned on.

That is, the buffer unit 130 is turned on when the buffer control signal BUFCTRL is at a low level.

However, even if the buffer control signal BUFCTRL is at a high level, if the input control signal INCTRL is not at a high level, that is, if the voltage level of the input signal DC_IN does not exceed the first voltage level, the buffer unit 130 is turned on. Not.

When the buffer unit 130 is turned on, the buffer unit 130 receives the command CMD and outputs the output OUT_CMD.

However, when the voltage level of the input signal DC_IN is equal to or greater than the first voltage level, the first transistor TR1 is not turned off completely but remains weakly turned on. Therefore, there is a problem that the DC current I flows through the first transistor TR1 and the second transistor TR2.

In addition, when the input signal DC_IN is affected by noise, the voltage level of the second node N2 is also affected by the noise that the input signal DC_IN receives. That is, when the voltage level of the input signal DC_IN is close to the first voltage level, the voltage level of the second node N2 may be generated at a high level or may be generated at a low level due to noise.

As described above, the conventional input buffer circuit 100 has a problem in that the current consumption is increased by continuously flowing the DC current I and is also vulnerable to noise affecting the input signal DC_IN.

An object of the present invention is to provide a DC voltage detection circuit that can reduce the influence of current consumption and noise.

Another object of the present invention is to provide an input buffer circuit having a DC voltage detection circuit capable of reducing the influence of current consumption and noise.

The DC voltage detection circuit according to the embodiment of the present invention for achieving the above technical problem includes a receiver, a first controller, a second node and a second controller.

The receiver receives an input signal and controls the voltage level of the first node. The first controller removes the DC current flowing through the receiver when the voltage level of the input signal is greater than or equal to a predetermined voltage level.

The second node has a voltage level opposite to the voltage level of the first node. The second control unit controls the voltage characteristic of the second node to have a hysteresis characteristic.

The first controller is a diode-type transistor having a source connected to a power supply voltage and a gate and a drain connected to each other.

 The receiver includes a first transistor and a second transistor. The first transistor has a first end connected to the drain of the diode-type transistor, receives the input signal through a gate, and a second end connected to the first node.

The second transistor has a first end connected to the first node, receives the input signal to a gate, and a second end connected to a ground voltage.

The second controller may be a PMOS transistor having a first end connected to a power supply voltage, a gate connected to the second node, and a second end connected to the first node. The voltage characteristic of the second node is controlled according to a ratio of the size of the PMOS transistor to the size of the second transistor.

The second controller may be an NMOS transistor having a first end connected to a ground voltage, a gate connected to the second node, and a second end connected to the first node. The voltage characteristic of the second node is controlled according to a ratio of the size of the NMOS transistor to the size of the second transistor.

In the first controller, a plurality of diode-type transistors having gates and drains connected to each other may be connected in series with a power supply voltage.

According to another aspect of the present invention, an input buffer circuit includes a DC voltage detection circuit, a buffer signal generator, and a buffer unit.

The DC voltage detection circuit generates an input control signal when the voltage level of the input signal becomes above a predetermined voltage level. The buffer signal generator generates a buffer signal in response to the input control signal and the buffer control signal.

The buffer unit receives a command and outputs the command in response to the buffer signal. The buffer signal generator is an inverse AND product that activates the buffer signal when both the input control signal and the buffer control signal are activated.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a circuit diagram illustrating an input buffer circuit including a DC voltage detection circuit according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 3 and the voltage level of the second node.

Referring to FIG. 3, an input buffer circuit 300 according to an embodiment of the present invention includes a DC voltage detection circuit 310, a buffer signal generator 320, and a buffer unit 330.

The DC voltage detection circuit 310 generates an input control signal INCTRL when the voltage level of the input signal DC_IN becomes greater than or equal to a predetermined voltage level. Hereinafter, the predetermined voltage level is expressed as the first voltage level as described above.

The buffer signal generator 320 generates a buffer signal BUFS in response to the input control signal INCTRL and the buffer control signal BUFCTRL. The buffer signal generator 320 may be an inverse AND function as shown in FIG. 3.

The buffer control signal BUFCTRL is a signal for controlling the operation of the buffer unit 330. If both the input control signal INCTRL and the buffer control signal BUFCTRL are at a high level, the buffer signal BUFS is generated at a low level. The buffer unit 330 is turned on when the buffer signal BUFS is at a low level.

When the buffer unit 330 is turned on, the buffer unit 330 receives the command CMD and outputs the output OUT_CMD. Since the operation of the buffer signal generator 320 and the buffer unit 330 is the same as the input buffer circuit 100 of FIG. 1, detailed description of the operation will be omitted.

The DC voltage detection circuit 310 includes a receiver 311, a first controller 313, a second node N2, and a second controller 315.

The receiver 311 receives the input signal DC_IN and controls the voltage level of the first node N1. The first controller 313 removes the DC current flowing through the receiver 311 when the voltage level of the input signal DC_IN becomes equal to or greater than the predetermined voltage level.

The second node N2 has a voltage level opposite to the voltage level of the first node N1.

The DC voltage detection circuit 310 includes a first control unit 313 and a second control unit 315 unlike the conventional DC voltage detection circuit 310. The first controller 313 removes the DC current flowing through the receiver 311. The second controller 315 controls the noise that affects the input signal DC_IN not to affect the voltage level of the second node N2.

The first controller 313 is a diode-type transistor DTR having a source connected to the power supply voltage VDD and a gate and a drain connected to each other.

 The receiver 311 includes a first transistor TR1 and a second transistor TR2. The first transistor TR1 has a first terminal connected to a drain of the diode transistor DTR, receives an input signal DC_IN through a gate, and a second terminal connected to the first node N1.

The second transistor TR2 has a first end connected to a first node N1, receives an input signal DC_IN through a gate, and a second end connected to a ground voltage VSS.

The source voltage of the first transistor TR1 is the value obtained by subtracting the threshold voltage Vt of the diode transistor DTR from the power supply voltage VDD by the diode transistor DTR of the first controller 313.

Assuming that the power supply voltage VDD is about 2.5V and the threshold voltage of the diode-type transistor DTR is about 0.7V, the source voltage of the first transistor TR1 is about 1.8V. If the threshold voltage of the first transistor TR1 is also about 0.7V, the voltage that should be applied to the gate of the first transistor TR1 to turn on the first transistor TR1 should be about 1.1V or less.

However, if the input signal DC_IN is a reference voltage signal, the reference voltage signal is generally 1/2 level of the voltage level of the power supply voltage, and thus the voltage level of the input signal DC_IN is about 1.25V.

The first transistor TR1 is turned off while the input signal DC_IN is applied at a voltage level of 1.25V. The second transistor TR2 is turned on to make the voltage level of the first node N1 low.

The inverter INV applies the input control signal INCTRL to the buffer signal generator 320 at a high level. Since the first transistor TR1 is turned off while the input signal DC_IN is applied at a voltage level of 1.25V and the buffer unit 330 is turned on and the command CMD is transmitted, no DC current is generated. .

If the voltage level of the power supply voltage VDD is increased, a plurality of diode transistors of the first controller 313 may be connected to adjust the source voltage level of the first transistor TR1.

The second controller 315 controls the voltage characteristic of the second node N2 to have hysteresis characteristics. The second controller 315 may be a PMOS transistor having a first terminal connected to the power supply voltage VDD, a gate connected to the second node N2, and a second terminal connected to the first node N1.

The second controller 315 allows the voltage characteristic of the second node N2 to have the characteristic shown in FIG. 4. The voltage characteristic shown in FIG. 4 is called hysteresis characteristic.

When the voltage level of the input signal DC_IN where the voltage level of the second node N2 changes to a high level as the voltage level of the input signal DC_IN is increased is VH, VH = VDD-2 * Vtp (Vtp Is the threshold voltage of the diode-type transistor DTR and the first transistor TR1.

In addition, when the voltage level of the input signal DC_IN where the voltage level of the second node N2 changes to a low level as the voltage level of the input signal DC_IN decreases, VL is the second transistor TR2. ) And the size ratio of the transistor PTR of the second control unit 315.

In the conventional DC voltage detection circuit 110 of FIG. 1, as shown in FIG. 2, the voltage level of the input signal DC_IN in which the voltage level of the second node N2 changes to a high level or changes to a low level is constant. .

Therefore, even if the voltage level of the input signal DC_IN which makes the voltage level of the second node N2 high is slightly lowered, there is a high possibility that the voltage level of the second node N2 is changed to a low level. That is, even if the voltage level of the input signal DC_IN is slightly changed by noise, the voltage level of the second node N2 is also changed.

However, the DC voltage detection circuit 310 of FIG. 3 has a voltage level VH and a second node N2 of the input signal DC_IN where the voltage level of the second node N2 changes to a high level as shown in FIG. 4. ) Is different from the voltage level VL of the input signal DC_IN in which the voltage level of the signal is changed to the low level.

Therefore, even if the voltage level VH of the input signal DC_IN which makes the voltage level of the second node N2 high is lowered to VL due to noise, the voltage level of the second node N2 remains high. do. That is, the DC voltage detection circuit 310 is less affected by noise by the transistor PTR of the second controller 315.

Unlike in FIG. 3, the second controller 315 has a first end connected to the ground voltage VSS, a gate connected to the second node N2, and a second end connected to the first node N1. It may be an NMOS transistor (not shown).

Even when the second control unit 315 is an NMOS transistor (not shown), the principle of controlling the voltage level of the second node N2 is the same as that of the case where the second control unit 315 is the PMOS transistor PTR. Omit.

FIG. 5A is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 3 and the voltage level of the first node.

FIG. 5B is a diagram illustrating the removal of the direct current according to the voltage level of the input signal.

Referring to FIG. 5A, when the voltage level of the input signal DC_IN decreases, the voltage until the moment when the voltage level of the first node CON_N1 of the conventional DC voltage detection circuit 110 changes to a high level. Margin is indicated by (A).

Since the voltage level of the first node N1 and the voltage level of the second node N2 are only opposite in phase, the relationship between the voltage level of the input signal DC_IN and the voltage level of the first node CON_N1 is determined by the input signal DC_IN. Is the same as the relationship between the voltage level of the circuit and the voltage level of the second node N2.

When the voltage level of the input signal DC_IN is lowered, the voltage margin until the moment when the voltage level of the first node PRO_N1 of the DC voltage detection circuit 310 changes to the high level is (B). Are indicated by).

Since the voltage margin B of the DC voltage detection circuit 310 according to the embodiment of the present invention is larger than the voltage margin A of the conventional DC voltage detection circuit 110, the DC voltage detection circuit according to the embodiment of the present invention. It can be seen that 310 is more resistant to noise.

Referring to FIG. 5B, it can be seen that the DC current is greatly reduced while the second transistor TR2 is turned on (C) because the voltage level of the input signal DC_IN is maintained above a certain voltage level.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the input buffer circuit including the DC voltage detection circuit and the DC voltage detection circuit according to the present invention reduces the unnecessary DC current and removes the influence of noise to some extent even if the voltage level of the input signal is changed by noise. There is an advantage to this.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a circuit diagram showing an input buffer circuit including a conventional DC voltage detection circuit.

FIG. 2 is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 1 and the second node voltage level.

3 is a circuit diagram illustrating an input buffer circuit including a DC voltage detection circuit according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 3 and the voltage level of the second node.

FIG. 5A is a diagram illustrating a relationship between the voltage level of the input signal of FIG. 3 and the voltage level of the first node.

FIG. 5B is a diagram illustrating the removal of the direct current according to the voltage level of the input signal.

Claims (18)

A receiver which receives an input signal and controls a voltage level of the first node; A first control unit which removes a DC current flowing through the receiving unit when the voltage level of the input signal is greater than or equal to a predetermined voltage level; A second node having a voltage level opposite to that of the first node; And And a second controller configured to control the voltage characteristic of the second node to have a hysteresis characteristic. The method of claim 1, wherein the first control unit, A DC voltage detection circuit comprising a diode-type transistor having a source connected to a power supply voltage and a gate and a drain connected to each other. The method of claim 2, wherein the receiving unit, A first transistor connected to a drain of the diode transistor, a first transistor connected to a gate thereof, and a second terminal connected to the first node; And And a second transistor connected to the first node, receiving the input signal through a gate, and a second transistor connected to a ground voltage. The method of claim 3, wherein the second control unit, And a PMOS transistor having a first end connected to a power supply voltage, a gate connected to the second node, and a second end connected to the first node. The method of claim 4, wherein And a voltage characteristic of the second node is controlled according to a ratio of the size of the PMOS transistor to the size of the second transistor.  The method of claim 3, wherein the second control unit, And an NMOS transistor, wherein a first end is connected to a ground voltage, a gate is connected to the second node, and a second end is connected to the first node. The method of claim 6, And a voltage characteristic of the second node is controlled according to a ratio of the size of the NMOS transistor to the size of the second transistor. The method of claim 1, wherein the first control unit, A DC voltage detection circuit, characterized in that a plurality of diode-type transistors having a gate and a drain connected to each other are connected in series with a power supply voltage. A DC voltage detection circuit for generating an input control signal when the voltage level of the input signal becomes equal to or higher than a predetermined voltage level; A buffer signal generator for generating a buffer signal in response to the input control signal and the buffer control signal; And And a buffer unit for receiving a command and outputting the command in response to the buffer signal. The method of claim 9, wherein the buffer signal generation unit, And an inverse AND function for activating the buffer signal when both the input control signal and the buffer control signal are activated. The method of claim 9, wherein the DC voltage detection circuit, A receiver which receives the input signal and controls a voltage level of a first node; A first control unit which removes a DC current flowing through the receiving unit when the voltage level of the input signal is greater than or equal to a predetermined voltage level; A second node for generating the input control signal having a voltage level opposite to that of the first node; And And a second controller for controlling the voltage characteristic of the second node to have a hysteresis characteristic. The method of claim 11, wherein the first control unit, An input buffer circuit, comprising: a diode-type transistor having a source connected to a power supply voltage and a gate and a drain connected to each other. The method of claim 12, wherein the receiving unit, A first transistor connected to a drain of the diode transistor, a first transistor connected to a gate thereof, and a second terminal connected to the first node; And And a second transistor connected to the first node, receiving the input signal through a gate, and a second transistor connected to a ground voltage. The method of claim 13, wherein the second control unit, And a PMOS transistor having a first end connected to a power supply voltage, a gate connected to the second node, and a second end connected to the first node. The method of claim 14, And the voltage characteristic of the second node is controlled according to a ratio of the size of the PMOS transistor to the size of the second transistor. The method of claim 13, wherein the second control unit, And an NMOS transistor having a first end connected to a ground voltage, a gate connected to the second node, and a second end connected to the first node. The method of claim 16, And the voltage characteristic of the second node is controlled according to a ratio of the size of the NMOS transistor to the size of the second transistor. The method of claim 11, wherein the first control unit, An input buffer circuit, characterized in that a plurality of diode-type transistors having a gate and a drain connected to each other are connected in series with a power supply voltage.