KR20050043299A - Apparatus and method for handling interrupt using dynamic allocation memory in embedded system - Google Patents

Abstract

The present invention provides a method for processing an interrupt in an embedded system, the method comprising: selecting a part or all of interrupt signals required among all possible interrupt signals, dynamically allocating a memory, and dynamically selecting the selected signals. And a step of one-to-one mapping of each interrupt signal recorded in the memory and the corresponding interrupt service routine (ISR) function.

Description

Apparatus and method for handling interrupts using dynamic allocation memory in embedded systems {APPARATUS AND METHOD FOR HANDLING INTERRUPT USING DYNAMIC ALLOCATION MEMORY IN EMBEDDED SYSTEM}

The present invention relates to an apparatus and method for handling interrupts in an embedded system, and more particularly, to an apparatus and method for handling interrupts by allocating memory.

An embedded system can be defined as a system embedded in any device for processing a specific purpose task with limited resources. For example, in the mobile phone, the limited resources include size and battery. In addition, the task having a specific purpose may be a call processing that is responsible for the transmission and reception of the telephone. As such, the embedded system is a system that can be easily found around us. In fact, annually embedded systems are much larger than desktop PCs and are used in various fields. Looking at the field and the typical applications that the embedded system is utilized as follows.

1. Information Appliances-Fields that link home appliances such as TVs, refrigerators and washing machines to the Internet

2. Information terminal-field of mobile communication terminal such as personal digital assistant (PDA), video telephone, etc.

3. Communication equipment-Field of communication equipment such as digital exchange, private automatic telephone exchange, router, switch, etc.

4. Logistics / Finance-Logistics / Finance sector such as ATM, barcode related devices

5. Vehicles / Transportation-Vehicles / Transportation Fields such as Engines, Control Systems, Intelligent Transport Systems (ITS), etc.

In addition to the applications and applications, the embedded system may be applied to all systems closely related to life such as medical, gaming, aviation / military.

Recently, the embedded system has been in the spotlight for two reasons.

First, the saturation of personal computers and the demand for information appliances. As various information appliances such as PDAs, mobile phones, and high-definition TVs have emerged, they are replacing personal computers. In other words, the reason why the embedded system is in the spotlight is that a personal computer includes one microprocessor, but one home appliance can have dozens of embedded systems depending on the purpose, and thus the marketability is infinite.

Second is the aging system due to the development of new technologies. Any existing system is unable to provide a timely control program in line with the rapid technological development. Therefore, it is inevitable to develop a lightweight, integrated low power embedded system.

On the other hand, the embedded system may be composed of a variety of hardware, which is called an interrupt (interrupt) to request that the hardware to perform a task. The cause of the interruption is that the embedded system includes a limited number of Central Processing Units (hereinafter referred to as CPUs), and usually one CPU is included in one system. In other words, when a CPU performing a task of any hardware device A receives a task request from another hardware device B of higher priority by interrupt priority, the task of the hardware device A which was being performed is paused first, Process the job of B that made the request. The CPU, which has completed the processing of B, loads the job information of A stored in the memory and resumes the work of A continuously from the time when it is suspended. As such, the CPU performs only one task for one hardware device, but the processing time is so short that the user feels that the hardware devices A and B are processed simultaneously.

The CPU for handling the interrupt maps an interrupt service routine (hereinafter, referred to as an 'ISR') that is implemented programmatically to main memory and an interrupt signal generated from each hardware device. mapping) to process. For example, the CPU, which receives an input signal from any key of the keyboard, calls the corresponding ISR stored in the main memory to handle the interrupt for the keyboard input. Hereinafter, a relationship between a CPU receiving the interrupt request signal and an ISR of the main memory will be described with reference to FIG. 1.

1 is a diagram schematically illustrating a flow of execution between a CPU and a main memory for processing a general interrupt.

Referring to FIG. 1, the CPU 100 first receiving an interrupt request 102 signal from an arbitrary hardware device stores information about a task that has been previously performed in a temporary memory (not shown) in the CPU. The received interrupt request signal is read. For example, it is assumed that the interrupt request signal 102 is generated by a key input of a keyboard, and the temporary memory may be a cache memory and a register. The cache memory serves to improve the processing speed of the CPU in the storage hierarchy. The cache also works by leaving the copy in cache memory in anticipation that data in the main memory will be used once by the CPU and then used again. The CPU 100, which senses the interrupt request signal of the keyboard, implements the ISR0 106 implemented in the main memory 150 through a path between the CPU 100 and the main memory 150 called a memory bus 104. Call The ISR0 106 is a function that programmatically implements a series of processing for the keyboard interrupt signal. The ISR0 106 to ISRn 112 are referred to as an interrupt vector table implemented in an array structure and implement processing for each interrupt request signal as a programming function. With reference to the ISR0, the CPU performs a series of tasks on the interrupt request signal, and when the processing is completed, loads a previous task previously stored in the temporary memory and resumes the task continuously from the time when it is suspended.

Then, the difference between the hardware devices of the embedded system and the hardware devices of a general personal computer (PC) will be described with reference to Table 1 below.

As above, embedded systems also vary in the complexity of the functionality and the size of the system. Examples include refrigerators and PDAs with embedded systems. The PDA has to use a minimum hardware device with the highest performance in order to implement a portable system. That is, referring to Table 1, the embedded system rarely uses various hardware devices and requires a minimum amount of memory.

Embedded systems using this limited memory capacity store an ISR to perform a series of processing in the memory to handle the interrupt when the interrupt occurs. If the embedded system is configured with a hardware device that generates a plurality of interrupts, a certain area of the memory for processing the interrupts must also be increased. However, the memory should not only handle interrupts but also drive applications and store various data. In other words, the embedded system needs to effectively use limited memory resources.

A memory storing a conventional interrupt process allocates a predetermined area in an array structure. The array structure is a data language that can store elements having the same data type in a contiguous storage space under a single name from an arbitrary starting point to an ending point of a memory physical address in a programming language, for example, C language. Initialize all for processing. In such a case, assuming that a hardware device generates only two interrupt signals, the memory area for other interrupt signals that are not generated is also initialized. This causes a waste of memory since the memory must be allocated for the non-occurring interrupt signal processing even in an area that is not required to be used. In addition, when a new hardware device is added to the embedded system, there is an inefficient aspect of redefining the number of ISRs of the interrupt vector table.

Accordingly, an object of the present invention is to provide an apparatus and method for dynamically implementing a memory to effectively use limited memory resources in an embedded system.

It is another object of the present invention to provide an apparatus and method for handling interrupts more efficiently using dynamically allocated memory.

The method of the present invention for achieving the above object; CLAIMS What is claimed is: 1. A method for handling interrupts in an embedded system, the method comprising: selecting some or all of the required interrupt signals among all possible interrupt signals, dynamically allocating memory, and dynamically assigning the selected signals to the dynamically allocated memory. And a one-to-one mapping of each interrupt signal recorded in the memory and a corresponding interrupt service routine (ISR) function.

The apparatus of the present invention for achieving the above object; An apparatus for processing an interrupt in an embedded system, the apparatus comprising a memory for storing an interrupt signal in a dynamically allocated address area and a CPU for processing an interrupt dynamically allocated to the memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

Prior to the description, the present invention proposes an apparatus and method for more efficiently utilizing limited memory resources by dynamically initializing a memory structure in order to process only an interrupt signal required by an embedded system. In addition, when the memory is dynamically implemented as described above, an apparatus and method for more effectively performing an interrupt service routine (hereinafter, referred to as an 'ISR') when adding new hardware are proposed.

On the other hand, the linked list, which will be described later, allocates memory whenever necessary and adds data, so that the memory can be managed more efficiently than the array, and the data can be stored indefinitely unless the memory is full. have.

2 is a block diagram showing an apparatus configuration for processing an interrupt according to an embodiment of the present invention.

First, the interrupt signal defining unit 202 detects all interrupt signals generated by any hardware device of the embedded system and extracts and selects only the interrupt signal required by the embedded system. Herein, the select factor indicated by the interrupt signal defining unit 202 means extracting the required interrupt signal. For example, assume that any hardware device A all generates seven interrupt signals. When the hardware device A is used in Russia, assuming that only the first and second interrupt signals of the seven interrupt signals are needed, and only the third and fourth interrupt signals are required in China, only the first and second interrupt signals are used in Russia. In this case, the third and fourth interrupt signals are extracted and selected in China. That is, the type and number of interrupts generated may vary depending on where and how the same hardware device A is used. In this case, the system only needs to input the required interrupt signal and store only the ISR for processing the interrupt.

Next, the interrupt number scan unit 204 detects some or all interrupt signals selected by the interrupt signal definition unit 202. The interrupt number scanning unit 204 is included in a central processing unit (hereinafter referred to as a CPU). Therefore, when the hardware device in which the interrupt signal is defined is mounted in the embedded system, the CPU controls the memory initialization unit 208 to be referred to as a 'head' in a predetermined area of the memory. ) And the interrupt vector table is initialized with a linked list structure having only a tail and a tail (hereinafter, referred to as a 'tail'). The interrupt vector table may be referred to as a structure in which an ISR number for performing a corresponding interrupt is stored when an interrupt occurs.

The interrupt number input unit 206 inputs the necessary interrupt number in the initialized interrupt vector table, that is, the dynamic memory space of the head and tail. That is, in the case of the input, the interrupt number is input by allocating a memory area to the head and the tail. Thereafter, the function initialization unit 210 performs function initialization only for the input number in the dynamic memory and does not initialize the function corresponding to the interrupt number. Next, the ISR allocator 212 maps the corresponding ISR to each input number for the interrupt number input in the dynamic memory. For example, when the interrupt number input unit 206 inputs the keyboard interrupt occurrence as interrupt number 1, the interrupt number input unit 206 may map to ISR0 for the interrupt processing.

Next, if an interrupt signal is generated from any hardware device, the ISR execution unit 214 checks whether there is a number detected by the interrupt number scan unit 204, and if the corresponding interrupt signal is stored in the dynamic memory, the ISR is performed. Branches to perform ISR. In FIG. 2, the AND operator 216 processes the interrupt signal allowed to the system by ANDing the input interrupt number and the ISR to be performed by the CPU. For example, the ISR execution unit 214 inputs a situation in which one of the interrupt signals 1, 3, and 6 may occur to the PEND node of the AND operator 216, and interrupt signals 1 and 6 configured to be processed by the system. When input to the MASK node, the system performs interrupt processing only when the interrupt signals 1 and 6 occur, and performs error processing when the interrupt signal 3 occurs.

Hereinafter, each block configuration of FIG. 2 will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating selecting an interrupt signal from an interrupt signal defining unit 202 or 304 according to an embodiment of the present invention.

First, there are a total of seven interrupt signals generated by any hardware 302. Assuming that only interrupts 1, 2, 5, and 7 of the 7 signals are used, the interrupt signal defining unit 304 extracts and selects only the interrupt signals of 1, 2, 5, and 7 from the hardware from the total 7 interrupt signals. do. Thereafter, the selected interrupt signals are detected by the interrupt number scan unit 204 of the CPU 306 and transmitted to the interrupt number input unit 206. Thereafter, when the selected interrupt signal is generated, it branches to the corresponding ISR of the interrupt vector table of the dynamic memory to process the interrupt.

Next, FIG. 4 is a diagram illustrating a form in which the memory initialization unit 208 initializes the memory in a linked list structure.

4 is a diagram illustrating a dynamic memory structure initialized only with a head and tail structure according to an embodiment of the present invention.

Referring to FIG. 4, the dynamic memory structure is programmatically initialized with only the head 402 and tail 404 using self-referencing structures and linked list structures in, for example, C or C ++ languages. Hereinafter, the dynamic memory structure is an example case where the C language is defined.

typedef struct_table {

       unsigned int vector_number;

       struct_table * next;

} table;

table * head_table, * tail_table;

Referring to the programming example using the self-reference structure and linked list, * head_table indicates the start of dynamic memory and * tail_table indicates the end of dynamic memory.

Next, referring to FIG. 5, after the dynamic memory is initialized to the head and the tail, nodes, which are regions for storing data between the head and the tail by inputting an interrupt signal number, will be described.

5 is a diagram illustrating a dynamic memory structure in which an interrupt number is input according to an embodiment of the present invention.

Referring to FIG. 5, the dynamic memory includes an address region of the selected interrupt signals 1 504, 2 506, 5 508, and 7 510 between the head 502 and the tail 512. The structure is inserted by the interrupt number input unit 206. The node means a space in which data is stored, and 504, 506, 508, and 510 of FIG. 5 are called nodes. Hereinafter, an example of a function used when the dynamic memory structure in which the interrupt number is input is defined in the C language.

insert_table (unsigned int vector_number);

The program syntax takes an integer vector_number argument and stores it in the vector number of the self-reference structure and becomes a list of interrupt vector tables. Therefore, a program implementation that uses the insert_table function to occupy the address region between the head 502 and the tail 512 by using the interrupt signals 1, 2, 5, and 7 may include the following syntax. The function to be defined can be freely defined by the program writer.

insert_table (1);

insert_table (2);

insert_table (5);

insert_table (7);

Next, a diagram in which a dynamic memory including the head, the interrupt number node, and the tail is mapped to an initialization function will be described with reference to FIG. 6.

6 is a diagram illustrating a dynamic memory structure in which each node is mapped to an initialization function according to an embodiment of the present invention.

Referring to FIG. 6, the function initialization unit 210 of the dynamic memory that terminates the interrupt signal input maps to an initialization function for each node. The initialization function is a function defined freely by a programmer and a function defined as a default when designing a system. For example, when the CPU detects an interrupt signal requesting image loading, the CPU loads an initialization function that is predefined in system design. For example, each of the nodes may be initialized to a null value. Each of these nodes is mapped to the same initialization function.

FIG. 7 illustrates a dynamic memory structure in which nodes are mapped to corresponding ISRs according to an embodiment of the present invention.

Referring to FIG. 7, when the mapping to the initialization function is completed, the ISR allocator 212 maps each node by the corresponding ISR. That is, the ISR allocator 212 assigns the interrupt signal 1 704 to ISR0 mapped to the corresponding interrupt vector table, the interrupt signal 2 706 to ISR1 mapped to the corresponding interrupt vector table, and the interrupt signal 5 708. Is ISR2 mapped with the corresponding interrupt vector table, and interrupt signal 7 710 maps to ISR3 mapped with the corresponding interrupt vector table, respectively. Each of the mapped interrupt signals is determined by the ISR performing unit 214 when the random interrupt signal is mapped with the signals detected by the interrupt number scanning unit 204 when it is generated. The ISR is performed by branching to a vector table.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention has an advantage in that a limited memory can be used more efficiently by allocating memory only for an interrupt signal defined by implementing a dynamic allocation memory using a connection list in an embedded system.

1 is a diagram schematically illustrating a flow of execution between a CPU and a main memory for processing a general interrupt;

2 is a block diagram showing an apparatus configuration for processing an interrupt according to an embodiment of the present invention.

3 is a diagram illustrating selecting an interrupt signal from an interrupt signal defining unit 202 or 304 according to an embodiment of the present invention.

4 illustrates a dynamic memory structure initialized only with a head and tail structure according to an embodiment of the present invention.

5 is a diagram illustrating a dynamic memory structure in which an interrupt number is input according to an embodiment of the present invention.

6 illustrates a dynamic memory structure in which each node is mapped to an initialization function according to an embodiment of the present invention.

FIG. 7 illustrates a dynamic memory structure in which nodes are mapped to corresponding ISRs according to an embodiment of the present invention. FIG.

Claims (9)

In a method for handling interrupts in an embedded system, Selecting some or all of the required interrupt signals among all possible interrupt signals; The process of dynamically allocating memory, Writing the selected signal to the dynamically allocated memory; And one-to-one mapping of each interrupt signal written to the memory and a corresponding interrupt service routine (ISR) function. The method of claim 1, wherein dynamically allocating the memory comprises: Initializing the memory with the head and tail address areas, Allocating a new data storage address area to an address area between the head and tail corresponding to the selected interrupt signal. The method of claim 2, Wherein each data storage address area refers to a next data address area. The method of claim 1, And determining whether the generated interrupt signal is the selected interrupt signal when a predetermined interrupt signal is generated. An apparatus for handling interrupts in an embedded system, Memory in which interrupt signals are stored in dynamically allocated address areas; And a CPU for handling an interrupt dynamically allocated to the memory. The method of claim 5, And the memory initializes the head and tail address areas and allocates a data storage address area corresponding to one or more selected interrupt signals among all possible interrupt signals to an address area between the head and tail. The method of claim 6, Wherein each data storage address area refers to a next data address area. The method of claim 5, The CPU controls one-to-one mapping between each interrupt signal stored in the memory and an interrupt service routine (ISR) corresponding thereto to perform the one-to-one mapped corresponding interrupt service routine (ISR) when the interrupt signal is generated. Device. The method of claim 5, And the CPU determines whether the generated interrupt signal is an interrupt signal allowed by the system when any interrupt signal is generated.