KR20050043269A - High-speed multi-bank semiconductor memory apparatus operating interleaved stack bank arrays and method thereof - Google Patents

Abstract

A high speed multi-bank semiconductor memory device having a stack bank array operating interleaved and a method thereof are disclosed. The high-speed multi-bank semiconductor memory device may improve the overall operation speed by operating the plurality of stack bank arrays interleaved, that is, one by one in succession.

Description

High-speed multi-bank semiconductor memory apparatus operating interleaved stack bank arrays and method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a multi-bank semiconductor memory device having a stack type and a method of speeding up its operation.

In semiconductor memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), flash random access memory (FRAM), and the like, there is an increasing number of semiconductor memory device products having a multi-bank structure in which bank structures are stacked. In semiconductor memory devices having such a structure, a demand for speeding up has become a big issue.

A multi-bank semiconductor memory device having a stacked bank array includes a bank array having a plurality of banks. Here, each of the banks has a plurality of cell arrays composed of memory cells. The cell arrays provided in the bank have the same structure. The operation of reading or writing the cell data stored in the memory cells of the cell array is performed by a predetermined decoder provided in a peripheral circuit, that is, a peri block. That is, by selecting each of the cells in the ferry block, data stored in the cell is read or necessary data is written to the cell. However, in the conventional multi-bank semiconductor memory device, there is a need for a countermeasure for faster operation.

Accordingly, an aspect of the present invention is to provide a high-speed multi-bank semiconductor memory device and a method for interleaving a plurality of stack bank arrays, that is, operating one by one in succession to improve the overall operation speed. There is.

According to another aspect of the present invention, there is provided a multi-bank semiconductor memory device including a plurality of stack bank arrays, a plurality of ferry blocks, and an active selection control circuit. The plurality of stack bank arrays consist of stacked banks, each of which is accessed in response to a bank operation signal. Each of the plurality of ferry blocks corresponds to each of the stack bank arrays, and generates and outputs the bank operation signal in response to a ferry active signal. The active selection control circuit generates and outputs the ferry active signal corresponding to each of the stack bank arrays. The ferry active signal is a signal obtained by dividing a frequency of a system clock signal by the number of stack bank arrays. The number of the ferry active signals as many as the stack bank array is a pulse which is activated one by one in a predetermined order every time the system clock signal is activated in synchronization with the system clock signal.

According to another aspect of the present invention, there is provided a method of driving a multi-bank semiconductor memory device, including: generating and outputting a ferry active signal corresponding to each of the stack bank arrays; Generating and outputting a bank operation signal in response to the ferry active signal; And accessing banks constituting each of the stack bank arrays in response to the bank operation signal. The ferry active signal is a signal obtained by dividing a frequency of a system clock signal by the number of stack bank arrays. The number of the ferry active signals as many as the stack bank array is a pulse which is activated one by one in a predetermined order every time the system clock signal is activated in synchronization with the system clock signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a multi-bank semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, a multi-bank semiconductor memory device according to an embodiment of the present invention may include a plurality of stack bank arrays 110 and 120 and a plurality of periblocks 130 and 140. And an active selection control circuit 150.

The plurality of stack bank arrays 110 and 120 each consist of stacked banks that are accessed in response to a bank operation signal. Each of the stacked banks has a plurality of cell arrays composed of memory cells, as shown in FIG. The cell arrays provided in the bank have the same structure. When the stacked banks are accessed by the bank operation signal, cell data stored in memory cells of a cell array is read or written to cells using a sense amplifier SA. The operation is made.

Each of the plurality of ferry blocks 130 and 140 corresponds to each of the stack bank arrays 110 and 120, and generates and outputs the bank operation signal in response to the ferry active signals PERI1AS and PERI2AS. . Each of the plurality of ferry blocks 130 and 140 selects the stacked banks by a predetermined decoder and generates the bank operation signal to access each of the selected stacked banks, thereby receiving data stored in a memory cell. Read or write the necessary data into the cell.

The active selection control circuit 150 generates and outputs the ferry active signals PERI1AS and PERI2AS corresponding to each of the stack bank arrays 110 and 120.

3 is a timing diagram illustrating an operation of a multi-bank semiconductor memory device of FIG. 1. Referring to FIG. 3, the ferry active signals PERI1AS and PERI2AS are signals obtained by dividing a frequency of a system clock signal SCLK by the number of stack bank arrays. That is, in FIG. 2, since the number of the stack bank arrays is 2, when the frequency of the system clock signal SCLK is f _SCLK , the frequencies of the ferry active signals PERI1AS and PERI2AS are f _SCLK / 2. The number of the ferry active signals PERI1AS and PERI2AS corresponding to the number of the stack bank arrays are pulses that are activated one by one in a predetermined order whenever the system clock signal SCLK is activated in synchronization with the system clock signal SCLK. . That is, when the system clock signal SCLK is activated from a first logic state (eg, a logic low state) to a second logic state (eg, a logic high state), the ferry active signals PERI1AS, PERI2AS) is activated from the first logic state to the second logic state one by one in a predetermined order.

4 is a block diagram of a multi-bank semiconductor memory device according to another embodiment of the present invention. The present invention is not limited to two stack bank arrays as shown in FIG. 1, but may be extended to four stack bank arrays as shown in FIG. 4. The larger the number of stack bank arrays, the faster the overall operation speed. As shown in FIG. 1, when the number of stack bank arrays is 2, since the stack bank arrays 110 and 120 are interleaved one by one by two ferry active signals PERI1AS and PERI2AS, the overall system operation speed is increased. Double the operating speed of each of the stack bank arrays. As shown in FIG. 4, when the number of stack bank arrays is 4, the active selection control circuit 490 generates and outputs four ferry active signals PERI1AS to PERI4AS corresponding to each of the stack bank arrays 410 to 440. As shown in FIG. 5, the stack bank arrays 410 to 440 interleave once in a predetermined order according to a bank operation signal output from each of the active ferry blocks 450 to 480. The overall system operating speed is four times the operating speed of each stack bank array.

As described above, when the multi-bank semiconductor memory device generates and outputs the ferry active signals PERI1AS and PERI2AS from the active selection control circuit 150, the stack bank arrays 110,. 120. A plurality of ferry blocks 130 and 140 corresponding to each generate and output a bank operation signal in response to the ferry active signals PERI1AS and PERI2AS. Accordingly, the stacked banks of the stacked bank arrays 110 and 120 that are accessed thereby read / write the memory cell data in response to the bank operation signal.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the multi-bank semiconductor memory device according to the present invention may improve the overall operation speed by interleaving a plurality of stack bank arrays, that is, operating one by one in succession.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a multi-bank semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a view illustrating the inside of a bank of FIG. 1.

3 is a timing diagram illustrating an operation of a multi-bank semiconductor memory device of FIG. 1.

4 is a block diagram of a multi-bank semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a timing diagram for describing an operation of the multi-bank semiconductor memory device of FIG. 4.

Claims (6)

A plurality of stack bank arrays each of stacked banks accessed in response to a bank operation signal; A plurality of ferry blocks each corresponding to each of the stack bank arrays and generating and outputting the bank operation signal in response to a ferry active signal; And And an active select control circuit configured to generate and output the ferry active signal corresponding to each of the stack bank arrays. The method of claim 1, wherein the ferry active signal, And a frequency of a system clock signal divided by the number of stack bank arrays. The method of claim 2, wherein the number of the ferry active signals is equal to the number of the stack bank arrays. And a pulse which is activated one by one in a predetermined order every time the system clock signal is activated in synchronization with the system clock signal. Generating and outputting a ferry active signal corresponding to each of the stack bank arrays; Generating and outputting a bank operation signal in response to the ferry active signal; And And accessing banks constituting each of the stack bank arrays in response to the bank operation signal. The method of claim 4, wherein the ferry active signal, A method of driving a multi-bank semiconductor memory device, characterized in that the frequency of a system clock signal is divided by the number of stack bank arrays. The method of claim 5, wherein the number of the ferry active signals is equal to the number of the stack bank arrays. And a pulse which is activated one by one in a predetermined order every time the system clock signal is activated in synchronization with the system clock signal.