KR20050029593A - Method and apparatus for plasma display panel - Google Patents

Abstract

A method and an apparatus for driving a plasma display panel are provided to improve image quality by preventing discharge error or mis-discharge. A plasma display panel comprises driving electrodes of a first, second and third electrodes and a partition wall to partition a discharge space of a cell. The method drives the plasma display panel by dividing the cell into a reset period to initialize the cell, and an address period to select the cell, and sustain period to sustain the discharge of the cell. According to the method, the scattering of wall charge distribution on the partition wall is suppressed by supplying a number of sub pulses(stp) to the first electrode during the sustain period. And a sustain pulse(sus1-sus6) is supplied to the second electrode after the sub pulse is generated, and the sustain pulse is supplied to the third electrode after the sub pulse is generated.

Description

Method and apparatus for driving plasma display panel {METHOD AND APPARATUS FOR PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel capable of improving image quality by preventing mis-discharge and miss discharge.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs"), and electroluminescence (Electro). -Luminescence (EL) display.

PDP is a display device using a gas discharge has the advantage that it is easy to manufacture a large panel. The PDP is mainly composed of a three-electrode AC surface discharge type PDP as shown in FIG. 1.

Referring to FIG. 1, a discharge cell of a PDP includes an address electrode 12X formed on a lower substrate 18, a pair of sustain electrodes formed on the upper substrate 10, that is, a scan electrode 12Y and a sustain electrode ( 12Z).

The lower dielectric layer 22 is formed on the lower substrate 18 on which the address electrode 12X is formed to cover the address electrode 12X, and the partition wall 24 is formed thereon. Phosphor 20 is formed on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 is generally formed in a stripe pattern as shown in FIG. 2 or in a closed pattern in order to increase luminous efficiency as shown in FIG. The partition wall 24 physically divides the discharge space so that ultraviolet rays and visible rays generated at the time of discharge are not leaked to the adjacent discharge cells. The phosphor 20 is excited and shifted by ultraviolet rays generated during gas discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Each of the sustain electrode pairs 12Y and 12Z formed on the upper substrate 10 includes a transparent electrode 12a and a bus electrode 12b and intersects with the address electrode 12X.

An upper dielectric layer 14 is formed on the upper substrate 10 where the sustain electrode pairs 12Y and 12Z are formed to cover the sustain electrode pairs 12Y and 12Z, and a protective film 16 is formed thereon. The upper dielectric layer 14 accumulates wall charges generated during discharge. The protective film 16 is usually made of magnesium oxide (MgO), and prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases the emission efficiency of secondary electrons.

The discharge cell of this structure is selected by the counter discharge between the address electrode 12X and the scan / hold electrode 12Y and then sustains the discharge by the surface discharge between the sustain electrode pairs 12Y and 12Z. In such a discharge cell, the fluorescent substance 20 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted to the outside of the cell. Here, gradation is realized by adjusting the sustain period during which the discharge is maintained or the number of discharges within the period.

Recently, in the PDP, Japanese Patent Laid-Open No. 2001-135238 or the like has tended to increase the concentration of Xe in discharge gas by more than 8% of Ne to increase luminous efficiency. When comparing the strengths and disadvantages known to date when increasing the concentration of Xe is shown in Table 1 below.

Advantages of increasing Xe concentration Disadvantages of Increasing Xe Concentration Brightness increase Increased discharge voltage & increased discharge delay Increase efficiency Temperature rise of panel Color temperature increase Afterimage occurrence, etc.

As can be seen from Table 1, the increase of Xe concentration has excellent advantages, but many disadvantages are also exposed. For example, the increase in the discharge delay makes it difficult to implement high-speed driving, which is an obstacle in increasing the resolution, brightness, and display quality of the PDP.

In addition, if the distribution of the wall charges accumulated on the partition wall 24 is shaken, the discharge delay is increased and false discharge or miss discharge is caused. In other words, the wall charges accumulated in the partition wall 24 is because the partition wall 24 generally includes a material having a high dielectric constant such as Pb, Zr, TiO _3, and the amount thereof is not small, as described above when the distribution is shaken. It has been experimentally found to cause false discharge or miss discharge. This will be described in detail with reference to FIGS. 4 to 7.

Assuming that the wall charge distribution as shown in FIG. 4A can be normally discharged without mis-discharge or miss discharge, a scan pulse scp as shown in FIG. 4B is applied to the scan electrode 12Y, and the data pulse is applied to the address electrode ( 12X), the address discharge occurs after the ideal discharge delay time [Delta] t elapses after the scan pulse scp is generated. Under these ideal conditions, as the distribution of the wall charge 41 of the upper plate and the subordinate charge 42 of the lower plate is shaken as shown in FIG. 5A and FIG. 5B, the discharge delay time increases to Δdt1 as shown in FIG. 6. However, when the distribution of the wall charges 43 accumulated on the partition wall 24 as shown in FIG. 7A is shaken, the discharge time is further increased to Δdt2 as shown in FIG. 7B so that no discharge occurs in severe cases or discharge occurs in unwanted cells. do.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP that can improve image quality by preventing mis-discharge or miss discharge.

In order to achieve the above object, the driving method of the PDP according to an embodiment of the present invention comprises the steps of supplying a plurality of auxiliary pulses to the first electrode during the sustain period to suppress the shaking of the wall charge distribution on the partition wall; Supplying a sustain pulse to a second electrode after the auxiliary pulse is generated and supplying the sustain pulse to a third electrode after the auxiliary pulse is generated.

The driving method includes supplying an initialization waveform to the second electrode during the reset period; And supplying scan pulses to the second electrode and supplying data pulses to the first electrode during the address period.

The auxiliary pulse is set to the voltage of the data pulse.

The driving apparatus of the PDP according to the embodiment of the present invention includes a wall charge distribution stabilization driver for supplying a plurality of auxiliary pulses to the first electrode during the sustain period to suppress shaking of the wall charge distribution on the partition wall; And a sustain driver for supplying a sustain pulse to the second electrode after the auxiliary pulse is generated and for supplying the sustain pulse to the third electrode after the auxiliary pulse is generated.

The drive device further includes an oxide film formed on the partition wall.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 12.

Referring to FIG. 8, the PDP according to the embodiment of the present invention is driven by being divided into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

The rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y at the beginning of the reset period. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. The rising ramp waveform Ramp-up causes a write discharge with weak discharge between the scan electrode Y and the address electrode X and between the scan electrode Y and the sustain electrode Z in the cells of the full screen. The write discharge causes positive wall charges to be accumulated on the address electrode X and the sustain electrode Z, and negative wall charges to be accumulated on the scan electrode Y.

After this rising ramp waveform (Ramp-up) is supplied, it starts to fall from the approximately sustain voltage (Vs) lower than the peak voltage of the rising ramp waveform (Ramp-up) to a negative scan bias voltage (-Vy). This lowering ramp waveform Ramp-dn is simultaneously supplied to the scan electrodes Y. At the same time, the bias voltage Vz-bias of the sustain voltage Vs is supplied to the sustain electrode Z, and 0 [V] is supplied to the address electrode X. When the falling ramp waveform Ramp-dn is supplied in this manner, erase discharge occurs with a weak discharge between the scan electrode Y and the sustain electrode Z and between the scan electrode Y and the address electrode Z. The erase discharge erases excessive wall charges unnecessary for the address discharge among the wall charges generated in the setup period SU. Looking at the wall charge change in the setup period SU and the setdown period SD, there is almost no wall charge change on the address electrode X, and the negative wall charge of the scan electrode Y decreases. On the other hand, the wall charge of the sustain electrode Z was positive in the set-up period SU, but the negative wall charge accumulated on itself as much as the decrease in the negative wall charge of the scan electrode Y was set-up period. At (SD), its polarity is reversed to negative polarity.

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, auxiliary pulses for stabilizing the partition wall charge immediately before the sustain pulse sus alternately supplied to the scan electrodes Y and the sustain electrodes Z and every sustain pulse sus6 to sus6 are supplied. The pulse stp is supplied to the address electrodes X. The auxiliary pulse stp increases the voltage of the address electrode X to a positive voltage to induce negative wall charges accumulated on the partition wall 24 toward the discharge space or the address electrode X to sustain pulses sus1 to sus6. The wall charge distribution on the partition 24 is made constant before () is supplied. The voltage of the auxiliary pulse stp is set to approximately the data voltage Vd and its pulse width is set to approximately the data pulse or less. After the wall charge distribution of the partition wall 24 is stabilized, and the sustain pulses sus 1 to sus 6 are alternately applied to the scan electrodes Y and the sustain electrodes Z, the cells selected by the address discharge have a wall voltage in the cell. As the sustain pulse sus is added, a sustain discharge, that is, a display discharge, is generated between the scan electrode Y and the sustain electrode Z at each sustain pulse su.

After the sustain discharge is completed, an erase ramp waveform (not shown) is supplied to the scan electrode Y and / or the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

Meanwhile, as can be seen from FIG. 9, during the sustain period, the voltage on the address electrode X maintained the base voltage GND or 0 V, and no signal was applied to stabilize the wall charge distribution of the partition wall 24. .

10 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 10, a driving apparatus of a PDP according to an embodiment of the present invention may include a data driver 102 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 103 for driving, a sustain driver 104 for driving the sustain electrodes Z serving as a common electrode, a timing controller 101 for controlling each of the drivers 102, 103, and 104, A driving voltage generator 105 is provided for supplying driving voltages necessary for each of the driving units 102, 103, 104.

The data driver 102 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 102 samples and latches data in response to the timing control signal Cx from the timing controller 101, and then supplies the data to the address electrodes X1 to Xm. In addition, the data driver 102 supplies the auxiliary pulses stp of the data voltage Vd to the address electrodes X1 to Xm just before each sustain pulse sus is supplied during the sustain period.

The scan driver 103 supplies the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-dn to the scan electrodes Y1 to Ym under the control of the timing controller 101 during the reset period, and scans during the address period. The pulses scp are supplied sequentially. The scan driver 103 supplies the sustain pulses sus1, sus3, and sus5 to the scan electrodes Y1 to Ym during the sustain period under the control of the timing controller 101.

The sustain driver 104 supplies the DC bias voltage Vz-bias during the address period under the control of the timing controller 101, and then alternately operates the scan driver 103 during the sustain period to sustain the pulses sus2, sus4, and sus6. Will be supplied.

The timing controller 101 receives a vertical / horizontal synchronization signal and a clock signal, generates timing control signals Cx, Cy, and Cz necessary for each driver, and outputs the timing control signals Cx, Cy, and Cz to the corresponding driver 102. , Respectively, to control the driving units 102, 103, 104. The data control signal Cx includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal Cy includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 103. The sustain control signal Cz includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the sustain driver 104.

The driving voltage generation unit 105 includes a negative scan bias voltage (-Vy) and a direct current bias voltage (Vy-bias, Vz-bias) that are set to the setup voltage Vsetup of the rising ramp waveforms Ruy and Ruz, the scan voltage. ), Sustain voltage (Vs), data voltage (Vd), and the like. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

On the other hand, the applicant of the present application through the patent application No. 2003-48732 (July 16, 2003) structure for forming a low dielectric constant layer, such as silicon oxide or magnesium oxide on the partition wall 24 to stabilize the wall charge distribution on the partition wall And a method of manufacturing the same.

FIG. 11 illustrates an experimental result when a three-electrode surface discharge PDP in which silicon oxide is formed on a partition wall using driving signals as shown in FIG. 8. In this experiment, the sustain pulses (sus1 to sus6) were alternately supplied to the scan electrode and the sustain electrode at a frequency of 167 kHz and 24 pulses, and the voltage of the stabilization pulse (stp) was set to 80V. According to the results of the experiment, the shaking of the wall charge in the driving method and apparatus of the PDP according to the present invention is Δ4.81E-09 C / cm ² at the positive wall charge and Δ4.42E-09 at the negative wall charge. C / cm ² .

FIG. 12 illustrates an experimental result when driving a three-electrode surface discharge PDP in which silicon oxide is not formed on a partition wall using the conventional driving signals shown in FIG. 9. In this experiment, the sustain pulses (sus1 to sus6) were alternately supplied to the scan electrode and the sustain electrode at a frequency of 167 kHz and 24 pulses, and the voltage of the address electrode was set to 0 V during the sustain period. The results of this experiment show that in the conventional PDP driving method and apparatus, the shaking of the wall charge is Δ6.61E-09 C / cm ² at the positive wall charge and Δ7.31E-09 C / at the negative wall charge. cm ² .

As can be clearly seen from Figs. 11 and 12, when the stabilizing pulses (stp) are supplied to the address electrodes prior to the sustain pulses (sus1 to sus6) and the silicon oxide of low dielectric constant is formed on the partition walls, the wall charges are shaken as compared with the prior art. Can be significantly reduced.

As described above, the method and apparatus for driving a PDP according to the present invention can supply unwanted stabilization pulses to address electrodes prior to sustain pulses, thereby reducing unwanted wall charges accumulated on the partition walls and minimizing the shaking of the wall charge distribution. have. As a result, according to the present invention, image quality can be improved by preventing erroneous discharge or miss discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing a conventional three-electrode plasma display panel.

FIG. 2 is a diagram illustrating an example in which the partition wall illustrated in FIG. 1 is manufactured in a stripe form.

3 is a diagram illustrating an example in which the partition wall illustrated in FIG. 1 is manufactured in a closed type.

4A is a cross-sectional view illustrating an ideal wall charge distribution.

FIG. 4B is a waveform diagram showing discharge generated in the wall charge distribution as shown in FIG. 4A and light output according to the discharge.

5A is a cross-sectional view illustrating a case in which the top wall charges are shaken in the wall charge distribution of FIG. 4A.

5B is a cross-sectional view illustrating a case in which the lower wall charges are shaken in the wall charge distribution of FIG. 4A.

FIG. 6 is a waveform diagram illustrating discharge generated in the wall charge distribution as shown in FIGS. 5A and 5B and light output according to the discharge.

FIG. 7A is a cross-sectional view illustrating a case where partition wall charges are shaken in the wall charge distribution of FIG. 4A.

FIG. 7B is a waveform diagram illustrating discharge generated in the wall charge distribution as shown in FIG. 7A and light output according to the discharge.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to an exemplary embodiment of the present invention.

9 is a waveform diagram illustrating a method of driving a plasma display panel according to the related art.

10 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 11 is a waveform diagram illustrating an experimental result when a three-electrode surface discharge plasma display panel in which silicon oxide is formed on a partition wall using driving signals as shown in FIG. 8.

FIG. 12 is a waveform diagram illustrating experimental results when driving a three-electrode surface discharge plasma display panel in which silicon oxide is not formed on a partition wall using the conventional driving signals as shown in FIG. 9.

<Explanation of symbols for the main parts of the drawings>

10,110: upper substrate 12X, 112X: address electrode

12Y, 112Y: scan electrode 12Z, 12Z: sustain electrode

14, 22: dielectric layer 16: protective film

18: lower substrate 20: phosphor

24: bulkhead 101: timing controller

102: data driver 103: scan driver

104: sustain driver 105: drive voltage generator

Claims (7)

Drive electrodes of the first electrode, the second electrode and the third electrode and a partition wall for partitioning the discharge space of the cell, and a reset period for initializing the cell, an address period for selecting the cell, and a discharge of the cell In the method for driving the plasma display panel divided by the sustain period for maintaining Supplying a plurality of auxiliary pulses to the first electrode during the sustain period to suppress shaking of the wall charge distribution on the partition wall; And supplying sustain pulses to the second electrode after the auxiliary pulses are generated and supplying the sustain pulses to the third electrode after the auxiliary pulses are generated. The method of claim 1, Supplying an initialization waveform to the second electrode during the reset period; And selecting the cell by supplying a scan pulse to the second electrode and a data pulse to the first electrode during the address period. The method of claim 2, And the auxiliary pulse is set to a voltage of the data pulse. Drive electrodes of the first electrode, the second electrode and the third electrode and a partition wall for partitioning the discharge space of the cell, and a reset period for initializing the cell, an address period for selecting the cell, and a discharge of the cell An apparatus for driving a plasma display panel divided by a sustain period for maintaining A wall charge distribution stabilization driver for supplying a plurality of auxiliary pulses to the first electrode during the sustain period to suppress shaking of the wall charge distribution on the partition wall; And a sustain driver for supplying a sustain pulse to the second electrode after the auxiliary pulse is generated and for supplying the sustain pulse to the third electrode after the auxiliary pulse is generated. . The method of claim 4, wherein An initialization driver configured to supply an initialization waveform to the second electrode during the reset period; And an address driver for supplying scan pulses to the second electrode and supplying data pulses to the first electrode during the address period to select the cell. The method of claim 5, wherein The wall charge distribution stabilization driving unit, And the auxiliary pulse is set to the voltage of the data pulse. The method of claim 4, wherein And an oxide film formed on the partition wall.