KR20050024410A - Receiver - Google Patents

Abstract

The time constant of the HCC de-emphasis circuit 15, which has a high cut control function and a de-emphasis function, which is connected to the rear end of the stereo demodulation circuit 14 for demodulating the received signal, is varied based on the reception level.

Description

Receiver {RECEIVER}

Technical Field

The present invention relates to a receiver having a de-emphasis circuit which returns the frequency component of the signal highlighted at the transmitting side to its original after demodulation at the receiving side.

Background

In a receiver, especially an FM (Frequency Modulation) receiver, in addition to the de-emphasis circuit, an HCC (High Cut Control) circuit that attenuates high frequency components of the received signal when the reception level of the received signal decreases and improves hearing performance is provided. It is known that it is provided.

1 is a diagram illustrating a conventional receiver 40.

The receiver 40 shown in FIG. 1 includes an antenna 41, a front end portion 42, an FM detector 43, a stereo demodulation circuit 44, and a de-emphasis circuit 45. have. In addition to performing the tuning processing of the received signal, the front end section 42 also performs processing such as converting a frequency from a carrier frequency band to an intermediate frequency.

The FM detector 43 generates a composite signal composed of L (Left) + R (Right) component signals, L-R component signals, and the like from the received signals processed by the front end section 42. The stereo demodulation circuit 44 further includes an HCC circuit 46 that attenuates the high frequency component (high frequency component or side lobe) of the L + R component signal, and the L component signal and the R component signal from the L + R component signal and the LR component signal. Comprising a calculation circuit 47 for generating two signals. In the stereo demodulation circuit 44, the L-R component signal is mixed with a signal having a frequency of 38 kHz. On the other hand, the L + R signal is input to the HCC circuit 46. In the HCC circuit 46, the L + R component signal attenuates a high frequency component by a path (path S1) passing through as it is, a low pass filter (integrating circuit) composed of the resistor 46-1 and the capacitor 46-2. It branches into two paths of the path (path S2). When the L + R component signal input to the HCC circuit 46 has a sufficiently high reception level, most of the L + R component signals output the signal passing through the path S1. On the contrary, when the reception level is lowered, the path S2 depends on the reception level. The rate at which the signal passing through is output is increased. In this way, the L + R component signal increases the high frequency component of the L + R component signal that becomes noise as the reception level decreases. Therefore, the HCC circuit 44 increases the L + R component signal that has passed through the path S2 in accordance with the reception level, thereby increasing the L + R component. The high frequency component of the signal is attenuated. In other words, the cutoff frequency of the low pass filter is reduced as the reception level decreases. In addition, the control which attenuates a high frequency component according to a reception level in this way is performed based on reception of RSSI (Received Signal Strength Indicator) input to the mixer circuit 46-3. The RSSI circuit is a signal having information of the reception level.

2 is a diagram illustrating a circuit configuration of the HCC circuit 46.

As shown in Fig. 2, for example, the mixer circuit 46-3 is a differential amplifier composed of six transistors 50, a constant current circuit 51, and the like, and flows in the path S2 based on the difference between the RSSI signal and the reference voltage. The ratio of the L + R component signal is controlled.

As shown in FIG. 1, the LR component signal mixed with the L + R component signal and the 38 kHz signal output from the mixer circuit 46-3 is divided into the L component signal and the R component signal in the arithmetic circuit 47. The high frequency component is attenuated by the low pass filter which is respectively output to the de-emphasis circuit 45 and consists of the resistor 45-1 and the capacitor | condenser 45-2 (attached externally).

However, the cutoff frequency of the low pass filter composed of the resistor 46-1 and the condenser 46-2 of the HCC circuit 46 in the conventional receiver 40 varies around about 1 kHz and where the frequency is low. Therefore, it is necessary to increase the capacity of the capacitor 46-2, and it is difficult to configure it inside the IC chip.

As described above, in the conventional receiver, since the capacitor 46-2 of the HCC circuit 46 is externally mounted, the capacitor must be mounted on the printed board in addition to the IC chip, so that the mounting area of the printed board is increased, It caused the enlargement of the whole apparatus.

Another problem was that the cost of components of the externally mounted capacitor and the production cost of the externally mounted capacitor for the actual equipment to the printed board were increased.

Accordingly, an object of the present invention is to provide a receiver capable of suppressing an increase in the mounting area and cost of a printed board.

Disclosure of the Invention

In this invention, in order to solve the said subject, it comprised as follows.

That is, the receiver of the present invention is characterized by varying the time constant of the high frequency attenuation circuit having a high cut control function and a de-emphasis function connected to a rear end of the demodulation circuit for demodulating the received signal based on the reception level. do.

As a result, components necessary for the high-cut control function and components necessary for the de-emphasis function can be shared, so that, for example, the externally mounted capacitor required for the HCC circuit in the conventional receiver can be omitted, thereby reducing the IC chip area and cost. The increase can be suppressed.

In addition, the receiver of the present invention comprises: demodulation means for demodulating a received signal; Attenuation means connected to a rear end of the demodulation means for attenuating high frequency components of the received signal; Variable means for varying a cutoff frequency of the attenuation means; And generating means for generating a control signal for controlling the operation of the variable means based on the reception level of the received signal.

In addition, the receiver may cause the generating means to generate a control signal for controlling the operation of the variable means based on the reception level of the FM received signal when receiving the FM received signal.

The receiver may cause the generating means to generate a control signal such that the cutoff frequency of the attenuation means decreases as the reception level of the received signal decreases.

This allows the attenuation means to share a component for attenuating the high frequency components of the received signal in accordance with the reception level and a component for attenuating the reception level of the received signal to a predetermined reception level. The externally mounted capacitor necessary for the HCC circuit in the present invention can be omitted, and an increase in the IC chip area and cost can be suppressed.

In addition, the receiver of the present invention comprises: demodulation means for demodulating the received FM signal; A resistor composed of two or more resistors connected to the rear ends of the demodulation means; Switching means for switching the resistance of the resistor; A condenser for attenuating high frequency components of the demodulated FM signal by combination with the resistor; And generating means for generating a control signal for controlling the switching operation of the switching means based on the reception level of the FM signal.

The receiver may cause the generating means to generate a control signal such that the resistance value of the resistor increases as the reception level of the received signal decreases.

Thereby, the capacitor for attenuating the high frequency component of the FM received signal and the capacitor for attenuating the reception level of the FM received signal to a predetermined reception level can be shared according to the reception level of the FM received signal. Since the external capacitor required for the HCC circuit in the FM receiver can be omitted, an increase in IC chip area and cost can be suppressed.

In addition, the receiver of the present invention comprises: a receiver for receiving an FM signal or an AM signal, comprising: demodulation means for demodulating the FM signal or the AM signal; A resistor composed of two or more resistors connected to the rear ends of the demodulation means; Switching means for switching the resistance of the resistor; A condenser for attenuating high frequency components of the demodulated FM signal or AM signal by combination with the resistor; First generating means for generating a control signal for controlling a switching operation of the switching means based on the reception level of the FM signal; Second generating means for generating an AM control signal for controlling a switching operation of said switching means based on said AM signal; And selection means for selecting one of the control signal or the AM control signal based on the received reception signal and outputting the selected control signal to the switching means.

The first generating means of the receiver may generate a control signal so that the resistance value of the resistor increases as the reception level of the FM signal decreases.

The receiver further includes third generating means for generating an FM control signal for controlling the switching operation of the switching means, in order to change the time constant of the de-emphasis function, wherein the selection means comprises: Based on the received reception signal, one of the control signal, the AM control signal, and the FM control signal may be selected and output to the switching means.

Thereby, a capacitor for attenuating the high frequency components of the FM received signal according to the reception level of the FM received signal, a capacitor for attenuating the reception level of the FM received signal to a predetermined reception level, and a low pass filter of the AM received signal Since the capacitors can be shared, for example, the externally mounted capacitors required for the HCC circuit, the low pass filter, and the like in the conventional AM and FM receivers can be omitted, thereby increasing the IC chip area and cost.

Brief description of the drawings

The present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings.

1 is a diagram illustrating a conventional receiver.

2 is a diagram illustrating a circuit configuration of an HCC circuit.

3 is a diagram illustrating a receiver of an embodiment of the present invention.

4 is a diagram illustrating a switching operation of a switch of the HCC de-emphasis circuit.

Fig. 5A is a diagram showing a switch driving circuit 23 composed of a NOT circuit and a NAND circuit.

5B is a diagram illustrating a specific example of the circuit configuration of the switch.

6 is a diagram for explaining a receiver which is another embodiment.

7 is a diagram for explaining a receiver which is another embodiment.

Best Mode for Carrying Out the Invention

Embodiments of the present invention will be described below with reference to the drawings.

3 is a diagram illustrating a receiver of an embodiment of the present invention.

As shown in Fig. 3, the receiver 10 includes an antenna 11, a front end section 12, an FM detector 13, a stereo demodulation section 14 (demodulation means), and a high cut control function. An HCC de-emphasis circuit (15 (high frequency attenuation circuit)) having a de-emphasis function, a control circuit 16 (generating means), and an A / D conversion circuit 17 are provided. In addition to executing the tuning process of the received signal, the front end unit 12 executes various processes such as a process of converting the frequency of the received signal from the carrier frequency band to the intermediate frequency.

The FM detector 13 generates a composite signal composed of an L + R component signal, an L-R component signal, and the like from the received signal processed by the front end unit 12. In addition, the stereo demodulation circuit 14 includes an arithmetic circuit 14-1 for generating two signals of the L component and the R component signal from the L + R component signal and the L-R component signal. The L signal and the R signal are input to the HCC deemphasis circuit 15.

The HCC de-emphasis circuit 15 switches the resistance values of the eight resistors 18 (18-1, 18-2, ..., 18-8) and the resistor 18 (resistor) in accordance with the reception level of the received signal. And a switch 19 (switching means or variable means) for varying the count-off frequency of the HCC de-emphasis circuit 15 and the condenser 20. The high frequency component of the received signal is attenuated by the configuration (damping means) composed of the resistor 18 and the capacitor 20. In addition, although the L signal part and the R signal part have the same code | symbol, the resistance 18 and the capacitor | condenser 20 can be set arbitrarily, respectively.

The feature of the receiver 10 of the present embodiment is that the condenser (externally mounted; 45-2) of the conventional de-emphasis circuit 45 is also used for the condenser (externally mounted; 46-2) of the HCC circuit 46. It is used. First, the RSSI signal having the information of the reception level is converted into a digital signal by the A / D conversion circuit 17. Then, the control circuit 16 switches the eight resistors 18 of the HCC de-emphasis circuit 15 to the switch 19 based on the result of comparing the digital signal with the reference value, thereby the resistor 18 and the capacitor. Control so that the time constant of the low pass filter composed of (20) is changed (or the cut off frequency of the low pass filter composed of the resistor 18 and the condenser 20 is changed). That is, when the RSSI signal is large enough (when the reception level is high), the resistor 18 is selected so that the time constant of the low pass filter becomes small (so that the cutoff frequency of the low pass filter becomes large), and the RSSI When the signal is small (as the reception level is lowered), the resistor 18 is selected so that the time constant of the low pass filter is large (so that the cutoff frequency of the low pass filter is small). In addition, since the capacitances of the two capacitors of the capacitor 45-2 of the de-emphasis circuit 45 and the capacitance of the capacitor 46-2 of the HCC circuit 46 in the related art are of the same magnitude, Capacitors can be shared.

In this manner, the capacitor included in the HCC circuit for attenuating the high frequency component of the received signal and the capacitor included in the de-emphasis circuit can be shared, so that the externally mounted capacitor provided in the HCC circuit 46 of the conventional receiver 40 can be shared. While (46-2) can be omitted, the output terminal (pin) for connecting the IC chip and the capacitor 46-2 can be eliminated, and the printed circuit board area can be made small. In addition, since one externally mounted capacitor can be omitted, an increase in cost can be suppressed.

In addition, in the receiver 10 of the present embodiment, the switch 19 is switched in accordance with the reception level to select which of the eight resistors 18 to use. This is because the control signal for switching is a 3-bit digital signal. In the case of controlling the time constant more finely, it is possible to increase the number of resistors and the number of bits of the control signal.

Next, the switching operation of the switch 19 of the HCC de-emphasis circuit 15 will be described in detail.

4 is a schematic diagram illustrating the switching operation of the switch 19 of the HCC de-emphasis circuit 15. In addition, the switching operation of the switch 19 is the circuit configuration of the signal of either the L signal or the R signal, and the operation of switching the time constant of the HCC de-emphasis circuit 15 in the L signal in FIG. Explain.

As shown in FIG. 4, the HCC de-emphasis circuit 15 includes eight resistors 18 (18-1, 18-2, ..., 18-8) and eight resistors corresponding to the eight resistors 18, respectively. The switch 19; 19-1, 19-2, ..., 19-8 and the condenser 20 are provided. The terminals of the eight switches 19 are connected between the eight resistors 18, respectively, and the other terminal of the switch 19 is connected to the capacitor 20.

First, it demonstrates when reception level is more than an upper limit (predetermined value). The control circuit 16 outputs a control signal for decreasing the time constant of the HCC de-emphasis circuit 15 when the reception level is at least the upper limit value. That is, if the A / D converted RSSI (signal is output to the control circuit 16 and the difference between the digital signal (RSSI signal) and the reference signal is greater than or equal to the upper limit value in the A / D conversion circuit 17, the switch 19- 1) outputs a control signal for turning ON 1 from the control circuit 16. When the switch 19-1 is turned ON, the reception signal (L output signal) turns on the resistor 18-1 and the switch 19-1. When the reception level is sufficiently high (above the upper limit), it is not necessary to attenuate the high frequency components, so the cutoff frequency of the low pass filter of the HCC de-emphasis circuit 15 may be large. The function of the HCC circuit is not necessary, and only the function of the de-emphasis circuit is sufficient.

Next, the case where the reception level is lower than the upper limit (predetermined value) and higher than the lower limit (predetermined value) will be described. When the reception level is lower than the upper limit and higher than the lower limit, the control circuit 16 outputs a control signal for varying the time constant of the HCC de-emphasis circuit 15 in accordance with the reception level. In other words, when the reception level decreases, the time constant of the HCC de-emphasis circuit 15 is increased (the cut-off frequency is decreased). When the reception level increases, the time constant of the HCC de-emphasis circuit 15 is increased. Decrease (increase cutoff frequency). Specifically, when the RSSI signal is A / D-converted, and the difference between the digital signal (RSSI signal) and the reference signal is smaller than the upper limit and larger than the lower limit, the switch 19 corresponding to the signal of the difference between the digital signal and the reference signal; A control signal for turning on one of the switches 19-2, 19-3, 19-4, 19-5, 19-6, and 19-7) is output from the control circuit 16. For example, when the switch 19-4 is turned ON according to the reception level, the received signal is output through the resistors 18-1, 18-2, 18-3, 18-4 and the switch 19-4. Thus, attenuating high frequency components by varying the time constant (cut-off frequency) of the low pass filter in the HCC de-emphasis circuit 15 based on the reception level (high cut control function: for improving hearing characteristics). Function), and at the same time, it is possible to return the highlighted received signal to its original state (de-emphasis function).

Next, the case where the reception level is below the lower limit (predetermined value) will be described. The control circuit 16 outputs a control signal (which decreases the cutoff frequency of the HCC de-emphasis circuit 15) that increases the time constant of the HCC de-emphasis circuit 15 when the reception level is lower than or equal to the lower limit. In other words, when the difference between the digital signal of the RSSI signal and the reference signal is equal to or lower than the lower limit, the control circuit 16 outputs a control signal for turning on the switch 19-8. When the switch 19-8 is turned on, the received signal is output through the resistors 18-1 to 18-8 and the switch 19-8. When the reception level is low enough (below the lower limit), the received signal passes through all the resistors 18 (with the largest time constant) to reduce the cutoff frequency of the low pass filter in the HCC de-emphasis circuit 15. It makes small and a high frequency component attenuates sufficiently.

Here, the structure of the HCC de-emphasis circuit 15 is further demonstrated in detail.

FIG. 5 is a diagram showing a specific example of the HCC de-emphasis circuit 15 composed of a logic circuit such as a NAND circuit or a NOT circuit, and FIG. 5 (a) is composed of a NOT circuit 21 and a NAND circuit 22. FIG. 5B is a diagram showing an example of the circuit configuration of the switch 19. The switch driving circuit 23 for driving the switch 19 is shown. By configuring the switch 19 and the switch driving circuit 23 in this manner, it is possible to mount the HCC de-emphasis circuit 15 other than the capacitor 20 (externally mounted) on the IC chip.

For example, the case where the switch 19-1 is turned ON in the case where the difference between the above-described reception level and the reference signal is equal to or greater than the upper limit (7 or more) will be described.

First, the control circuit 16 switches the 3-bit control signals, 1, 1, and 1 so as to reduce the time constant of the HCC de-emphasis circuit 15 when the reception level and the value of the processing of the reference signal are higher than or equal to the upper limit. Output to SW2, SW1, and SW0 of (23-1), respectively. When the control signals, 1, 1, and 1 are input, the switch drive circuit 23-1 is set to 1 for SW2H, 0 for SW2L, 1 for SW1H, 0 for SW1L, and 0 for SW0H through two NOT circuits 21. 1, 0 is output to SW0L.

Although the switch driving circuit 23-2 is omitted in Fig. 3 (a), the eight logic circuits 24 consisting of the NOT circuit 21 and the NAND circuit 22 (24; 24-1, 24-2, ..., 24-) 8) consists of. The output signal of the logic circuit 24 is input to the two input terminals R1 to R16 of the eight switches 19-1 to 19-8, respectively. When 1, 1, and 1 are input to SW2H, SW1H, and SW0H of the logic circuit 24-1, 1 and 0 are output from R1 and R2. 0 input to R2 of the switch 19-1 is inverted to 1, and as a result, the switch 19-1 is turned ON. At this time, the switches 19-2 to 19-8 other than the switch 19-1 are not turned on because the signals opposite to the switch 19-1, 0 and 1 are input (for example, the switch 19). 0 is entered in R3 of -2, and 1 is input in R4). In this way, when only the switch 19-1 is turned on, the control driver 16 outputs a 3-bit control signal 111 from the control circuit 16 to the switch driving circuit 23-1. For example, when the switch 19-2 is turned on, the control circuit 16 outputs three bits of control signals, 1, 1, and 0 from the control circuit 16 to SW2, SW1, SW0 of the switch drive circuit 23-1. . When the switch 19-8 is turned ON, the control circuit 16 outputs a control signal of three bits, 0, 0 and 0, from the control circuit 16 to the switch driving circuit 23-1.

That is, the control circuit 16 outputs the control signals of 1, 1, and 1 to the switch driving circuit 23-1 when the difference between the reception level and the reference signal indicates a value of 7 or more, and the difference between the reception level and the reference signal is When indicating a value of 0 to 6, a control signal corresponding to the difference value is output to the switch driving circuit 23-1, and when the difference between the reception level and the reference level indicates a negative value, 0, 0 and 0 Control signal is outputted to the switch drive circuit 23-1, and the switch 19 is drive controlled.

In this manner, the time constant of the HCC de-emphasis circuit 15 may be small when the reception level is higher than or equal to any upper limit, and is set to be the largest when the reception level is lower than or equal to any lower limit, and the reception level is smaller than the upper limit and lower than the lower limit. If large, it is set to the time constant based on the reception level. Thus, the time constant in the HCC de-emphasis circuit 15 is varied by the resistor 18 and the capacitor 20 selected by the switch 19 based on the reception level (the cut-off frequency is variable), so that the reception level is low. High frequency components that cause ground noise are attenuated. Thereby, since the HCC circuit for attenuating the high frequency components and the deemphasis circuit for attenuating the received signal can be configured in accordance with the reception level of the received signal, the printed circuit board area constituting the receiver 10 can be reduced. Will be.

In addition, this invention is not limited to embodiment mentioned above, A various structure or shape can be taken within the range which does not deviate from the summary of this invention.

6 is a diagram for explaining a receiver 30 of another embodiment.

As shown in FIG. 6, the receiver 30 includes an antenna 11, a front end portion 12, an FM detector 13, a stereo demodulation portion 14, an HCC de-emphasis circuit 15, Control circuit 16 (first generating means: means for generating a control signal for varying the time constant of the high cut control function in the HCC de-emphasis circuit 15), A / D conversion circuit 17, AM front end section 31, AM detector 32, and HCC DM for various processing such as tuning of AM (Amplitude Modulation) signals and converting frequencies of AM signals from carrier frequency bands to intermediate frequencies. An AMFM switching unit 33 for switching the signal output to the periphery circuit 15 to either the composite signal output from the stereo demodulation circuit 14 or the AM reception signal output from the AM detector 32; And a circuit 34 (selection means). In addition, the same code | symbol is attached | subjected about the thing of the structure same as the structure of the receiver 10 of FIG. 3, and the description is abbreviate | omitted. In addition, the stereo demodulator 14 and the AM detector 32 may be combined to form one demodulation circuit (demodulation means).

The difference from the receiver 10 is that the selection circuit 34 is attached to the control circuit 16. The signal output from the selection circuit 34 is a signal for controlling the operation of the switch (switching means). In addition to the signal for controlling the operation of the switch 19 in accordance with the reception level of the FM reception signal, the selection circuit 34 has a resistance value of the resistor 18 in the HCC de-emphasis circuit 15 when receiving an AM signal. The LPF time constant control signal for AM to be a fixed resistance value based on the AM signal, the reception band switching signal for switching these control signals, and the de-emphasis function according to the country (frequency different for each country) used. A de-emphasis time constant switching signal for changing the time constant is input. The AM LPF time constant control signal and the de-emphasis time constant switching signal are each an AM generating circuit (second generating means) and a time constant switching circuit (third generating means: HCC DM) which are not shown in FIG. Means for generating a control signal for varying the time constant of the de-emphasis function in the furnish circuit 15). The AM LPF time constant control signal can arbitrarily change the resistance value of the resistor 18 in the HCC de-emphasis circuit 15 by changing the set value of the control signal, for example, in a production line process. . In addition, the time constant of the de-emphasis function in the HCC de-emphasis circuit 15 can be varied by inputting the de-emphasis time constant switching signal to the control circuit 16 in the receiver 10 of FIG. 3. .

For example, the selection circuit 34 determines, based on the reception band switching signal, whether to control the FM reception signal or the AM reception signal, and outputs a predetermined control signal to the switch 19. That is, the selection circuit 34 selects the switch 19 according to the reception level of the FM reception signal, as described above, if the information included in the reception band switching signal is instruction information for controlling the FM reception signal. A control signal for attenuating high frequency components is output. On the other hand, if the information included in the reception band switching signal is instruction information for controlling the AM reception signal, the switch 19 is selected based on the AM LPF time constant control signal (AM control signal), The high frequency component of the AM reception signal is attenuated by the cutoff frequency. In addition, the selection circuit 34 controls the switch 19 to be a time constant corresponding to each country by the de-emphasis time constant switching signal.

As described above, in the receiver for receiving the FM and AM reception signals, when the FM reception signal is received, the capacitor of the HCC circuit and the capacitor of the de-emphasis circuit can be shared, and when the AM reception signal is received, the HCC By selecting the switch 19 of the de-emphasis circuit 15, it is possible to switch to the LPF time constant (a cut-off frequency required for receiving the AM received signal) for the AM received signal. In this way, the capacitor 20 can be shared by the HCC circuit, the de-emphasis circuit, and the LPF for AM, so that an increase in the printed circuit board area and cost can be suppressed.

In the receiver 10 or 30 of the present embodiment, the setting of the upper limit value and the lower limit value when controlling the operation of the switch 19 and the setting of the reference signal input to the control circuit 16 is performed so as to perform the microcomputer or the like. You may.

7 is a figure explaining the receiver of another embodiment. 7 also shows only the features.

A characteristic feature of the receiver shown in FIG. 7 is that eight resistors 18 of the HCC de-emphasis circuit 15 shown in FIG. 3 are connected in parallel.

As shown in FIG. 7, the resistors 18 (18-1 to 18-8) of the HCC de-emphasis circuit 35 are connected in parallel and are connected to the reception level of the received signal in the same manner as the HCC de-emphasis circuit 15. Based on this, the operation of the switch 19 is controlled. That is, as the reception level is lowered, the resistance value of the resistor is switched so that the cutoff frequency is reduced. Further, for example, the resistors 18 connected in parallel are different resistance values, and as the reception level is lowered from the control circuit 16, the control signal for selecting the resistors 18 having a large resistance value is selected from the switch ( 19) is output.

In this way, even when a resistor having a different resistance value is connected in parallel, the cutoff frequency can be changed by switching the resistance based on the reception level of the reception signal.

In addition, in the receiver of the present embodiment, in order to reduce the printed board area, the receiver and the de-emphasis circuit are configured to have both functions, so that the resistance, the control circuit 16, and the like increase as compared with the conventional receiver. Although the board | substrate area seems to become large, compared with the installation space of an external mounting capacitor, the increase of the area on the IC chip and the area by the control circuit 16 is very small.

According to the receiver of the present invention, the time constant of the high frequency attenuation circuit having the high cut control function and the de-emphasis function connected to the rear end of the demodulation circuit for demodulating the received signal is varied based on the reception level. As a result, components necessary for the high-cut control visual and de-emphasis functions can be shared, for example, the externally mounted capacitor can be omitted, so that the printed circuit board area can be reduced, so that the parts cost and the actual equipment are used. The cost can also be suppressed.

In addition, since the output terminal (pin) for connecting the IC chip and the capacitor can be eliminated, the printed circuit board area can be made smaller.

Moreover, since the printed circuit board area can be made small, increase in cost can be suppressed.

Claims (9)

And a time constant of a high frequency attenuation circuit having a high cut control function and a de-emphasis function connected to a rear end of the demodulation circuit for demodulating the received signal, based on the reception level. Demodulation means for demodulating a received signal; Attenuation means connected to a rear end of said demodulation means for attenuating high frequency components of a received signal; Variable means for varying a cutoff frequency of the attenuation means; And And generating means for generating a control signal for controlling the operation of the variable means based on the reception level of the received signal. The method of claim 2, And the generating means generates a control signal for controlling the operation of the variable means based on the reception level of the FM received signal when the receiver receives the FM received signal. The method of claim 2, And the generating means generates a control signal such that the cutoff frequency of the attenuation means decreases as the reception level of the received signal decreases. Demodulation means for demodulating the received FM signal; A resistor composed of two or more resistors connected to a rear end of the demodulation means; Switching means for switching the resistance of the resistor; A condenser for attenuating high frequency components of the demodulated FM signal by combination with the resistor; And And generating means for generating a control signal for controlling the switching operation of the switching means based on the reception level of the FM signal. The method of claim 5, wherein And the generating means generates a control signal such that the resistance value of the resistor increases as the reception level of the received signal decreases. A receiver for receiving an FM signal or an AM signal, Demodulation means for demodulating the FM signal or the AM signal; A resistor composed of two or more resistors connected to a rear end of the demodulation means; Switching means for switching the resistance of the resistor; A condenser for attenuating high frequency components of the demodulated FM signal or AM signal by combination with the resistor; First generating means for generating a control signal for controlling a switching operation of the switching means based on the reception level of the FM signal; Second generating means for generating an AM control signal for controlling a switching operation of said switching means based on said AM signal; And And selecting means for selecting one of the control signal or the AM control signal based on the received signal and outputting the selected signal to the switching means. The method of claim 7, wherein And the first generating means generates a control signal so that the resistance value of the resistor increases as the reception level of the FM signal decreases. The method of claim 7, wherein And third generating means for generating an FM control signal for controlling the switching operation of the switching means, in order to change the time constant of the de-emphasis function, And the selection means selects one of the control signal, the AM control signal, and the FM control signal based on the received signal and outputs the selected signal to the switching means.