KR20050022003A - A method to measure transmission delay between 1394 bridges - Google Patents

Abstract

Instead of stringent dedicated bus transactions such as ping and self-identification, the timing delay for the IEEE 1394 serial bus is determined by the asynchronous transaction request and the responding acknowledgment. Therefore, timing can be determined from asynchronous transactions that occur for other purposes (eg, read or write) or initiated for timing determination.

Description

A METHOD TO MEASURE TRANSMISSION DELAY BETWEEN 1394 BRIDGES}

FIELD OF THE INVENTION The present invention generally relates to serial bus timing, and more particularly to determining bus delay associated with data communication over an IEEE 1394 serial bus.

The Institute for Electrical and Electronic Engineers (IEEE) standard 1394 {often referred to as "FireWire" is a serial bus standard developed as a low-cost alternative to parallel buses, which are small physical domains. Limited to, does not support plug-and-play, and does not support isochronous applications The standard is the most modern personal computer in that many devices connected via USB can alternatively be connected via IEEE 1394. It is similar to the universal serial bus (ISB) standard available for IEEE 1394, if supported, to increase the transfer rate, up to 400 Mb / s (per second) for devices such as hard disk drives, motion video recorders, sound mixers, etc. supports Mb) or more of the transmission rate 16 exabytes (exabyte:. theoretical address space of 10 ^{to 18} bytes), each Scalability mechanisms such as connection to a single computer on up to 1024 buses with as many as 64 devices, and hot-swapping and auto-detection or auto-discovery of connected / disconnected devices Other advantageous features, such as support for, make IEEE 1394 a versatile standard.

In order to use longer cables than specified by the standard, or to allow the physical layer to have a longer delay (eg, an arbitration gap delay) than the maximum allowed by the physical layer, the timing mechanism is for example. It is necessary to determine the bus arbitration gap count. Therefore, there is a need in the prior art for precise timing mechanisms for evaluating IEEE 1394 bus delays.

1 illustrates a data processing system and / or network comprising a serial bus in which transmission delay is determined in accordance with one embodiment of the present invention.

2 is a timing diagram illustrating determination of serial bus transmission delay in a data processing system and / or network in accordance with an embodiment of the present invention.

3 is a high level flow diagram illustrating a method of determining serial bus transmission delay in a data processing system and / or network in accordance with an embodiment of the present invention.

In order to address the aforementioned deficiencies of the prior art, the primary object of the present invention is to use asynchronous transactions instead of strict dedicated bus transactions such as ping and self-identification, for use in timing determination for IEEE 1394.1 systems or networks. To determine the timing delay from the requesting and responding acknowledgment. Therefore, timing may be determined from asynchronous transactions that occur for other purposes (eg, read or write) or initiated to determine timing.

The foregoing description has described rather broadly the features and technical advantages of the present invention so that those skilled in the art can better understand the following detailed description of the invention. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. Those skilled in the art will appreciate that those skilled in the art may readily use the disclosed concepts and specific embodiments as a basis for designing modifications or other structures for carrying out the same purposes of the present invention. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of the invention in its broadest form.

Before beginning the description, it will be advantageous to describe the definitions of specific words or phrases used throughout this patent specification: the terms “comprising,” “comprising,” as well as their terms mean simple inclusion without limitation; The term “or” is generic and means and / or; The phrases "associated with" and "associated with", and their terms, include, within, interact with, connect to, or connect to, or bind to In conjunction with, in communication with, cooperating with, inserting in, juxtaposed with, having a boundary of, having a characteristic of, and the like. There is; The term "controller" means any device, system or portion thereof that controls at least one operation, whether implemented in hardware, firmware, software or some combination of at least two of them. It should be noted that the function associated with any particular controller may be centralized or distributed even if it is local or remote. It will be understood by those skilled in the art that definitions of specific words and phrases are provided throughout this patent specification and that such definitions apply in most cases to past and future use of such defined words and phrases in most cases.

For a more complete understanding of the present invention and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals indicate similar objects.

1 to 3, and various embodiments described below used in the present patent specification to explain the principles of the present invention, are merely examples, and should not be considered as limiting the scope of the present invention. Those skilled in the art will appreciate that the principles of the present invention may be implemented in any suitably arranged device.

1 illustrates a data processing system and / or network comprising a serial bus in which transmission delay is determined in accordance with an embodiment of the present invention. The data processing system 100 includes a first device 101, such as a personal computer, and a second device, which may be an external hard disk drive or other computer or peripheral such as a compact disk read / write drive, a digital camera, or the like ( 102). Devices 101 and 102 are communicatively coupled by a serial bus 103 that generally conforms to the IEEE 1394a-2000 standard. Optionally, device 101 (or device 102) may include a bridge controller 104 to allow device 101 to communicate over another IEEE 1394a-2000 bus (not shown). Each device 101 and 102 includes a physical (PHY) and a link (LINK) layer in accordance with the IEEE 1394a-2000 standard. The bridge controller 104 in the device 101 is also a separate and independent operation coupled by routing and glue logic for communication over both the bus 103 and the other IEEE 1394a-2000 buses described above. It can include physical and link layers.

Those skilled in the art will recognize that the complete configuration and operation of the data processing system 100 is not shown in the figures or described herein. Instead, only the systems unique to or necessary to understand the present invention are shown and described herein. The rest of the system will be constructed and operated according to the prior art.

Moreover, although devices 101 and 102 are shown in the figure as being directly connected, devices 101 and 102 may alternatively be connected via one or more intermediate nodes coupled to serial bus 103.

Devices 101 and 102 communicate over serial bus 103. One proposed technique for determining a transmission delay for communication over the bus 103 is to allow the bridge controller 104 in the device 101 to respond with a self-identifying (SID) packet to the physical layer of the device 102. Involves sending out a physical layer "ping" packet that instructs. The link layer in bridge controller 104 then transmits the length of time that bus 103 remains idle, that is, the transition-to-data-end of the ping packet is transmitted. Time the delay until the transition-to-beginning-of-data prefix of the self-identifying response packet from time. This information allows the determination of the worst case timing for the transmission channel to set the gap count to optimize the bus 103.

In the present invention, rather than using ping packets and self-identifying responses, asynchronous transaction request and acknowledgment (ACK) responses are used. The delay from the transmission of the transition-data-end of the asynchronous transaction request until the receipt of the transition-start-data prefix of the acknowledgment packet is measured to determine the serial bus transmission delay. If an asynchronous transaction request is sent only to determine the timing delay, it is desirable that the read request be used because the write request may cause undesirable side effects. However, in the present invention, the bus period need not only be used to determine the bus timing as in the proposed ping method. In the present invention, the timing delay can be determined in relation to any asynchronous (eg read or write) transaction. Moreover, timing can optionally be determined periodically with each asynchronous transaction.

The timing technique of the present invention does not need to exclude the ping method described above. Instead, timing may be determined periodically from an asynchronous transaction whenever an asynchronous transaction occurs, with the ping method used to determine the timing delay for an extended interval of a predetermined length where no asynchronous transaction occurs. In this way, the timing delay can typically be determined using an asynchronous transaction on an opportunistic basis and, if necessary, using the ping method.

2 is a timing diagram illustrating determination of serial bus transmission delay in a data processing system and / or network in accordance with one embodiment of the present invention. The delay from the transmission of an asynchronous transaction request from the first device to the receipt of an acknowledgment from the second device can be easily measured by logic in the link layer of the first device.

3 is a high level flow diagram for a method of determining serial bus transmission delay in a data processing system and / or network in accordance with an embodiment of the present invention. The method 300 begins with a timing determination that begins (step 301). An asynchronous transaction request (eg, read or write) is sent (step 302). Upon receipt of a response acknowledgment packet (step 303), the elapsed interval is determined (step 304). The method is then idle until another timing decision is initiated.

As described above, the timing delay may be determined based on the timing each time an asynchronous transaction occurs. Thus, bus transactions can be monitored for suitable asynchronous transactions. Moreover, whenever a predetermined time interval elapses without an asynchronous transaction on the bus, the timing may be determined by the ping method, or the asynchronous transaction disclosed for this purpose.

The present invention allows timing determination for IEEE 1394a-2000 systems and networks without necessarily requiring bus transactions for this purpose only. At this time, the timing can be used to optimize the bus. For example, the determined timing interval can be used to set the bus arbitration gap count.

Although the invention has been described in the context of a full functional system, at least a portion of the mechanisms of the invention may be dispensed in the form of machine usable media containing instructions in various forms, and the invention may be used to actually perform the distribution. It is important to note that the same applies regardless of a particular type of single support medium. Examples of machine usable media include, but are not limited to, nonvolatile hard-coding type media such as read only memory (ROM), or erasable electrically programmable read only memory (EEPROM), floppy disk, hard disk drive, and compact disk read only. Recordable type of media such as memory (CD-ROM) or digital versatile disk (DVD), and transmission type of media such as digital and analog communication links.

Although the present invention has been described in detail, various changes, substitutions, variations, improvements, nuances, step changes, fewer forms, modifications, corrections, enhancements, and duplications of the invention described herein are in the broadest form. And one of ordinary skill in the art will appreciate that the disclosure can be made without departing from the scope thereof.

As noted above, the present invention generally relates to serial bus timing, and more particularly, to determining bus delays associated with data communication over an IEEE 1394 serial bus.

Claims (20)

A system for determining a transmission delay, A controller 104 in a first device 101 coupled to a second device 102 by an IEEE 1394 serial bus 103, the controller 104 between an asynchronous transaction request packet and an acknowledgment packet that responds. And a controller (104) for receiving an interval of and using the interval to determine a transmission delay between the first and second devices (101, 102). The system of claim 1, wherein the controller (104) measures the interval. 2. The first and second devices (101, 102) of claim 1, wherein the controller 104 is configured on an opportunistic basis whenever an asynchronous transaction is initiated on the serial bus 103. System for determining a transmission delay. The system of claim 1, wherein the first and second devices (101, 102) are computers. 5. The system of claim 4, wherein the first and second devices (101, 102) are coupled via an intervening node on the IEEE 1394 serial bus (103). The system of claim 1, wherein the first device (101) is a computer and the second device (102) is a peripheral. The system of claim 1, wherein the controller (104) calculates the interval from the acknowledgment packet responsive to the asynchronous transaction request. A system for determining a transmission delay, The first device 101, The second device 102, An IEEE 1394 serial bus 103 coupling the first and second devices 101, 102, As controller 104 in the first device 101, the controller 104 receives an interval between an asynchronous transaction request packet and a response acknowledgment packet, and between the first and second devices 101, 102. Using the interval to determine the transmission delay, the controller 104 A system for determining a transmission delay. 10. The system of claim 8, wherein the controller (104) measures the interval. 9. The transmission according to claim 8, wherein the controller (104) is configured to delay the transmission between the first and second devices (101, 102) based on an appropriate time each time an asynchronous transaction is initiated on the serial bus (103). System for determining a transmission delay. 10. The system of claim 8, wherein the first and second devices (101, 102) are computers. 12. The system of claim 11, wherein the first and second devices (101, 102) are coupled via an arbitration node on the IEEE 1394 serial bus (103). 10. The system of claim 8, wherein the first device (101) is a computer and the second device (102) is a peripheral device. 10. The system of claim 8, wherein the controller (104) calculates the interval from a timestamp in the asynchronous transaction request and responding acknowledgment packet. A method of determining a transmission delay between first and second devices 101, 102 coupled by an IEEE 1394 serial bus 103, Receiving an interval between an asynchronous transaction request packet and a response acknowledgment packet; Using the interval to determine a transmission delay between the first and second devices (101, 102) And a transmission delay. 16. The method of claim 15, further comprising measuring the interval. 16. The method of claim 15, further comprising determining a transmission delay between the first and second devices (101, 102) based on an appropriate time each time an asynchronous transaction is initiated on the serial bus (103). , How to determine the transmission delay. 16. The method of claim 15, further comprising determining a transmission delay between two computers. 16. The method of claim 15, further comprising determining a transmission delay between two computers coupled via an arbitration node on the IEEE 1394 serial bus (103). 16. The method of claim 15, further comprising determining a transmission delay between a computer and a peripheral device.