KR20050020837A - Mram in-pixel memory for display devices - Google Patents

Abstract

Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. The memory circuit 25 includes a memory element for storing a drive setting, and a reading circuit (for example, a flip-flop circuit 64, etc.) for reading the stored drive setting. The memory element comprises two MRAMs 60 and 62, each of which is connected to an input of a flip-flop circuit 64, respectively. The drive circuit 26 is connected to the readout circuit and the pixel display electrode 27, and according to the read-our drive setting using a drive current that does not pass through the MRAM 60, 62, the pixel display electrode 27 ). There is provided a display device 1 comprising a plurality of pixels 20 connected to one memory circuit 25 and a driving circuit 26, respectively.

Description

Pixel and in-pixel memory and display devices {MRAM IN-PIXEL MEMORY FOR DISPLAY DEVICES}

The present invention relates in particular to in-pixel memories and in-pixel memory circuits for display devices. The present invention particularly provides, but is not limited to, an in-pixel memory circuit in an active matrix liquid crystal display device.

Known display devices include liquid crystal, plasma, polymer light emitting diodes, organic light emitting diodes, and field emission display devices. Such devices typically include an array of pixels consisting of rows and columns. In an active matrix display device, each pixel is each connected to one or more switching devices, typically thin film transistors or the like, to form an array of pixels and the switching device. In operation, pixels are addressed according to an addressing scheme, whereby each pixel is displayed in each frame displayed as display data (e.g. video) indicating the intensity level at which the pixel is displayed. Are refreshed regularly. In general, the addressing scheme selects pixels on a row-by-row basis and provides individual intensity levels on a column-by-column basis.

One of the improvements in the field of display devices is to provide in-pixel memory, thereby providing a respective memory device for each pixel, such that the memory devices are aligned in an array corresponding to the pixel array. Then, static images can be displayed without refreshing, thereby saving power. This is a potentially particularly advantageous display device for portable devices such as mobile phones, cordless phones, personal digital assistants (PDAs) and the like.

It is known to use static random access memory (SRAM) and dynamic random access memory (DRAM) circuits for such in-pixel memory. Typically, only one memory device (consisting of one circuit) is provided for each pixel. In addition to the pixel and switching device arrays, separate arrays of SRAM or DRAM circuits are provided. This includes other overall manufacturing processes added to the manufacturing process used for the pixel and switching device arrays, or requires a number of additional masking stages.

Apart from display device technology, there is a magnetoresistive random access memory (MRAM) as a type of memory device, where the tunneling current depends on the magnetization direction of the two so-called magnetic electrodes. MRAM provides non-volatile memory. The use of such memory (in an application independent of the display) is disclosed, for example, in "Magnetoelectronic memories last and last ..." by Mark Johnson (IEEE Spectrum, February 2000, pages 33-40).

One problem associated with the use of MRAM is that it provides several resistance states (eg, as opposed to voltage variations) as its output during operation. In addition, the difference between the resistance states is generally as small as less than 35%. Another problem is that when conventional driving techniques are used for MRAM, current must be transferred through the MRAM to drive the pixel electrode (e.g., to charge the effective capacitance of the liquid crystal layer at that pixel electrode), which is the case in all environments. In other words, a voltage higher than the optimum voltage for using the MRAM may be applied to the MRAM.

1 is a schematic view (not shown to scale) of a liquid crystal display device.

2 is a schematic of a 2x2 portion of a sample of an array of pixels.

3 is a schematic diagram of a simple MRAM stack.

4 is a circuit diagram for an in-pixel memory circuit.

5 is a diagram illustrating a pixel and in-pixel memory device including two MRAMs, one read circuit, and one drive circuit.

6 is a schematic diagram (not shown to scale) of the structural arrangement used for the pixel.

7 is a flowchart illustrating certain process steps used to form an in-pixel memory structure.

FIG. 8 is a cross-sectional view taken between the X point and the X point shown in FIG. 6.

9 is a cross-sectional view (not shown to scale) of the preferred MRAM stack.

10 and 11 illustrate simulation results performed on the in-pixel memory circuit shown in FIG. 4.

The present invention provides an in-pixel memory for a display device using MRAM technology to solve the above problems.

In a first aspect, the present invention provides a memory circuit including at least one MRAM connected to a read circuit and a drive circuit connected to the read circuit. The drive circuit is configured to drive the pixel electrode directly, that is to say, without driving current passing through the one or more MRAMs to the pixel electrode.

The drive circuit is connected to a reference voltage source (e.g., reference voltage line) and includes switching means (e.g., transistor, etc.) configured to control or enable the flow of drive current to the pixel electrode. It is preferable.

The memory circuit is a reference voltage source from the switching device via a switching device (e.g., a conventional active matrix TFT, etc.) and one end of each of the one or more MRAMs configured to switch according to the received display data. It is preferred to include a bit line extending to.

The readout circuit is preferably a flip-flop circuit. Preferably, the memory circuit comprises two MRAMs, the flip-flop circuit comprises two input stages, and the two MRAMs are each connected to respective input terminals of the flip-flop circuit.

In another aspect, the present invention provides a display device comprising a plurality of pixels and a plurality of memory circuits according to the first aspect, each pixel being connected to or including a respective memory circuit.

In another aspect, the present invention provides a drive line device for an in-pixel memory, in which a drive line (e.g., a bit line, etc.) is configured to drive the first MRAM in a first direction and in a second direction. Configured to pass through or connect to the second MRAM, the first and second directions being in the plane of the drive line and being substantially opposite to each other. This provides the opposite resistance state in the two MRAMs. Preferably, the bit line is configured to pass through the first MRAM and then return or meander to the original line before passing through the second MRAM.

In another aspect, the present invention provides a memory circuit or structure including one or more MRAMs and flip-flop circuits used in applications other than display applications (eg, preferably sensors such as medical sensors, etc.).

Still other aspects are set forth in the appended claims.

Embodiments of the present invention will be described by way of example with reference to the accompanying drawings.

1 is a schematic view (not shown to scale) of the liquid crystal display device 1, which comprises two opposing glass plates 2, 4 (or any other suitable transparent plate). do. The glass plate 2 has an active matrix layer 6 on its inner surface (which will be described in more detail below) and a liquid crystal orientation layer deposited on the active matrix layer 6. (8) is provided. The opposing glass plate 4 has a common electrode 10 on its inner surface and a liquid crystal alignment layer 12 deposited on the common electrode 10. The liquid crystal layer 14 is disposed between the alignment layers 8, 12 of the two glass plates. With the exception of the details of any active matrix to be described below, more specifically except for its relationship with in-pixel memory, the structure and operation of the liquid crystal display device 1 is described in US Pat. No. 5,130,829 (referenced herein). It is the same as the liquid crystal display device disclosed by the said reference.

Certain details of the active matrix layer 6 related to the understanding of this embodiment are shown schematically in FIG. 2 (not shown to scale). The active matrix layer 6 comprises an array of pixels. Typically such an array contains thousands of pixels, but for simplicity, this embodiment will be described for a 2x2 portion which is a sample of the arrays 20 to 23 of pixels as shown in FIG.

In the field of display devices, there are several variations that are sometimes intended to be included in the term "pixel". For convenience, in this example each pixel 20 to 23 is considered to comprise in particular an element of the active matrix layer 6 connected to that pixel. The pixel 20 includes, in particular, a thin film transistor (TFT) 24, an in-pixel memory circuit 25, a drive circuit 26 and a pixel electrode 27. The TFT 24 and pixel electrode 27 are conventional and will be the same, for example, as disclosed in the aforementioned US 5,130,829. The in-pixel memory circuit 25 and the driver circuit 26 are not found in a conventional liquid crystal device and will be described in more detail below.

The other pixels 21-23 are TFTs 28, 32, 36, in-pixel memory circuits 29, 33, 37, drive circuits 30, 34, 38 and pixel electrodes 31, 35, 39, respectively. It includes.

Further, a plurality of address lines are provided as part of the active matrix layer 6 as follows. Pixels 20 and 21 form a first row within the array of pixels, and pixels 22 and 23 form a second row within the array. The first row has a plurality of drive lines and address lines, which, for convenience, enable lines 56, polarity lines 40, and refresh lines 41 that extend across the entire row. , Read line 42, word line 43, and gate line 44. Bit line 45 is also provided to pixel 20, and bit line 46 is provided to pixel 21. Similarly, the second row includes the enable line 57, the polarization line 47, the refresh line 48, the read line 49, the word line 50 and the gate line 51 extending over the entire row, A bit line 52 for the pixel 22 and a bit line 53 for the pixel 23.

Pixels 20 and 22 form a first column within the array of pixels, and pixels 21 and 23 form a second column. The first column has column lines 54. Similarly, the second column has column lines 55. The first column further includes a reference voltage line 58 and the second column further includes a reference voltage line 59. These reference voltage lines may be provided alternately on a row-by-row basis, and of course any other convenient arrangement may be used.

By way of example, further details of the connection of the various pixel components and address lines and the operation of the pixel will be described below, taking the case of pixel 20 as an example, but the following description is directed to the other pixels 21-23. The same can be applied to.

As in the conventional active matrix liquid crystal device, the input terminal to the TFT 24 is connected to the column line 54 and the gate of the TFT is connected to the gate line 44. The output terminal of the TFT 24 is connected to the bit line 45, which is connected to both the in-pixel memory circuit 25 and the reference voltage line 58. The word line 43 is connected to the in-pixel memory circuit 25. Read line 42 is connected to the in-pixel memory circuit. The enable line 56, the polarization line 40, the refresh line 41, and the reference voltage line 58 are connected to the drive circuit 26, respectively. The in-pixel memory circuit has two separate connections towards the drive circuit 26. The drive circuit 26 is connected to the pixel electrode. In the apparatus described above, the bit line 45 and the drive circuit 26 are each connected to the same voltage source of the reference voltage line 58 in this form. Another possibility is to provide different reference voltage sources for the drive circuit 26 separately with different voltage levels as compared to the bit line 45.

During operation, row selection is performed using gate line 44 and column level 54 is used to provide intensity level data, as in a conventional active matrix display device. The output from the TFT 24 is effectively transferred to the in-pixel memory circuit 25 by the bit line 45, and the driving of the pixel electrode 27 by the driving circuit 26 is described in detail below. Likewise controlled by the resulting memory settings of the in-pixel memory circuit 25. The drive circuit 26 and the in-pixel memory circuit 25 may include the enable line 56, the polarization line 40, the refresh line 41, and the read line 42, as described in more detail below. It is additionally controlled by the input provided.

Before describing the features described above in more detail, it will be useful to provide a schematic overview of the operation of the MRAM structure. 3 is a schematic diagram of a simple MRAM stack. The MRAM stack includes two ferromagnetic layers, a free layer 102 and a pinned layer 106, each layer consisting of Ni ₈₁ Fe ₁₉ , for example, of several nanometers. has a thickness and is separated by an insulating layer 104 (e.g., having a thickness of 1 to 2㎚, for example constituted by any Al ₂ 0 _3). Occasionally, the free layer 102 and the pinned layer 106 are referred to as magnetic electrodes, respectively. The insulating layer 104 serves as a tunnel barrier layer. Electrical contacts are formed to the free layer 102 and the pinned layer 106. In this example, these are the bit lines 45 and contacts 108 (in the pixel array of the embodiment shown in FIG. 2, the contacts of each MRAM are made through respective flip-flop connections as described in more detail below. Connected to flip-flop circuit 64). Another electrical supply line is provided below the MRAM stack, but is insulated from the MRAM stack. This other electrical supply line extends in a direction orthogonal to the bit line 45, that is, in a direction passing back and forth through the figure shown in FIG. 3. In this example, this other electrical supply line is a word line 43.

The MRAM stack works as follows. The pinned layer 106 has a fixed magnetization orientation shown by arrow 110. The free layer can be switched between the two magnetization orientations indicated by the double arrows 112. The write currents 114 and 116 are applied to the bit lines 45 and word lines 43 to control or set the magnetization orientation 112 of the free layer. The magnetization orientation 112 of the free layer may be set parallel or antiparallel to the magnetization orientation 110 of the pinned layer 106. These two possibilities are stable when additional write currents 114 and 116 are set to not be applied.

These two states are identifiable, ie readable, as follows. Read currents 118, 120, and 122 may be transferred from bit line 45 to contact 108 through the MRAM stack due to electrons tunneling through tunneling barrier layer 104. The resistance that this current encounters depends on the tunneling resistance of the tunneling barrier layer 104, which has its own magnetization orientation 112 of the free layer 102 at the magnetization orientation 110 of the pinned layer 106. Directly depends on whether they are parallel or antiparallel to the However, the maximum resistance variation of these MRAM stacks is typically only about 35%.

Additional details about the MRAM stack used in this embodiment will be described below, but providing an overview thereof provides details of the array of pixels described in the present invention, in particular through the bottom of the MRAM stack but directly to the MRAM stack. The function of the unconnected word line 43 and the function of the bit line 45 and the contact 108 (in this embodiment connected to the flip-flop circuit 64) directly connected to the respective ends of the MRAM stack. Will help you understand.

4 is a circuit diagram for the in-pixel memory circuit 25. In-pixel memory circuit 25 includes two MRAMs 60 and 62 and flip-flop circuit 64. The two MRAMs 60, 62 function as memory elements, and the flip-flop circuit 64 functions as read circuits for reading the memory state of the memory elements.

The flip-flop circuit 64 includes two p-type transistors (hereinafter referred to as the first p-type TFT 66 and the second p-type TFT 67) implemented as TFTs, and two implemented as TFTs. n-type transistors (hereinafter referred to as first n-type TFT 68 and second n-type TFT 69). The TFTs are actually configured to provide two input chains, which in this example are the first p-type TFT 66 and the first n-type TFT (connected to the first MRAM 60). A first input chain comprising 68 and a second input chain comprising a second p-type TFT 67 and a second n-type TFT 69 connected to the second MRAM 62 in this example. . The remaining end of each input chain of flip-flop circuit 64 is connected to read line 42. The other ends of each of the first MRAM 60 and the second MRAM 62 are connected to the bit line 45 (the operation of the MRAM also includes a word line 43 as described below, although the Not shown in FIG. 4 for clarity). The flip-flop circuit comprises two output contacts, hereinafter referred to as a first output contact 70 and a second output contact 71, which are typically D and in FIG. 4. Two (complementary) flip-flop circuit outputs are shown.

In this example, the detailed connections of the flip-flop circuit 64 components are as follows. Each TFT 66-69 typically includes one gate and two source / drain terminals (hereinafter referred to as first terminal and second terminal). During operation, one of the source / drain terminals functions as the source of the TFT and the other of the source / drain terminals functions as the drain of the TFT. At a particular point in time, the question of which source / drain terminal will function as the source and which source / drain terminal will function as the drain is determined by the polarity of the voltage applied at that point in time.

The first terminal of the p-type TFT 66 and the first terminal of the second p-type TFT 67 are connected to each other, and are also connected to the read line 42. The gate of the first p-type TFT 66, the gate of the first n-type TFT 68, the second terminal of the first p-type TFT, and the first terminal of the second n-type TFT 69 are connected to each other, It is also connected to the 1st output connection part 70. The second terminal of the first p-type TFT 66, the first terminal of the first n-type TFT 68, the gate of the second p-type TFT 67 and the gate of the second n-type TFT 69 are connected to each other. It is also connected to the 2nd output connection part 71. FIG. The second terminal of the first n-type TFT 68 is connected to the first MRAM 60. The second terminal of the second n-type TFT 69 is connected to the second MRAM 62.

During operation, the MRAM is set to a specific resistance state using bit line 45 and word line 43, which is read by flip-flop circuit 64 operating as follows. Initially, the bit line 45 and the read line 42 are at the same potential, for example 0V. The voltages at the two nodes 70, 71 of the flip-flop circuit will be substantially the same. To read the resistance state of the MRAM, a power supply voltage is applied to the flip-flop circuit by switching from 0V to 3V, for example, to have a positive value for the read line bit line. The voltage at both nodes of the flip-flop circuit will initially begin to charge to an average voltage of 1.5V, the voltage on the bit line and read line. The rate of change of voltage on this node will depend on the resistance of the MRAM element, the resistance of the TFT, and the capacitance of the circuit node. The first MRAM element of the MRAM element will have a lower resistance than the second MRAM element. For example, the resistance of the MRAM device 60 may be lower than the MRAM device 62. In this case, the voltage on the flip-flop node 70 will be more positive than the voltage on the node 71. This voltage difference is then amplified by positive feedback in the flip-flop circuit, so node 70 is determined to be 3V, the potential on the read line, and node 71 is determined to be 0V, the voltage on the bit line. .

5 shows additional details of the overall pixel circuit for pixel 20. In addition to the items described above (and indicated with the same reference numerals as previously used), FIG. 5 shows additional details of the drive circuit 26 and the connection of the drive circuit 26 to the pixel electrode 27. . The connection to the pixel electrode 27 is shown in a conventional circuit diagram, which connection is formed by the liquid crystal layer 14 between the pixel electrode 27 and the opposing common electrode 10 and the capacitance C _LC is applied. a connection to a storage capacitor 80 having a connection and a capacitance (C _S) of the liquid crystal cells having shown.

The drive circuit 26 in this example comprises five transistors implemented as TFTs, which in turn are the first drive circuit TFT 75, the second drive circuit TFT 76, and the third drive circuit. The TFT 77, the fourth driver circuit TFT 78, and the fifth driver circuit TFT 79 are referred to. The second drive circuit TFT 76 is a p-type TFT, and the remaining four drive circuit TFTs 75, 77, 78, 79 are n-type TFTs. The driving circuit TFTs 75 to 79 are provided with two outputs D, from the flip-flop circuit 64. Is configured to provide a single drive input to the pixel electrode 27 on the basis of.

In this example, detailed connection portions of the drive circuit TFTs 75 to 78 are as follows. Gates of the first driver circuit TFT 75 and the third driver circuit TFT 77 are connected to each other, and also to the refresh line 41. Gates of the second driver circuit TFT 76 and the fourth driver circuit TFT 78 are connected to each other, and also to the polarization line 40. The first terminal of the first driving circuit TFT 75 is connected to the first flip-flop output connecting portion 70. The first terminal of the third driving circuit TFT 77 is connected to the second flip-flop output connecting portion 71. The second terminal of the first driver circuit TFT 75 is connected to the first terminal of the second driver circuit TFT 76. The second terminal of the third driver circuit TFT 77 is connected to the first terminal of the fourth driver circuit TFT 78. The second terminal of the second driving circuit TFT 76 and the second terminal of the fourth driving circuit TFT 78 are connected to each other, and the first terminal of the fifth driving circuit TFT 79 and the pixel electrode 27 (that is, And the storage capacitor 80 and the liquid crystal capacitance 82. The gate of the fifth driving circuit TFT 79 is connected to the enable line 56. The second terminal of the fifth driving circuit TFT 79 is connected to the reference voltage line 58.

During operation, a signal is applied to the polarization line 40, the refresh line 41, the read line 42, the word line 43, the gate line 44 and the column line 54 as follows. The drive circuit operates as follows to provide the required inputs to the pixel electrode 27, i.e., the storage capacitor 80 and the liquid crystal capacitance 82. One method of operating the circuit shown in FIG. 5 to provide an appropriate drive signal for liquid crystal capacitance is as follows. In general, liquid crystals require a driving voltage waveform in which the polarity of the common electrode of the display alternately varies. This is accomplished by driving the pixel with a positive drive signal and a negative drive signal in accordance with successive pixel refresh periods. In order to refresh the pixel electrode with the positive drive signal, data must first be read from the MRAM. Initially, the word line and the read line are at the same potential, for example 0V. Next, the read line is switched to a positive voltage level, for example 3V, and the flip-flop circuit 64 takes a predetermined state determined by the state of the MRAM. If MRAM 60 has a higher resistance than MRAM 62, node 70 will be determined at a voltage level of 0V and node 71 will be determined at a voltage level of 3V. The pixel is refreshed by taking the signal on the refresh line from a low voltage level to a high voltage level. This turns the two transistors 75 and 77 ON so that the data voltage generated by the flip-flop circuit is transferred to the liquid crystal capacitance. During the positive refresh period, the polarization line remains at a high voltage level. This causes transistor 78 to be turned on, so that the liquid crystal capacitance is charged to a voltage present on node 71, in this example 3V. After the liquid crystal capacitance is charged, the refresh line returns to a low voltage level, causing transistors 75 and 77 to turn off, and the voltage on the read line returns to 0V.

In order to refresh the pixel electrode with a negative drive signal, data must be read again from the MRAM, but in this case it is achieved by bringing the word line to a negative voltage level, for example -3V. If MRAM 60 has a higher resistance than MRAM 62, node 70 will be determined at a voltage level of -3V and node 71 will be determined at a voltage level of 0V. The pixel is refreshed again by taking the signal on the refresh line from a low voltage level to a high voltage level. During the negative refresh period, the polarization line remains at a low voltage level. This causes transistor 76 to turn on, causing the liquid crystal capacitance to charge to the voltage present on node 70, in this example -3V. After the liquid crystal capacitance is charged, the refresh line returns to a low voltage level, causing transistors 75 and 77 to be turned off and the voltage on the read line back to zero volts.

When the resistance of the MRAM 60 is higher than the resistance of the MRAM 62, the liquid crystal capacitance is driven by a voltage waveform with an amplitude of 6V. In general, in the case where a white transmissive TN LC effect is used, the above described situation will cause the pixel to be dark. If the relative resistance of the MRAM is inverted so that the MRAM 60 has a lower resistance than the MRAM 62, the voltage generated at the two nodes of the flip-flop circuits 70 and 71 will also be reversed. As a result, a voltage of 0 V will be applied to the liquid crystal capacitance in both the positive and negative refresh periods. This will cause the liquid crystal pixels to appear light.

The pixel is driven using data from the MRAM, not data supplied through the column line, but the gate line is kept at a low voltage to keep the transistor 24 in an unconductive state.

MRAM 60 and 62 and flip-flop circuit 64 provide a drive signal to the liquid crystal to provide a means to switch the pixel to a bright or dark state. When a pixel is supplied with data from the MRAM, the power consumption of the display is relatively low since the pixel does not need to be supplied with data from an external circuit. However, it would be desirable to drive the display in a second mode capable of reproducing gray levels. This can be accomplished by addressing the pixel with a gray level drive voltage in the same way that a conventional active matrix LC display is addressed using the reference electrode 58, enable line 56 and thin film transistor 79. have. The reference electrodes 58, 59 of the display are addressed with the same signal as the column drive signal in a typical active matrix LCD. Enable lines 56 and 57 are addressed with selection pulses equivalent to the row drive signal in a typical active matrix LCD. In this way, every pixel in the display can be addressed line by line to produce a gray scale image on the display.

In the version of the drive circuit 26 described above, the state of the flip-flop circuit in some environments may not initially be fully determined or completely discharged between the frames. This may lead to a residual state of charge that will result in incomplete reads from the MRAMs. This can be avoided or mitigated by other possible versions of the drive circuit 26, where the p-type TFT 76 and the n-type TFT 77 are omitted, i.e. instead the drive circuit is the n-type TFT 75. ), the n-type TFT 78 and the n-type TFT 79 are included. Then, although the TFTs 75 and 78 can generally change the polarity of the liquid crystal alternately, they can instead be switched on to reset the flip-flop circuit 64.

In the above-described circuit, in particular in the driving circuit 26, the driving current is directly supplied to the pixel electrode 27, that is, directly to the storage capacitor 80 having the capacitance C _S and the liquid crystal cell having the capacitance C _LC . The manner in which it is supplied means that the pixel electrode 27 is driven without a drive current delivered through the MRAMs 60 and 62. Thus, the possibility of applying an excessively high voltage, for example 12V, across the MRAM is avoided.

6 is a schematic diagram (not shown to scale) of the configuration arrangement used for the pixel 20 in this embodiment. For clarity of explanation, the drive circuit 26, the enable line 56, the polarization line 40, the refresh line 41 and the read line 42 are not shown. In addition, the advantages of the configuration arrangement described below can be achieved regardless of items not shown. As shown in FIG. 6, the aforementioned items are word line 43, gate line 44, TFT 24, column line 54, bit line 45, pixel electrode 27 and flip-flop. Circuit 64.

The various components and lines are formed using conventional thin film deposition, masking and etching processes, respectively, as in conventional active matrix display devices. FIG. 7 is a flow diagram illustrating certain process steps used to form the in-pixel memory structure shown in FIG. 6.

In step s2, the word line 43 and the gate line 44 are formed in the same masking stage. Thus, the word line 43 used in connection with the operation of the in-pixel memory and not present in a typical active matrix display device without in-pixel memory is conventional (to provide the gate line 44). It is advantageous in any case in the device to be provided during the necessary masking stage, ie without the need for an additional masking stage. In addition, a dielectric layer may be formed between the MRAM and the word line 43 using a gate dielectric.

In step s4, the first MRAM 60 and the second MRAM 62 are formed as respective MRAM stacks on the word line 43 using a half tone mask. This represents one of only two additional mask steps (compared to conventional active matrix display devices) that are required in this embodiment to add the additional features shown in FIG. 6. As seen from above, the location of the MRAM stack consisting of the first RAM 60 and the second MRAM 62 is indicated by items 84 and 85, respectively.

In step s6, the bit line 45 and the column line 54 are formed in the same masking stage with each other. Thus, bit lines 45 used in connection with the operation of in-pixel memory and not present in a typical active matrix display device without in-pixel memory are typically (to provide column line 54). It is advantageous in any case in the device to be provided during the necessary masking stage, ie without the need for an additional masking stage.

Further, in step s6, i.e., this masking stage, two connecting portions, hereinafter referred to as the first flip-flop connecting portion 86 and the second flip-flop connecting portion 87, are formed. The first flip-flop connection 86 connects the flip-flop circuit 64 to a first contact-via connected to the bottom of the first MRAM 60, i.e., flip-flop The first n-type TFT 68 of the circuit 64 is effectively connected to the first MRAM 60. As viewed from above, the location of the first contact-via is shown as item 88 in FIG. 6. Similarly, the second flip-flop connection 87 connects the flip-flop circuit 64 to a second contact-via connected to the bottom of the second MRAM 62, that is, of the flip-flop circuit 64. The second n-type TFT 69 is effectively connected to the second MRAM 62. As viewed from above, the location of the second contact-via is shown as item 89 in FIG. 6 (the forming of the contact-via is an additional feature shown in FIG. A second masking step of the two additional masking steps required in this embodiment to add a).

Considering the bit line 45 again, other optional useful features are included in this embodiment as follows. The bit line 45 allows current to flow in a direction passing or crossing the first MRAM 60 in a first direction (upward in the figure as indicated by the arrow 90 in FIG. 6), and a second 6 is configured in such a manner that current flows in the direction passing or crossing the second MRAM 62 in the direction (the downward direction of the drawing as shown by the arrow 91 in FIG. 6), the first direction and the second direction. The direction is substantially the opposite direction (in the plane of the bit line). Within one MRAM stack, the current creates a magnetic field in an outward-to-inward direction (i.e., the bottom of each MRAM stack), while within another MRAM stack, the current is directed from the inside to the outside of the drawing (i.e. Magnetic field in the direction of the other MRAM stack), which has the effect of creating different resistance states, ie opposite resistance states, between the first MRAM 60 and the second MRAM 62. Such devices with bit lines are advantageous by increasing the difference made in the overall resistance state of a pair of MRAMs.

In this embodiment, as shown in FIG. 6, by placing the bit lines 45, a virtual reference line is passed between two MRAMs having substantially opposite directions, that is, between the positions of the first MRAM and the second MRAM. Considered, the bit line 45 passes through the first MRAM 60 in a first direction substantially perpendicular to the reference line and then returns to its original direction, so as to be substantially perpendicular to the reference line but in a first direction. The bit line 45 is configured to pass through the second MRAM 62 in a second direction opposite the direction (with a 180 ° difference). In other words, the bit lines are arranged in such a way that they pass through the first MRAM 60 and then return to their original lines or bend before passing through the second MRAM 62.

Another advantageous feature included in this example is as follows. The word line 43 is disposed between the gate line 44 and the pixel electrode 27. This means that the bit line 45 does not need to pass through the gate line 44. This reduces the amount of overlap capacitance that can be caused by the bit line 45 overlapping the gate line 44.

Further details of the configuration of the in-pixel memory in this embodiment will be described with reference to FIG. 8, which shows a cross-sectional view taken between X and X points shown in FIG. The word line 43 extends along the bottom of the cross section. Dielectric layer 94 resides on word line 43 and insulates word line 43 from MRAM (as described above, this dielectric layer 94 may be formed using a gate dielectric layer). A conductive layer serving as MRAM contact extension 96 is provided over dielectric layer 94. Other dielectric layers 95a, 95b, 95c are provided over and around the MRAM contact extension 96. The MRAM stack 97 of the first MRAM 60 is formed at one end of the MRAM contact extension 96. Bit line 45 is provided over the top of the MRAM stack 97. Contact-via 98 is provided on the other end of MRAM contact extension 96. First flip-flop connection 86 extends toward contact-via 98 along another dielectric layer 95a. Therefore, a connection between flip-flop circuit 64 and MRAM stack 97 is made through contact-via 98 and MRAM contact extension 96. In other embodiments, it will be appreciated that such connections may be formed in any other convenient manner.

The present invention may be implemented using any suitable MRAM stack, for example the simple form described with reference to FIG. However, this embodiment used the preferred MRAM stack design.

9 shows a cross-sectional view of this preferred MRAM stack (not shown to scale). The layers will be described in the order in which they were deposited during the formation of the MRAM stack, which is as shown in FIG. 9. The bottom contact in this embodiment is the MRAM contact extension 96 described above, which extends beyond the edge of the remainder of the MRAM stack to allow for contact as described above. The MRAM contact extension 96 is a roughly 3.5 nm thick Ta layer and serves as a buffer layer for the deposition process and the mechanical characteristics of the MRAM stack.

The next layer is a (conductive) layer 132 comprising a layer of Ni ₈₁ Fe ₁₉ approximately 2 nm thick. The next layer is a bias-biasing layer 134 comprising a layer of approximately 20 nm thick Pt ₅₀ Mn ₅₀ .

The next layer is the pinned layer 106 (using the same reference numerals as in FIG. 3), ie a magnetic electrode. The pinned layer 106 is composed of three layers here: a first Co ₉₀ Fe ₁₀ layer 136 having a thickness of approximately 3 nm, a Ru layer 138 having a thickness of approximately 0.8 nm, and a thickness of approximately 3 nm. Having a second Co ₉₀ Fe ₁₀ layer 140. The second Co ₉₀ Fe ₁₀ layer 104 has a fixed magnetization orientation 110 as described above in FIG. 3. The first Co ₉₀ Fe ₁₀ layer 136 has a fixed magnetization orientation 141 antiparallel to the fixed magnetization orientation 110 of the second Co ₉₀ Fe ₁₀ layer 104. The use of these two layers instead of one ferromagnetic layer is the use of an artificial antiferromagnetic layer, also called synthetic ferrimagnet in the field of ferromagnetism. Known. Further details regarding the composition can be found in International Application No. WO99 / 58994, which is incorporated herein by reference.

The next layer is the tunneling barrier layer 104 (using the same reference numerals as in FIG. 3), which includes a layer of approximately 0.8 nm thick Al oxide.

The next layer is the free layer 102 (using the same reference numerals as in FIG. 3). This free layer 102 consists of two layers, approximately 4 nm thick Co ₉₀ Fe ₁₀ layers and approximately 10 nm thick Ni ₈₀ Fe _2O layers, with two switchable opposing magnetization orientations indicated by double arrows. Shown by 112 (using the same reference numeral as in FIG. 3).

The next layer comprises a Ta layer approximately 10 nm thick as the protective (conductive) layer 146.

As described above, the top contact is provided by bit line 45.

10 and 11 show simulation results performed on the in-pixel memory circuit described with reference to FIG. 4. 10 shows the result of one of the states of the two MRAMs 60 and 62. 11 shows the result of the other of the states of the two MRAMs 60 and 62. In both FIGS. 10 and 11, x-axis 162 is time in microseconds, y-axis 160 is voltage in volts, and plot 164 is the first output terminal of flip-flop circuit 64 ( D), plot 166 shows second (complementary) output stage of flip-flop circuit 64 ( The plot 168 represents the voltage across the first MRAM 60, and the plot 170 represents the voltage across the second MRAM 62. When the average resistance of two MRAMs is 50W, the difference between the resistances of the two MRAMs is 24% (that is, one pair has a resistance 12% higher than the average, and the other pair has a resistance 12% lower than the average). . Simulation results indicate that the voltage across the MRAM is less than 0.57V, which is good enough because it is below the breakdown voltage level of the tunneling junction, which is typically approximately 1V. The threshold voltage value of the TFTs 66 to 69 used in the simulation is approximately 1 V, which represents a lower threshold voltage device than that used in production. Plot (164) of D and Plot 166 may successfully provide a separate logic output that can drive an active matrix display device.

The above-described embodiment includes a combination of a number of advantageous features. However, in other embodiments most of them may be implemented alone or in any two or more combinations, for example in the following cases.

In other embodiments, the circuit arrangement described with reference to FIGS. 2 and / or 3 and / or 5 is used in any suitable structural arrangement using any suitable deposition process other than that described above. Another possibility is that the MRAM and flip-flop devices are as described above, but have any suitable drive circuit that differs from the drive circuit described above, such that no current delivered through the MRAM is used to charge the pixel electrode. Similarly, other flip-flop circuit designs or other read circuits that do not use flip-flop circuits, and / or MRAM stack designs, and / or pixel electrode detail structures, and / or switching component detail structures, and / or The drive line detailed structure and the like can be used in place of the above-described configuration.

In another embodiment, flip-flop circuits can be used to create different resistance states of a single MRAM that function as in-pixel memory.

In another embodiment, two or more MRAMs may be provided for each pixel and aligned in an appropriate manner to provide, for example, increased read performance. For example, if four MRAMs are provided for each pixel, the bit lines can be configured to pass two MRAMs in one direction and two other MRAMs in the opposite direction.

In another embodiment, increased read performance may be provided by providing two (two or more) MRAMs in a single pixel and using any suitable read device other than a flip-flop circuit. In particular, two (two or more) MRAMs can be configured such that the write current passing in these MRAMs in the opposite direction directly provides different resistance states.

In another embodiment, two (two or more) MRAMs are configured such that write currents passing in these MRAMs in opposite directions directly provide different resistance states, and any device that causes write currents to pass in opposite directions. It may be implemented in a suitable manner, ie without necessarily using the above-described bit line pattern or concept.

In another embodiment, during the deposition process, the word line is provided at the same stage as the gate line in any suitable in-memory pixel design.

In another embodiment, during the deposition process, the bit line is provided at the same stage as the column line in any suitable in-memory pixel design.

In other embodiments, in any suitable in-memory pixel design, the bit line is located between the pixel electrode and the gate line, so that the bit line does not pass through the gate line.

In other embodiments, the possibilities described above may apply to other types of active matrices.

In other embodiments, the possibilities described above apply to devices that use other types of liquid crystals or any other suitable display device type, including, for example, plasma, polymer light emitting diodes, organic light emitting diodes, and electroluminescent display devices. Can be.

In other embodiments, memory structures or circuits including two or more MRAMs and one flip-flop circuit may be used in applications other than display devices. For example, this memory structure or circuit can be used for sensors such as medical sensors, for example.

Claims (7)

Pixel and in-pixel memory for display devices, The pixel display electrode 27, One or more magnetoresistive random access memories (MRAMs) 60, 62 for storing drive settings, A read circuit 64 connected to the at least one MRAM 60, 62, A drive connected to the read circuit 64 and the pixel display electrode 27 to drive the pixel display electrode using a drive current that does not pass through the one or more MRAMs according to a read-out drive setting Circuit (26) Pixel and in-pixel memory comprising. The method of claim 1, The drive circuit comprises a transistor (79) connected to a voltage reference (58) and configured to control the drive current flow from the drive circuit to the pixel display electrode. The method according to claim 1 or 2, And a switching device 24 configured to switch in accordance with the received display data and a bit line 45 extending from the switching device toward the reference voltage section via one end of each of the one or more MRAMs. Pixel and in-pixel memory. The method according to any one of claims 1 to 3, And the readout circuitry 64 includes a flip-flop circuit. The method of claim 4, wherein The pixel and in-pixel memory comprise two MRAMs, The flip-flop circuit includes two input stages, The two MRAMs are each connected to respective inputs of the flip-flop circuit. A display device comprising a plurality of pixels and in-pixel memory according to any one of claims 1 to 5. The method of claim 6, And a liquid crystal layer driven by the pixel display electrode.