KR20050020375A - Method for attaching solder ball on substrate of semiconductor package and semiconductor package manufactured thereby - Google Patents
Method for attaching solder ball on substrate of semiconductor package and semiconductor package manufactured thereby Download PDFInfo
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- KR20050020375A KR20050020375A KR1020030058275A KR20030058275A KR20050020375A KR 20050020375 A KR20050020375 A KR 20050020375A KR 1020030058275 A KR1020030058275 A KR 1020030058275A KR 20030058275 A KR20030058275 A KR 20030058275A KR 20050020375 A KR20050020375 A KR 20050020375A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 반도체 패키지의 솔더볼 부착방법 및 이에 의해 제조된 반도체 패키지에 관한 것으로, 더욱 자세하게는 솔더볼과 기판간의 접합을 강화하기 위하여 개선된 반도체 패키지의 솔더볼 부착 방법과 이에 의해 제조된 반도체 패키지에 관한 것이다.The present invention relates to a solder ball attaching method of a semiconductor package and a semiconductor package manufactured thereby, and more particularly, to a solder ball attaching method of a semiconductor package and a semiconductor package manufactured thereby to enhance the bonding between the solder ball and the substrate. .
도 1a 내지 도 1c는 각각 종래 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다. 이하에서는 도 1a 내지 도 1c를 참조하여 종래 반도체 패키지의 솔더볼 부착방법을 설명한다. 먼저, 도 1에서 보는 바와 같이, 솔더볼 랜드(2)가 마련된 기판(1)에 소정 패턴을 가진 솔더 마스크(3)를 도포한다. 다음으로, 솔더볼 랜드(2) 상에 플럭스(4)를 도포한다. 다음으로, 리플로우(reflow)를 통하여 솔더볼(5)을 기판(1) 위에 솔더 조인트(solder joint)시켜 솔더볼 부착 공정을 종료한다.1A to 1C are cross-sectional views illustrating a method for attaching solder balls to a conventional semiconductor package, respectively. Hereinafter, a solder ball attaching method of a conventional semiconductor package will be described with reference to FIGS. 1A to 1C. First, as shown in FIG. 1, the solder mask 3 having a predetermined pattern is applied to the substrate 1 on which the solder ball lands 2 are provided. Next, the flux 4 is apply | coated on the solder ball land 2. Next, the solder ball 5 is soldered onto the substrate 1 through reflow to terminate the solder ball attaching process.
그러나 종래 반도체 패키지의 솔더볼 부착방법에 따르면 솔더볼이 단순히 솔더볼 랜드의 평면위에 부착되어 있기 때문에 그 반도체 패키지가 마더보드에 실장된 후 그 반도체 패키지에 진동·충격 또는 열응력이 가해지는 경우 솔더볼 랜드에서 솔더볼이 쉽게 떨어지게 되는 솔더볼 분리·이탈의 문제점이 있다. However, according to the conventional solder ball attach method of the semiconductor package, since the solder ball is simply attached on the plane of the solder ball land, when the semiconductor package is mounted on the motherboard and the vibration, impact or thermal stress is applied to the semiconductor package, the solder ball in the solder ball land There is a problem of separation and separation of the solder ball is easily dropped.
따라서 본 발명은 솔더볼 부착 강도가 향상된 반도체 패키지의 솔더볼 부착방법 및 이에 의해 제조된 반도체 패키지를 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a solder ball attaching method of a semiconductor package having improved solder ball attaching strength and a semiconductor package manufactured thereby.
본 발명에 따른 반도체 패키지의 솔더볼 부착방법은, (가) 소정의 패턴을 가진 솔더 마스크에 의해 노출된 솔더볼 랜드가 마련되어진 기판을 준비하는 단계; (나) 와이어 본딩 방법으로 형성된 골드 볼을 그 솔더볼 랜드 상에 부착시키는 단계; (다) 그 골드 볼과 연결된 골드 와이어를 절단하여, 복수의 볼 범프를 그 솔더볼 랜드 상에 형성하는 단계; (라) 그 볼 범프가 형성된 그 솔더볼 랜드 상에 플럭스를 도포하는 단계; 및 (마) 그 솔더볼 랜드 상에 리플로우(re-flow) 방식으로 솔더볼을 융착하는 단계;를 포함하는 것을 특징으로 한다. Method for attaching a solder ball of a semiconductor package according to the present invention, (A) preparing a substrate provided with a solder ball land exposed by a solder mask having a predetermined pattern; (B) attaching a gold ball formed by a wire bonding method onto the solder ball lands; (C) cutting the gold wire connected with the gold ball to form a plurality of ball bumps on the solder ball lands; (D) applying flux onto the solder ball lands on which the ball bumps are formed; And (e) fusion bonding the solder balls on the solder ball lands in a reflow manner.
본 발명에 따른 반도체 패키지의 다른 솔더볼 부착방법은, (a) 소정의 패턴을 가진 솔더 마스크에 의해 노출된 솔더볼 랜드가 마련되어진 기판을 준비하는 단계; (b) 와이어 본딩 방법으로 캐필러리 하단부에 형성된 골드 볼을 그 솔더볼 랜드 상에 부착시키는 단계; (c) 그 캐필러리를 이동시켜 웨지 본딩(wedge bonding) 방식으로 골드 와이어의 일단을 그 솔더볼 랜드 상에 부착하는 단계; (d) 전술한 (c)단계에서 형성된 그 골드 와이어의 루프(loop), 그 골드 볼 및 그 솔더볼 랜드에 플럭스를 도포하는 단계; 및 (e) 그 솔더볼 랜드 상에 리플로우(re-flow) 방식으로 솔더볼을 융착하는 단계;를 포함하는 것을 특징으로 한다. Another solder ball attaching method of a semiconductor package according to the present invention comprises the steps of: (a) preparing a substrate provided with a solder ball land exposed by a solder mask having a predetermined pattern; (b) attaching a gold ball formed at the lower end of the capillary by a wire bonding method on the solder ball land; (c) moving the capillary to attach one end of the gold wire to the solder ball land by wedge bonding; (d) applying flux to the loop of the gold wire, the gold ball and the solder ball land formed in step (c) described above; And (e) fusion bonding the solder balls on the solder ball lands in a reflow manner.
본 발명에 따른 반도체 패키지는, 반도체칩; 그 반도체칩을 다이 어태치(die attach)하며, 소정의 패턴을 가진 솔더 마스크에 의해 노출된 솔더볼 랜드가 마련되어진 기판; 및 그 기판에 부착된 솔더볼을 포함하는 반도체 패키지에 있어서, 와이어 본딩 방식으로 형성된 골드 볼이 골드 와이어와 분리된 볼 범프가 그 솔더볼 랜드 상에 하나 이상 형성되고, 그 볼 범프는 그 솔더볼에 내장되는 것을 특징으로 한다. A semiconductor package according to the present invention includes a semiconductor chip; A substrate on which die attach the semiconductor chip and provided with solder ball lands exposed by a solder mask having a predetermined pattern; And a solder ball attached to the substrate, wherein at least one ball bump in which the gold ball formed by wire bonding is separated from the gold wire is formed on the solder ball land, and the ball bump is embedded in the solder ball. It is characterized by.
본 발명에 따른 다른 반도체 패키지는, 반도체칩; 그 반도체칩을 다이 어태치하며, 소정의 패턴을 가진 솔더 마스크에 의해 노출된 솔더볼 랜드가 마련되어진 기판; 및 그 기판에 부착된 솔더볼을 포함하는 반도체 패키지에 있어서, 와이어 본딩 방식으로 형성되고 골드 와이어와 연결된 골드 볼이 그 솔더볼 랜드 상에 하나 이상 부착되고, 그 골드 와이어의 일단이 그 골드 볼과 연결되며 그 골드 와이어의 타단이 그 솔더볼 랜드에 웨지 방식으로 부착되어 형성된 와이어 루프가 그 솔더볼 랜드 상에 하나 이상 형성되며, 그 와이어 루프는 그 솔더볼에 내장되는 것을 특징으로 한다. Another semiconductor package according to the present invention, a semiconductor chip; A substrate on which a die attach is attached to the semiconductor chip and provided with a solder ball land exposed by a solder mask having a predetermined pattern; And a solder ball attached to the substrate, wherein at least one gold ball formed by wire bonding and connected to the gold wire is attached to the solder ball land, and one end of the gold wire is connected to the gold ball. One or more wire loops formed by attaching the other end of the gold wire to the solder ball lands in a wedge manner are formed on the solder ball lands, and the wire loops are embedded in the solder balls.
이하 첨부된 도면을 참고하여 본 발명에 따른 반도체 패키지의 솔더볼 부착방법을 자세하게 설명한다. Hereinafter, a solder ball attaching method of a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 각각 본 발명의 일실시예에 따른 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다. 도 2a 내지 도 2e를 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 솔더볼 부착방법을 설명한다.2A through 2E are cross-sectional views illustrating a solder ball attaching method of a semiconductor package according to an exemplary embodiment of the present invention, respectively. A solder ball attaching method of a semiconductor package according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A through 2E.
먼저, 도 2a에서 도시된 바와 같이, 소정의 패턴을 가진 솔더 마스크(13)에 의해 노출된 솔더볼 랜드(12)가 마련되어진 기판(11)을 준비한다. First, as shown in FIG. 2A, a substrate 11 having a solder ball land 12 exposed by a solder mask 13 having a predetermined pattern is prepared.
다음으로, 도 2b에서 도시된 바와 같이, 와이어 본딩 방법으로 형성된 골드 볼(22)을 솔더볼 랜드(12) 상에 부착시킨다. 와이어 본딩 공정시 사용되는 캐필러리(31) 내에 골드 와이어(21)가 내장되고, 캐필러리(31) 하단부에 골드 와이어(21)가 용융되어 형성된 골드 볼(22)이 솔더볼 랜드(12) 상에 부착된다. Next, as shown in FIG. 2B, the gold balls 22 formed by the wire bonding method are attached onto the solder ball lands 12. The gold ball 21 is formed in the capillary 31 used in the wire bonding process, and the gold ball 22 formed by melting the gold wire 21 at the lower end of the capillary 31 is the solder ball land 12. Attached to the top.
다음으로, 도 2c에서 도시된 바와 같이, 솔더볼 랜드(12) 상에 부착된 골드 볼(22a)과 연결된 골드 와이어(21)를 절단하여, 볼 범프(도 2d의 22b)를 솔더볼 랜드(12) 상에 형성한다. 와이어 커터(32)를 화살표 방향으로 이동시켜 골드 와이어(21)를 절단한다.Next, as shown in FIG. 2C, the gold wires 21 connected to the gold balls 22a attached to the solder ball lands 12 are cut to cut the ball bumps 22b of FIG. 2D into the solder ball lands 12. Form on the phase. The wire cutter 32 is moved in the direction of the arrow to cut the gold wire 21.
다음으로, 도 2d에서 도시된 바와 같이, 볼 범프(22b)가 형성된 솔더볼 랜드(12) 상에 플럭스(14)를 도포한다.Next, as shown in FIG. 2D, the flux 14 is applied onto the solder ball lands 12 on which the ball bumps 22b are formed.
다음으로, 도 2e에서 도시된 바와 같이, 솔더볼 랜드(12) 상에 리플로우(re-flow) 방식으로 솔더볼(15)을 융착하여 솔더볼 부착 공정을 종료한다. 여기서, 솔더볼 융착은 아이알 리플로우 (IR re-flow)방식으로 수행된다.Next, as shown in FIG. 2E, the solder ball 15 is fused on the solder ball land 12 in a reflow method to terminate the solder ball attaching process. Here, solder ball fusion is performed by IR reflow method.
도 3a 내지 도 3d는 각각 본 발명의 다른 실시예에 따른 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다. 도 2a, 그리고 도 3a 내지 도 3d를 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 솔더볼 부착방법을 설명한다.3A to 3D are cross-sectional views illustrating a method for attaching solder balls to a semiconductor package according to another exemplary embodiment of the present invention, respectively. A method of attaching solder balls to a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 2A and 3A to 3D.
먼저, 전술한 실시예와 마찬가지로, 도 2a에서 도시된 바와 같이, 소정의 패턴을 가진 솔더 마스크(13)에 의해 노출된 솔더볼 랜드(12)가 마련되어진 기판(11)을 준비한다. First, as in the above-described embodiment, as shown in FIG. 2A, the substrate 11 having the solder ball lands 12 exposed by the solder mask 13 having a predetermined pattern is prepared.
다음으로, 도 3a에 도시된 바와 같이, 와이어 본딩 방법으로 캐필러리 하단부에 형성된 골드 볼(도 2b의 22)을 솔더볼 랜드(12) 상에 부착하여, 솔더볼 랜드(12) 상에 부착된 골드 볼(22a)을 형성한다. 와이어 본딩 공정시 사용되는 캐필러리(31) 내에 골드 와이어(21)가 내장되고, 캐필러리(31) 하단부에 골드 와이어(21)가 용융되어 형성된 골드 볼(도 2b의 22)이 솔더볼 랜드(12) 상에 볼 본딩(ball bonding) 방식으로 부착된다. Next, as illustrated in FIG. 3A, gold balls (22 of FIG. 2B) formed on the lower end of the capillary are attached to the solder ball lands 12 by the wire bonding method, and the gold is deposited on the solder ball lands 12. The ball 22a is formed. The gold ball 21 is embedded in the capillary 31 used in the wire bonding process, and the gold ball (22 in FIG. 2B) formed by melting the gold wire 21 at the lower end of the capillary 31 is solder ball land. (12) is attached by a ball bonding (ball bonding) method.
다음으로, 도 3b에 도시된 바와 같이, 캐필러리(31)를 이동시켜 웨지 본딩(wedge bonding) 방식으로 골드 와이어(21)의 일단을 솔더볼 랜드(12) 상에 부착한다. 이 때, 솔더볼 랜드(12) 상에는 와이어 루프(loop)(21a)가 형성된다.Next, as shown in FIG. 3B, the capillary 31 is moved to attach one end of the gold wire 21 to the solder ball land 12 by wedge bonding. At this time, a wire loop 21a is formed on the solder ball land 12.
다음으로, 도 3c에 도시된 바와 같이, 전술한 단계에서 형성된 골드 와이어의 루프(21a), 골드 볼(22a) 및 솔더볼 랜드(12)에 플럭스(14)를 도포한다. Next, as shown in Figure 3c, the flux 14 is applied to the loop 21a, the gold ball 22a and the solder ball land 12 of the gold wire formed in the above-described step.
다음으로, 도 3d에 도시된 바와 같이, 솔더볼 랜드(12) 상에 리플로우(re-flow) 방식으로 솔더볼(15)을 융착하여 솔더볼 부착 공정을 종료한다. 여기서, 솔더볼 융착은 아이알 리플로우 (IR re-flow)방식으로 수행된다.Next, as illustrated in FIG. 3D, the solder ball 15 is fused on the solder ball land 12 in a reflow method to terminate the solder ball attaching process. Here, solder ball fusion is performed by IR reflow method.
도 4는 본 발명의 일실시예에 따른 반도체 패키지를 나타낸 단면도이다. 도 4에 도시된 바와 같이, 반도체 패키지는 반도체칩(41), 반도체칩(41)을 다이 어태치(die attach)하며, 소정의 패턴을 가진 솔더 마스크(13)에 의해 노출된 솔더볼 랜드(12)가 마련되어진 기판(11) 및 기판(11)에 부착된 솔더볼(15)을 포함한다. 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. As shown in FIG. 4, the semiconductor package die attaches the semiconductor chip 41 and the semiconductor chip 41, and exposes the solder ball lands 12 exposed by the solder mask 13 having a predetermined pattern. ) Is provided with a substrate 11 and a solder ball 15 attached to the substrate (11).
여기서, 와이어 본딩 방식으로 형성된 골드 볼(미도시)이 골드 와이어(미도시)와 분리된 볼 범프(22b)가 솔더볼 랜드(12) 상에 형성된다. 볼 범프(22b)는 솔더볼(15)내에 내장되며, 그 개수는 솔더볼 랜드(12) 상에 3~5개가 되도록 하는 것이 바람직하다. 솔더볼(15)은 마더보드(mother board)(51)와도 접합된다. Here, a ball bump 22b in which a gold ball (not shown) formed by a wire bonding method is separated from a gold wire (not shown) is formed on the solder ball land 12. The ball bumps 22b are embedded in the solder balls 15, and the number of the ball bumps 22b is preferably 3 to 5 on the solder ball lands 12. The solder ball 15 is also bonded to the motherboard (mother board) (51).
도 5는 본 발명의 다른 실시예에 따른 반도체 패키지를 나타낸 단면도이다. 도 5에 도시된 바와 같이, 반도체 패키지는 반도체칩(41), 반도체칩(41)을 다이 어태치하며, 소정의 패턴을 가진 솔더 마스크(13)에 의해 노출된 솔더볼 랜드(12)가 마련되어진 기판(11) 및 기판(11)에 부착된 솔더볼(15)을 포함한다. 5 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention. As shown in FIG. 5, the semiconductor package die-attaches the semiconductor chip 41 and the semiconductor chip 41, and the solder ball land 12 exposed by the solder mask 13 having a predetermined pattern is provided. And a solder ball 15 attached to the substrate 11 and the substrate 11.
여기서, 와이어 본딩 방식으로 형성되어 솔더볼 랜드(12) 상에 골드 볼(22a)이 부착되고, 와이어 루프(21a)가 솔더볼 랜드(12) 상에 형성된다. 와이어 루프(21a)의 일단은 골드 볼(22a)과 연결되며, 그 타단은 웨지 본딩(wedge bonding) 방식으로 솔더볼 랜드(12) 상에 부착된다. 한편, 와이어 루프(21a)는 솔더볼(15)내에 내장되며, 와이어 루프(21a)의 개수는 솔더볼 랜드(12) 상에 둘 이상이 될 수도 있다. 솔더볼(15)은 마더보드(51)와도 접합된다. Here, the gold ball 22a is formed on the solder ball land 12 by a wire bonding method, and the wire loop 21a is formed on the solder ball land 12. One end of the wire loop 21a is connected to the gold ball 22a, and the other end thereof is attached to the solder ball land 12 by wedge bonding. Meanwhile, the wire loops 21a are embedded in the solder balls 15, and the number of the wire loops 21a may be two or more on the solder ball lands 12. The solder ball 15 is also bonded to the motherboard 51.
이에 따라, 반도체 패키지에 도 4 및 도 5에서와 같이 x축 및/또는 y축으로 외부힘이나 내부 열응력이 작용되는 경우에도 반도체 패키지가 마더보드 상에 견고히 부착될 수 있다.Accordingly, even when an external force or an internal thermal stress is applied to the semiconductor package in the x-axis and / or y-axis as shown in FIGS. 4 and 5, the semiconductor package may be firmly attached to the motherboard.
이상, 본 발명의 원리를 예시하기 위한 바람직한 실시예에 대하여 도시하고 설명하였으나, 본 발명은 그와 같이 도시되고 설명된 그대로의 구성 및 작용으로 한정되는 것이 아니다. 오히려, 첨부된 특허청구범위의 사상 및 범주를 일탈함이 없이 본 발명에 대한 다양한 변경 및 수정이 가능함을 당업자들은 잘 이해할 수 있을 것이다. 따라서, 그러한 모든 적절한 변경과 수정 및 균등물들도 본 발명의 범위에 속하는 것으로 간주되어야 할 것이다. As mentioned above, although the preferred embodiment for illustrating the principle of this invention was shown and demonstrated, this invention is not limited to the structure and operation as it was shown and described. Rather, those skilled in the art will appreciate that various changes and modifications can be made to the present invention without departing from the spirit and scope of the appended claims. Accordingly, all such suitable changes, modifications, and equivalents should be considered to be within the scope of the present invention.
본 발명에 따른 솔더볼 부착방법에 의해 제조된 반도체 패키지는, 와이어 본딩 방식을 이용하여 형성된 볼 범프 또는 와이어 루프가 내장된 솔더볼이 솔더볼 랜드에 융착되어, 볼 범프 또는 와이어 루프가 솔더볼 랜드에 대한 솔더볼의 걸림편 역할을 하므로, 기판에서 솔더볼의 탈락이 억제되어 반도체 패키지의 기계적·열적 신뢰성이 향상되는 이점이 있다. In the semiconductor package manufactured by the solder ball attaching method according to the present invention, a solder ball embedded with a ball bump or a wire loop formed by using a wire bonding method is fused to the solder ball land, so that the ball bump or wire loop is connected to the solder ball land. Since it acts as a locking piece, the fall of the solder ball from the substrate is suppressed, there is an advantage that the mechanical and thermal reliability of the semiconductor package is improved.
도 1a 내지 도 1c는 각각 종래 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다. 1A to 1C are cross-sectional views illustrating a method for attaching solder balls to a conventional semiconductor package, respectively.
도 2a 내지 도 2e는 각각 본 발명의 일실시예에 따른 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다. 2A through 2E are cross-sectional views illustrating a solder ball attaching method of a semiconductor package according to an exemplary embodiment of the present invention, respectively.
도 3a 내지 도 3d는 각각 본 발명의 다른 실시예에 따른 반도체 패키지의 솔더볼 부착방법을 나타낸 단면도이다.3A to 3D are cross-sectional views illustrating a method for attaching solder balls to a semiconductor package according to another exemplary embodiment of the present invention, respectively.
도 4는 본 발명의 일실시예에 따른 반도체 패키지를 나타낸 단면도이다. 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 반도체 패키지를 나타낸 단면도이다. 5 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11: 기판 2, 12: 솔더볼 랜드1, 11: substrate 2, 12: solder ball land
3, 13: 솔더 마스크 4, 14: 플럭스3, 13: solder mask 4, 14: flux
5, 15: 솔더볼 21: 골드 와이어5, 15: solder ball 21: gold wire
21a: 와이어 루프 22, 22a: 골드 볼21a: wire loop 22, 22a: gold ball
22b: 볼 범프 31: 캐필러리22b: ball bump 31: capillary
32: 와이어 커터32: wire cutter
Claims (4)
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| KR1020030058275A KR20050020375A (en) | 2003-08-22 | 2003-08-22 | Method for attaching solder ball on substrate of semiconductor package and semiconductor package manufactured thereby |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020030058275A KR20050020375A (en) | 2003-08-22 | 2003-08-22 | Method for attaching solder ball on substrate of semiconductor package and semiconductor package manufactured thereby |
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| Publication Number | Publication Date |
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| KR20050020375A true KR20050020375A (en) | 2005-03-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11488928B2 (en) | 2020-02-07 | 2022-11-01 | Samsung Electronics Co., Ltd. | Ball disposition system, method of disposing a ball on a substrate and method of manufacturing semiconductor device |
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2003
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11488928B2 (en) | 2020-02-07 | 2022-11-01 | Samsung Electronics Co., Ltd. | Ball disposition system, method of disposing a ball on a substrate and method of manufacturing semiconductor device |
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