KR20050018658A - Focus voltage amplifier - Google Patents

Abstract

A dynamic focus amplifier that generates a dynamic focus voltage for a focus electrode of a cathode ray tube at a capacitive load includes a periodic signal source of a horizontal deflection frequency. The pull-down transistor is responsive to the periodic signal and is connected to the capacitive load and generates, according to the periodic signal, a first portion of the dynamic focus voltage that decreases during the first portion of the period of the periodic signal. A storage capacitor is connected to the capacitive load and supplements the charge stored in the storage capacitor from the charge stored in the capacitive load to generate a control voltage at the storage capacitor. Pull-up transistors respond to the control voltage, are connected to the high voltage source and the capacitive load, and generate current from the high voltage connected to the capacitive load. The current generates a second portion of the dynamic focus voltage that decreases during the second portion of the period of the periodic signal and stores the charge in the capacitive load.

Description

Focus voltage amplifier

This application claims the priority date of US Provisional Application No. 60 / 374,280, filed April 19, 2002.

The present invention relates to voltage reduction in relation to focus tracking in the presence of powering of kinescopes, in particular ultor voltage variation.

Video displays, such as those used for television viewing and computer operation, often use kinescopes, picture tubes or cathode ray tubes (CRTs) as the display device. The CRT is a vacuum tube with a phosphorescent display screen and control terminals for delivering an electron beam focused towards the screen to produce the desired image. In general, CRTs have a relatively high anode or “ulter” voltage that accelerates the electron beam towards the screen, a cathode and grid that modulates the intensity of the electron beam according to the image to be generated, and the electron beam is focused on the screen. This requires a focus electrode to which the focus voltage is applied. Moreover, the CRT is associated with a deflection structure that deflects the electron beam vertically and horizontally. The ultor or anode voltage of the CRT is often adjusted to reduce voltage variations due to the beam current required to generate the image or the interaction between the variable cathode and the internal impedance of the ultor voltage source. A "static" focus voltage is applied to the focus terminal of the CRT to focus the electron beam at a given location, such as the center of the screen. It will be appreciated that the "static" focus voltage is preferably a fixed ratio of the ultor voltage. Dynamic focus control adjusts the value of the focus voltage applied to the CRT according to the position of the electron beam to maintain the electron beam focused on the screen despite the length of change in the electron beam path due to deflection. Is often provided.

In a conventional structure, the focus amplifier includes a pull-up transistor and a pull-down transistor. The pull-down transistor supplies an amplified input signal to a capacitive load comprising a focus electrode capacitance in response to an input signal at a frequency associated with a deflection frequency. The high voltage source generates a high voltage at the collector of the pull-up transistor. The emitter of the pull-up transistor is connected to a capacitive load. It is desirable to generate the base voltage of the pull-up transistor in a manner that reduces power consumption from the high voltage source.

In practicing the features of the present invention, the base voltage of the pull-up transistor is generated in the storage capacitor from the charge stored in the capacitive load. The transfer of charge from the capacitive load to the storage capacitor does not add any significant voltage to the drive circuit that generates the base voltage of the pull-up transistor. Thus, power loss is reduced.

1A and 1B illustrate a dynamic focus amplifier in accordance with aspects of the present invention.

2 is a simplified equivalent view of an apparatus in which three CRTs are used.

Dynamic focus amplifiers that generate a focus voltage for a focus electrode of a cathode ray tube include a high voltage source and a pull-up transistor in response to a control voltage. The pull-up transistor is connected to a capacitive load and a high voltage source that generate a first dynamic focus voltage component of the focus voltage at the capacitive load. The amplifier further includes a source and a storage capacitor of the periodic dynamic focus input signal at a frequency associated with the deflection frequency. The pull-down transistor is connected to the capacitive load to amplify an input voltage that generates a second dynamic focus voltage component in the capacitive load. The capacitive load is connected to the pull-up transistor to generate a control voltage of the pull-up transistor from the charge stored in the capacitive load.

In FIG. 1A, a television device, generally indicated at 10, has a cathode ray tube (CRT) or kinescope 12, an ultor or high voltage (anode) terminal 12U, a focus terminal (at the bottom right) that includes a screen 12s. 12F) and cathode 12C. The cathode 12C of the CRT 12 is described as connected to the source of the image signal in the form of a video source 14. As discussed in FIG. 1A, the CRT 12 may be one of three similar CRTs that may be used, for example, in a projection television arrangement.

The ultor or high voltage terminal 12u of the CRT 12 of FIG. 1A is connected to the ultor or high voltage and focus voltage source described as block 49 through a conductor 9. Block 49 is described in more detail in FIG. 1B. In FIG. 1B, elements corresponding to the elements of FIG. 1A are denoted by like reference numerals. The structure 49 of FIG. 1B is connected to a horizontal output transistor described as one end connected to the source of the regulated voltage B + and block 218 which is part of the deflection block 18 at the upper left of FIG. 1A. An integrated voltage / focus voltage transformer / rectifier arrangement 50 including a primary winding 50p with the other end is included. The transformer 50 of FIG. 1B includes a distribution secondary winding consisting of a rectifier or diode 52 and secondary sections 50 disposed between each pair of secondary sections. The upper secondary windings 50 of the transformer 50 are connected to a high voltage capacitor 9 through which a high voltage is connected to the ultor terminal 12u of FIG. 1A through series coupling of an inductor 50i and an additional rectifier or diode 52 '. ) Is connected. The lowest secondary winding of transformer 50 in Fig. 1B is connected to ground via a series coupling of inductor 50i2 and diode 52 ". A resistor 4R 'is raised secondary over tap 50. The distributed resistance of the windings 52 is shown, and the capacitor C 'connected between the transformer terminal 9 and the tab 50t represents the distributed capacitance of the windings raised above the tab 50t. 2R 'represents the distributed resistance of the inductor 50t2 and the windings 52 raised below the tab 50t of the transformer 50, and the capacitor 2C' represents the distributed capacitance. Tab 50t of 50 is connected via input voltage conductor 11 to input terminal 26i2 of focus control 26 of Fig. 1A. Within focus control 26 of Fig. 1A, transformer 50 The focus voltage from is connected to the focus terminal 12F via the focus control 26 voltage divider 28. The voltage divider 28 is a resistor. Tabs 28t are inserted between the resistors, the tabs 28t are connected to the focus terminal 12F of the CRT 12. The focus control 26 is connected to another focus signal. The input port 26i1 to which it is supplied.

In FIG. 1A, the deflection structure Def1 described as block 16 on the upper left side receives a composite video or at least separated synchronization signals at portion 16i. The deflection structure 16 generates vertical and horizontal deflection signals generated at the output terminal 16o and is supplied to the deflection windings associated with the CRT 12 and described 12W through the path 19 as is known. . The deflection structure 16 includes a deflection processor 18 that is, for example, a Toshiba TA1317N deflection processor. The deflection processor 18 generates horizontal dynamic signals at the output port and vertical dynamic focus signals at the output port 18V.

In general, the dynamic focus coupling circuit and amplifier, indicated at 20 in FIG. 1A, has NPN transistors Q5 along with common emitter resistor R10 and base resistors R504 and R505. , A differential amplifier 22 comprising Q6). Vertical dynamic focus signals from terminal 18V of deflection processor 18 are supplied to first input port 22i1 of deflection amplifier 22 via AC-gain determination register R301 and dc blocking capacitor C301. . The voltage divider comprising resistors R11 and R12 provides bias and additional AC gain control for the input terminal 22i1 of the differential amplifier 22. The retrace parabola is a retrace comprising transistors Q201, Q202, diodes D201, D201, D203, capacitor C201, and resistors R16, R201, R202, R203, R204. The parabola cancellation circuit 24 removes the horizontal dynamic focus signal. Horizontal rate dynamic focus signals are transmitted from an output terminal 18H of the deflection processor 18 to an input port 24i of the retrace parabolic cancellation circuit 24. The retrace parabola circuit includes a retrace parabola removal circuit including transistors Q201 and Q202, diodes D201, D201 and D203, capacitor C201, and resistors R16, R201, R202, R203 and R204. 24) to remove from the horizontal dynamic focus signal.

In FIG. 1A, the retrace parabolic removal circuit 24 provides an output port (i. A series coupling of coupling capacitor C201 and resistor R16 electrically connected between input port 24i and output port 24o to be connected to 24o. Source 24H of horizontal retrace pulses couples a positive pulse to the base of ground emitter (NPN) transistor Q202 through resistor R204. Transistor Q202 is in a non-conductive state during the horizontal trace interval and conducting during the horizontal retrace interval. If transistor Q202 is in a non-conductive state during the horizontal trace interval, PNP transistor Q201 is in a non-conductive state without receiving a base bias. During horizontal retrace, when transistor Q202 is in a conductive state, a voltage divider comprising resistors R202 and R203 supplies a forward bias to the base-emitter junction of transistor Q201, and as a result transistor Q201) is turned on. The emitter current of transistor Q201 flows through the diode D201 to the + V1 supply voltage, whereby the emitter of transistor Q201 is one semiconductor junction voltage drop (VBE) that is lower or negative than the + V1 source voltage. Maintained at voltage. Transistor Q201 achieves a state of small collector-to-emitter voltage drop, whereby the collector and output port 24o of Q201 rise within the VBE of the + V1 source. Thus, the output voltage of the retrace parabolic removal circuit 24 is set to a fixed voltage during the horizontal retrace regardless of the magnitude of the horizontal dynamic focus signal supplied to the input port 24i. Diode D202 and resistor R201 form a voltage divider that provides reference voltage diode voltage drops 2VBE that are lower or negative than the + V voltage source supplied to the anode of D201. Thus, the cathodes of diodes D202 and D203 are 2VBE lower than + V1. Diode D203 together with capacitor C201 clamps the positive portion of the horizontal dynamic focus waveform to the voltage of the emitter of transistor Q201. The voltage drops of diodes D202 and D203 cancel each other and minimize changes in the clamped output signal due to temperature dependent changes in the diodes. Similarly, diode 201 erases the VBE drop of transistor Q401 such that the collector current from Q401 is zero during the positive portion of the waveform at the base of transistor Q401. This clamps to ground the negative portion of the waveform appearing in an inverted form to the resistor R402, which includes the portion removed during the horizontal retrace by the switching transistor Q201. Ground clamping operation maintains a predictable direct current voltage or DC if the horizontal dynamic focus waveform amplitude changes by bus control of a deflection processor (IC) 18.

Horizontal dynamic signals with the retrace parabola removed are generated at the output port 24o of the retrace parabola removal circuit 24 of FIG. 1A. The amplified horizontal dynamic focus signals (retrace parabola removed) are transferred from the collector of transistor Q401 to the differential amplifier 22 through a series-parallel coupling of the AC gain determination register R17 and the capacitors C24 and C401. It is connected capacitively to the second input port 22i2. The differential amplifier 22 generates collector currents from both transistors associated with the combination of vertical and horizontal dynamic focus signals. The collector current of transistor Q6 flows to DC voltage supply V1 without any effect. The current flowing in the collector of Q5 represents properly coupled dynamic focus signals.

“Dynamic Focus Amplifier”, generally indicated in FIG. 1A, includes a differential amplifier 22, a Q protection circuit, Q1 bias detector circuit 32, feedback elements R2, C504, DC current DC, indicated as block 25. FIG. Gain determining resistors R5, R11, R12, vertical gain determining elements R301, R301, R11, R12, horizontal gain determining elements C401, C24, R17, and surge limiting resistors (R503, R25), all of which are discussed below. Terminal 17o is the output portion of dynamic focus amplifier 17.

Transistor Q20 of FIG. 1A is connected in cascode structure with transistor Q5 of differential amplifier 22, and a low value surge protection resistor R506 is inserted between the transistors. Transistor Q20 is a high voltage transistor with low current gain and high voltage gain. The base of the transistor Q20 is connected to the DC voltage source V1 by a surge protection resistor R25, whereby the emitter of the transistor Q20 may not rise above the voltage V1. This structure keeps the voltage of the collector of transistor Q5 constant, so that the voltage of the collector, which can be connected through the collector-to-base "Miller" capacitance to operate as degenerative feedback at high frequencies, is Unchanged, transistor Q5 maintains the optical bandwidth.

Transistors Q1 and Q20 and auxiliary elements of FIG. 1A constitute part of a high voltage dynamic focus signal amplifier 17 that amplifies the combined dynamic focus signals. The load on the dynamic focus signal amplifier 17 is the same as the parallel combination of CT1, capacitors C602, C wire of the CRT (s) driven with the amplified dynamic focus signal. This parallel capacitance is charged through transistor Q1 and discharged through transistor Q20. In FIG. 1A, the collector of NPN transistor Q1 is connected to receive supply voltage V2 through diode D501 and the emitter is connected to the collector of transistor Q20 through resistor R501 and zener diode D4. do. The base of the transistor Q1 is connected to the collector of the transistor Q20 by the conductor 60. The base of the transistor Q1 is connected to the junction of the capacitor C501 and the cathode of the diode D502 via a resistor R502. The other end of capacitor C501 and the anode of zener diode D503 are connected to the junction of resistor R501 with zener diode D4. The anode of the diode D502 and the cathode of the zener diode D503 are connected to the output terminal 17o of the Q1 bias detector 32. Resistor R2 in parallel with capacitor C504 provides modified feedback to input 22i2 of differential amplifier 22 from a position near output terminal 17o.

In operation of the dynamic focus signal amplifier 17 of FIG. 1A embodying the features of the present invention, the collector current of transistor Q5 is coupled to the emitter to collector path of transistor Q5, diode D4, capacitor C501. And via diode D502 to the output 17o of the dynamic focus amplifier 17. As a result of the current flow from output terminal 17o to transistor Q20, capacitor C501 is charged.

In implementing features of the present invention, output terminal 17o provides the charging current of capacitor C501 from the capacitive load formed by capacitor C602, Cwire and CT1 as described above. Charging continues until the zener or breakdown voltage of the zener diode D503 is reached, after which time D503 continues to be constant and equal to the zener voltage across the capacitor C501. A portion of the collector current of Q20 flows through resistor R502. While collector current flows through transistor Q20, transistor Q1 remains OFF or nonconducting because the forward voltage drop across zener diode D4 reverse biases the base-emitter junction of transistor Q1. .

When the collector current flowing through transistor Q20 in FIG. 1A decreases to zero, during part of the operating cycle of dynamic focus signal amplifier 17, transistor Q1 is turned ON, or resistor R502, transistor Q1. The discharge of the capacitor C501 is performed to the capacitor C501 through a base-emitter junction and a resistor R501. The base-emitter junction of transistor Q1 is generated at capacitor C501 from the voltage generated at output terminal 17o of the capacitive load formed by capacitor C602, Cwire and CT1. The transfer of charge from the capacitive load formed by capacitor C602, Cwire and CT1 to storage capacitor C501 does not add any significant power consumption. Thus, advantageously, the power losses associated with the circuit generating the base voltage of transistor Q1 are reduced.

When Q1 is conductive, Q1 current is fed from amplifier V501 through diode D501, the collector to emitter path of transistor Q1, resistor R501, and forward biased diode D503. Tends to flow). The overcurrent damage to transistor Q1 limits the collector current to a value formed by the zener voltage of diode D4 fixed to emitter resistor R501 (one base-emitter junction voltage). This is prevented by the feedback voltage generated at emitter resistor R501. Capacitor C501 stores enough charge to keep Q1 ON during the entire portion of the amplifier cycle in which Q20 is OFF and to keep Q1 ON when the collector-emitter voltage of Q1 is low. This causes the maximum positive amplifier voltage to be close to the voltage of supply V2. Resistor R1 connected between positive V2 supply and output terminal 17o precharges capacitor C501 at start-up so that a cycle AC pumping operation can begin. At start-up, the voltage generated at the resistor R1 is very low and the power consumption at the resistor R1 is advantageously low. Diode D501 interacting with resistor R502 is either a high voltage or via collector to base junction in the event of an internal arc in the CRT 12 between the ultor terminal 12U and the focus terminal 12F. There is a tendency to protect the transistor Q1 from overcurrent.

The amplifier 17 of FIG. 1A may be considered a high voltage operational amplifier at least from the time of the output terminal 17o. In such operational amplifiers, resistor R2 and capacitor C504 provide feedback from the output to the input, and resistors R5, R11, and R12 set the direct current (DC) operating point. Resistor R17 and capacitor C24 set the dynamic or AC gain for the horizontal-rate dynamic focus signals, while resistors R301, R11, and R12 together with capacitor C301 are vertical-rate. rate) Sets the dynamic or AC gain for the dynamic focus signals.

Amplified coupled vertical and horizontal dynamic bias signals generated at the output port 17o of the Q1 bias detector 32 of FIG. 1A can be seen to be generated by a low-impedance source. Signals are supplied from port 17o through a surge limit resistor R503 to the first input port 34i of the beam current load sensing focus tracking circuit 34 (“coupled” circuit 34). The second input port 34i ₁ is connected to the ulter terminal 12U of the water pipe 12 to receive the ultor voltage. The output port 34o of the beam current load sensing focus tracking or coupling circuit 34 is connected to the input port 26i1 of the focus control block 26 and other corresponding focus controls associated with the water tube 12 and other water tubes. Is connected to the field. Cost savings in accordance with one aspect of the present invention are achieved by regulated high voltage sources by causing the high voltage to change in response to beam current. Thus, the high voltage source 49 is not regulated.

As shown in FIG. 1A, resistor R601 is connected in parallel with capacitor C601, and the parallel coupling of R (601) and C (601) has an input port 34i ₁ of coupling circuit 34 at one end. ) Is connected. The other end for parallel coupling of R 610 and C 601 is connected to the output port 34o of the coupling circuit 34. The coupling circuit 34 comprises a series combination of a resistor R602 and a capacitor C602, one end of the series coupling is connected to the second input port 34i ₂ and the other end of the series coupling is the output port 34o. ) Is connected.

The beam current load sensing focus tracking circuit 34 of FIG. 1A combines the high voltage element supplied to the second input port 34i ₂ and the combined vertical and horizontal dynamic focus signals supplied to the first input terminal 34i ₁ . It can be seen as a frequency-sensitive combiner. The resulting combined signals are supplied to an input port 26i1 of the focus control block 26 that couples with the static element of the focus voltage.

The focus control 26 and beam current load sensing focus tracking circuit 34 of FIG. 1A can be made by using the following element values.

R101 50 Megohms R102 80 Megohms R601 5.6 Megohms R602 940 Kilohms C101 1000 picofarads C601 470 picofarads C620 200 picofarads

The stray wiring capacitance is indicated as C _wire , has a value of 10 picofarads, and the capacitance CT1 for the focus electrode of a single image tube, such as the image tube 12, is about 25 picofarads. The output impedance of the Q1 bias detector 32 and the resistance of R 503 are ignored as being very small compared to the other values to influence the result. The series capacitor C602 connected between the output terminal 34o of the coupling circuit 34 and the second input port 34i ₂ has a high voltage variation or change ("sag") connected to the output port 34o. It will be appreciated by those skilled in the art. Similarly, when capacitor C101 is present between input port 26i1 of focus control block 26 and tap 28t of voltage divider 28, the coupling of DC current components to tap 28t is prevented. . Capacitor C101 together with the parallel coupling of resistors R101 and R102 constitutes a high pass filter with a cutoff frequency of about 5 hertz (Hz).

2 is a simplified equivalent circuit or schematic diagram of a television or video display device according to an aspect of the present invention in which red, green and blue cathode or water tubes are used for display. The red, green and blue water tubes are described as blocks 12R, 12G and 12B, respectively, the ultor terminals of the water tubes are identified as 12UR, 12UG, and 12UB, respectively, and the focus terminals of the water tubes are 12FR, 12FG, And 12FB, respectively. In FIG. 2, elements corresponding to those of FIG. 1A are indicated by like reference numerals. Elements R101, R102, RC101 have been appended with letters R, G or B to identify corresponding elements associated with the red, green and blue cathode ray displays, respectively. In FIG. 2, source V_DF represents a combined vertical and horizontal dynamic focus signal source supplied to the first input port 34i of the combiner 34.

Source V_HV in Figure 2 represents a high or ultor supply voltage source. The voltage source V_HV includes an integrated transformer 250 having a primary winding 250p. Primary windings 250p are connected at one end to a regulated source of B + and at the other end to a block representing a switching horizontal output transistor. Transformer 250 includes a distributed secondary winding that includes a plurality of windings, each of which is designated 250s. The distributed secondary winding of transformer 250 has one end grounded. Some diodes in the diode set are inserted between the winding secondary sections 250s and operate to rectify the high voltage generated on the output conductor described as 209. The "static" focus voltage is generated at tap 250t of transformer 250. In one embodiment of the present invention, tap 250t is one third tap with respect to the ultor voltage, such that the static voltage generated at tap 250t is about one third of the high voltage generated at conductor 209 and the ultor Maintain a fixed rate of voltage.

The high or ultor voltage V_HV is connected via a conductor 209 to the terminal 34i2 of the coupling circuit 34 and the ulter connections 12UR of the red, green and blue water tubes 12R, 12G, 12B of FIG. , 12UG, 12UB), whereby the coupler 34 and all cathode ray tubes are commonly provided from the ultor supply V_HV. The static focus voltage is coupled from the tap 250t through the conductor described as 211 to the red, blue and green focus terminals 12FR, 12FG, 12FB by the resistor voltage dividers 126R, 126G, 126B. The voltage divider 126R includes a series resistor R101R with a tab 126Rt inserted therein and a shunt resistor R102R. The tab 126Rt is connected to the red picture tube focus terminal 12FR. Resistor R101R has a value of 50 Megohm and resistor R102R has a value of 80 Megohm. Similarly, voltage divider 126G includes a series resistor R101G and a shunt resistor R102G into which a tab 126Gt is inserted. The tab 126Gt is connected to the green picture tube focus terminal 12FG. Resistor R101G has a value of 50 Megohm and resistor R102G has a value of 80 Megohm. The voltage divider 126B also includes a series resistor R101B and a shunt resistor R102B into which the tab 126B is inserted. The tab 126Bt is connected to the green picture tube focus terminal 12FB. Resistor R101B has a value of 50 Megohm and resistor R102B has a value of 80 Megohm. Thus, each focus terminal 12FR, 12FG, 12FB of the red, green and blue picture tubes sees a static focus voltage as starting from an impedance of about 30 Megohm, as in the configuration of FIG. 1A.

The output terminal 34 for the combiner 34 of FIG. 2 is connected to the respective red, green and blue focus terminals 12FR, 12FG, 12FB by coupling capacitors C101R, C101G, C101B, respectively. Each capacitor C101R, C101G, C101B has a value of 1000 pF. The capacitances of the red, green and blue picture tubes are indicated as CT1R, CT1G and CT1B, respectively.

Claims (11)

In a dynamic focus amplifier for generating a focus voltage for a focus electrode of a cathode ray tube, High voltage source; A pull-up transistor responsive to a control voltage, the pull-up connected to the high voltage source and a capacitive load to generate a first dynamic focus voltage portion of the focus voltage at the capacitive load; (pull-up) transistors; A cyclic dynamic focus input signal source at a frequency associated with a deflection frequency; And A pull-dow transistor responsive to the input signal, the second dynamic focus voltage portion of the focus voltage at the capacitive load connected to the capacitive load to amplify the input signal A pull-down transistor, wherein the capacitive load is connected to the pull-up transistor to generate a control voltage of the pull-up transistor from charge stored in the capacitive load. . The dynamic focus amplifier of claim 1, wherein the pull-down transistor further comprises a storage capacitor connected to the storage capacitor and generating the control voltage at the storage capacitor from charge stored in the capacitive load. . 4. The dynamic focus amplifier of claim 2, wherein the pull-down transistor connects the storage capacitor to the capacitive load to generate the control voltage at the storage capacitor during the first portion of the periodic dynamic focus input signal. . 4. The dynamic focus amplifier of claim 3, further comprising a semiconductor switch to prevent transfer of charge from the storage capacitor to the capacitive load during the second portion of the periodic dynamic focus input signal. 3. The dynamic focus amplifier of claim 2 wherein the storage capacitor is connected between a control terminal and a main current conducting terminal of the pull-up transistor. The dynamic focus amplifier of claim 2, wherein the storage capacitor is charged by a pull-down current flowing through the pull-down transistor from the capacitive load during a portion of the period of the input signal. 3. The dynamic focus amplifier of claim 2, further comprising an impedance connected to the high voltage source and at least the storage capacitor to charge the storage capacitor during the start-up operation. 3. The dynamic focus amplifier of claim 2, further comprising a zener diode connected to the storage capacitor to limit the control voltage. 2. The dynamic focus amplifier of claim 1, wherein the input signal comprises a signal component at a frequency associated with at least one of a horizontal deflection frequency and a vertical deflection frequency. A dynamic focus amplifier for generating a focus voltage for a focus terminal of a cathode ray tube, High voltage source; A pull-up having a first main current conducting terminal connected to the high voltage source and a second main current conducting terminal connected to the capacitive load to generate a first portion of the focus voltage at the capacitive load from the high voltage transistor; Storage capacitors; A cyclic dynamic focus input signal source of frequency associated with the deflection frequency; And A pull having an input control terminal connected to the periodic dynamic focus input signal source and a main current conducting terminal connected to the capacitive load to amplify the input signal to generate a second portion of the focus voltage at the capacitive load A dynamic focus comprising a main current conducting terminal of said pull-down transistor coupled to said storage capacitor for generating a control voltage at said storage capacitor connected to a control terminal of said pull-up transistor; amplifier. 11. The dynamic focus amplifier of claim 10, wherein the input signal comprises a signal component at a frequency associated with at least one of a horizontal deflection frequency and a vertical deflection frequency.