KR20050015144A - Method for aligning coordinates and apparatus for inspection adaptively aligning coordinates - Google Patents

Abstract

PURPOSE: A method for aligning coordinates and an apparatus for adaptive inspection of coordinates alignment are provided to automate defect inspection operation and to reduce inspection time by performing inspection after aligning coordinates using added values of eigenvalue differences. CONSTITUTION: A stage(100) for supporting and transferring a semiconductor substrate. A light emitter(120) is spaced from the stage by a predetermined distance and illuminates light on the semiconductor substrate. A controller(140) defines a plurality of sets by grouping two regions spaced from one region of the semiconductor substrate by the same distance into one set. A calculator(150) defines eigenvalues of respective regions based on the reflective light, calculates eigenvalue difference of each set and adds the eigenvalue differences for reference regions. A determiner(160) adjusts center coordinates of the reference region corresponding to a minimum value of the added result to coincide with predetermined coordinates and determines whether the semiconductor substrate is a defective one according to the coincided coordinates.

Description

Coordinate Alignment Method and Active Coordinate Alignment Inspection Device {METHOD FOR ALIGNING COORDINATES AND APPARATUS FOR INSPECTION ADAPTIVELY ALIGNING COORDINATES}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coordinate alignment method and an active coordinate alignment type inspection apparatus of a semiconductor substrate. It relates to a method and a defect inspection device for matching the coordinates of the wafer.

Current research on semiconductor devices is progressing toward high integration and high performance in order to process more data in a short time. In order to achieve high integration and high performance of a semiconductor device, a thin film deposition technology for accurately forming a thin film pattern on a semiconductor substrate is very important.

Therefore, an inspection process for determining whether the thin film pattern is accurately formed on the semiconductor substrate is essential.

In general, an inspection process acquires an image of a test wafer and overlaps an image of a preset reference wafer. This is used to match the coordinates of the inspection wafer with the coordinates of the inspection apparatus.

A conventional method of coordinate alignment to inspect the wafer for defects is described below with reference to FIG. 1.

1 is a flowchart illustrating a conventional coordinate alignment method.

Referring to FIG. 1, a randomly selected test wafer is loaded into a defect inspection apparatus. After irradiating the laser light to the loaded test wafer (S11), the reflected laser light is collected (S12). An optimal amplification ratio is calculated according to the intensity of the collected reflected light (S13), and the reflected light is amplified according to the amplification ratio (S14). Thereafter, the amplified reflected light is converted into a digital signal (S15), and the digital signal is converted into a test image (S16). The test image is stored in the server (S17), and the image of the preset reference wafer overlaps the test image (S18). Next, the degree to which the center of the test image is eccentric from the center of the reference image is calculated, and the coordinates of the inspection apparatus are matched to the coordinates of the test image (S19). Finally, the signal of the microstructure formed on the test wafer is analyzed to determine whether there is a defect.

In general, a light irradiation method is widely used to analyze a signal of a microstructure formed on a test wafer and to acquire an image of the test wafer.

When the light irradiation method is explained in detail, light is irradiated to a test wafer from the light source which irradiates light like a laser. The light irradiated onto the wafer is reflected at the same angle as the incident angle or scattered by defects on the wafer.

Light reflected from the wafer is collected by the optical multiplier and amplified at a predetermined amplification ratio. In this case, since reflectances are different for each region on the wafer, amplification of the reflected lights at the same amplification ratio may result in poor image information of the test wafer. Therefore, the amplification ratio should be changed according to the intensity of the reflected light collected in the photomultiplier.

As described above, an intermediate process for calculating an optimal amplification value of a plurality of regions formed on the test wafer is required. Therefore, the transient time is required to calculate the optimal amplification value for each region according to the intensity of the reflected light collected by the photomultiplier tube. For example, when light irradiated from a light source moves from a low reflectance region such as a cell on a wafer to a peri or sense amp and a high reflectance region, the controller detects the optimal amplification ratio. It takes time to determine the transition. In this case, the reflected light collected during the transient time is amplified with an inappropriate amplification ratio, and saturation of the test image occurs.

When an infiltration phenomenon occurs in a test image, the coordinates of the inspection apparatus are incorrectly corrected to the coordinates of the inspection wafer, and the detection effect of the entire defect inspection apparatus is lowered.

In addition, in order to capture the test image, the signal output from the optical multiplier needs to be converted into a digital signal, and an intermediate process of converting the digital signal into a Youngsan signal is necessary.

Not only a plurality of microstructures such as a line, a space, a contact hole or a pattern are formed on the wafer, but also the microstructures change slightly for each manufacturing process.

Therefore, in order to determine whether there is a defect on the wafer for each manufacturing process, a problem arises in that all images of the wafer on which each unit process is performed must be acquired. An image of the test wafer must be obtained for each unit process so that the coordinates of the inspection apparatus can be matched to the coordinates of the test wafer.

The inspection device already has a margin of error set for each process based on the reference wafer during the recipe setup. In more detail, the inspection apparatus is set to the tolerance range for the thickness and position of the microstructure formed on the wafer for each process. The signal measured from the test wafer includes information on the thickness and position of the microstructure, and the measured signal may determine whether the microstructure is defective on the test wafer. However, in general, the alignment of the coordinates of the inspection apparatus and the inspection wafer is necessary because the inspection wafer is not loaded correctly on the inspection apparatus.

Once the coordinates of the inspection apparatus and the test wafer are aligned, it may be determined whether the microstructure on the test wafer is defective by a predetermined program.

As described above, after acquiring an image of the subject in order to align the coordinates of the inspected wafer with the coordinates of the inspecting apparatus, many intermediate steps and time are required to overlap the reference image. This inevitably leads to time and financial losses and lowers overall wafer fabrication efficiency.

In order to prevent the conventional time and financial loss, there is a need for an inspection apparatus using a coordinate alignment method and a coordinate alignment method that can accurately and accurately align coordinates of a test wafer and an inspection apparatus.

The present invention has been made to solve the above-described problems of the prior art, the first object of the present invention is to calculate the difference in the characteristic value of a pair of microstructures located at the same distance, based on one region on the semiconductor substrate, By defining the center of the area where the sum of the characteristic values is the lowest as the center on the semiconductor substrate, a coordinate alignment method capable of quickly and accurately aligning the coordinates of the semiconductor substrate and the coordinates of the inspection apparatus.

Further, a second object of the present invention is to provide a defect inspection apparatus capable of accurately and quickly performing a defect on a semiconductor substrate after aligning the coordinates of the semiconductor substrate and the coordinates of the inspection apparatus according to the coordinate alignment method. .

In order to achieve the first object of the present invention described above, according to a preferred embodiment of the present invention, the characteristic value of the reflected light for each region is defined by irradiating light on a test wafer for each region. Then, a plurality of sets are defined by setting two regions located at the same distance with respect to one region on the test wafer as one set. Next, after calculating the difference in the characteristic values of the two regions constituting the set, the sum of all the difference in the characteristic values is defined as the sum of the reference regions. While changing the coordinates of the reference area to calculate the total value for each reference region, and defines the reference region that the minimum value of the plurality of the sum value is calculated as the center of the test wafer. Finally, the coordinate alignment is completed by matching the center of the defined test wafer to the preset coordinates.

In order to achieve the above-mentioned second object of the present invention, an active coordinate-aligned inspection apparatus according to a preferred embodiment of the present invention includes a stage for supporting and transporting a test wafer; A light emitting unit spaced apart from the stage by a predetermined distance to irradiate light onto the subject; A detector configured to collect light reflected from the semiconductor substrate; A control unit connected to the detection unit and defining a plurality of sets by setting two regions located at the same distance with respect to one region of the test wafer as a set, and repeatedly defining the plurality of sets while changing coordinates of the reference region; An operation unit for defining characteristic values for each region according to the reflected light collected by the detector, calculating a difference in the characteristic values of each set for each reference region, and summing the difference in the characteristic values of each set for each reference region; And a discriminating unit for matching the center coordinates of the reference region where the sum value is calculated to the maximum with the center of the preset coordinates, and determining the presence or absence of a defect on the test wafer according to the matched coordinates.

The conventional coordinate alignment method using an image and an inspection apparatus using the same overlap an image obtained by acquiring an image of a wafer for each semiconductor manufacturing process and a preset image. In this case, the overlapping images are used to align the coordinates of the wafer and the inspection device, which is a huge time and financial loss. Therefore, in reality, only a portion of the manufactured wafers were randomly selected and inspected, and then multiplied by a predetermined multiple to estimate the number and ratio of defects. Therefore, the conventional image coordinate alignment method and inspection apparatus using the same yield fundamentally unreliable inspection results, and cause huge loss in time and finance.

In fact, in the deposition process-related facilities, the inspection equipment inspects about 200 to 300 wafers per day, and the wafers inspected daily by defect inspection using about seven inspection equipments in one semiconductor production line It reaches about 1400 ~ 2100 sheets.

Among the wafers that are actually reexamined, when the number of defects is large, only a part of the defects is reexamined.

According to the present invention, the inspection process can be performed quickly by aligning the coordinates of the inspection wafer with the coordinates of the inspection apparatus without acquiring an image of the inspection wafer, and further inspection of more wafers can increase inspection efficiency. Can be.

Hereinafter, a coordinate alignment method and an active coordinate alignment inspection apparatus according to preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited or limited by the following embodiments.

Example 1

2 is a flowchart illustrating a coordinate alignment method according to an embodiment of the present invention.

Referring to FIG. 2, light such as a laser is irradiated on a test wafer for each region (S21). After collecting the light reflected from the test wafer (S23), the region-specific characteristic value of the test wafer is defined from the collected light (S25). Thereafter, a plurality of sets are defined by setting two regions located at the same distance with respect to one region on the test wafer as one set (S25). Next, after calculating all the difference in the characteristic values of the two regions constituting a set (S29), the difference in the characteristic values is summed to define the sum of the one reference region (S31). The sum of the plurality of reference areas is calculated while changing the coordinates of the reference area (S33). Coordinate alignment is completed by defining a reference area for calculating the lowest value among the calculated sum totals as the center of the test wafer and matching the center of the defined test wafer with a preset coordinate (S35).

The light irradiated onto the test wafer is preferably laser light having a wavelength of about 488 nm. In this case, not only laser light of 488 nm wavelength can be used. The light irradiated onto the test wafer is selectively available with light that is easy to determine the thickness or position of the microstructure on the wafer.

It is preferable that the laser light irradiated to the test wafer has an incident angle of about 20 degrees from the horizontal plane of the wafer. The incident angle of the laser light is also not limited to 20 degrees. In some cases, the incident angle may be about 10 to 90 degrees.

The type of light irradiated on the wafer, the number of light, and the angle of incidence of the light are disclosed in many publications relating to the inspection method and the inspection apparatus, and can be easily selected by one of ordinary skill in the art according to the kind and working environment of the subject.

The light irradiated onto the wafer is reflected at the same reflection angle as the incident angle or scattered by the defect. In this case, the presence or absence of a defect in the region to which the light is irradiated can be determined by collecting either the reflected light or the light that is scatteredly reflected at the same angle as the incident angle. In one example, when the microstructures on the wafer are free of defects, the incident light is reflected at almost the same angle. If the microstructure is defective, the incident light is increased to be scatteredly reflected light. That is, when there is a lot of light reflected at the same angle of incidence, it can be predicted that the microstructure is free of defects, and when there is a lot of scattered light, it can be predicted that the microstructure is defective. Therefore, whether the scattered light or the reflected light is the same as the incident angle, it is possible to determine whether the microstructure is defective.

Light reflected from the wafer is collected at various locations (S23). In this case, it is preferable to use a photomultiplier tube. The photomultiplier may collect the reflected light at an angle of 45 degrees to the left and the right based on the incident direction of the laser light.

The collected reflected light includes information on the height, thickness and position of the microstructure formed on the test wafer. In more detail, since the intensity of light reflected from each region and the scattering degree of light are different according to the height, thickness, and position of the microstructures, when the light reflected from each region is analyzed, information such as the height, thickness, and position of the microstructures is analyzed. It can be seen.

The intensity of light reflected from each region on the test wafer and the scattering degree of the light may be represented by a numerical value, which is referred to as a characteristic value for each region. For example, the reflectance of each region may be a characteristic value, and the luminance of light reflected from each region may also be a characteristic value.

The characteristic value is information of reflected light which can easily indicate the state of the microstructure formed on the test wafer, that is, the thickness or size.

When the characteristic values for each region on the test wafer are defined (S25), a plurality of sets are defined by setting two regions located at the same distance from one region on the wafer as one set (S27). In other words, two regions spaced apart by the same distance while getting farther away from one area are defined as a set.

Thereafter, the difference in the characteristic values of the fine structures for each set is calculated (S29), and the calculated characteristic value differences are added up (S31).

After summing all the difference in the characteristic values of one region (S31), change the coordinates of the one region to define a plurality of sets again, calculate the characteristic value difference for every set again, and add all the calculated characteristic value differences (S33).

To change the coordinates of one area is to change the reference area. The reference region selects a range predicted to be the center of the test wafer, and is changed within the selected range. In this case, it is not necessary to select the prediction range, but it is preferable to select a predetermined range in order to quickly define the center of the test wafer.

Next, the center of the reference area from which the lowest value is calculated among the sum values calculated for each area is matched with the preset coordinate center (S35). In this case, the center of the reference region where the lowest value is calculated is the center of the test wafer.

Calculating the center of the test wafer in more detail, a plurality of microstructures are formed on the wafer on which a predetermined semiconductor manufacturing process has been performed. The plurality of microstructures can be roughly divided into a cell region, a peri region, a sense AMP region, a sub-word divider (SWD), and the like. Further, a cell region, a ferry region, an S / A region, and the like are repeatedly formed on the wafer. In this case, the plurality of regions are repeatedly formed while showing a tendency of right and left symmetry. Therefore, almost all wafers are symmetrical left or right about the central axis in the radial direction.

That is, the two regions spaced apart by the same distance from the central axis are almost similar. Therefore, the characteristics of the light reflected from the two regions are almost similar.

The coordinate alignment method according to the present embodiment uses the feature that the characteristic values of two regions located at the same distance from the central axis of the test wafer are similar. One region on the test wafer is defined as a reference axis, a difference in the characteristic values of two regions located at the same distance from the defined reference axis, and the difference in the characteristic values of the reference region are summed up.

Subsequently, the sum of the difference between the characteristic values of each reference region is calculated while changing the reference region. In this case, the reference area is changed on a diameter line perpendicular to the axis of symmetry of the test wafer. Also, the reference area is changed in the range in which the center of the test wafer is expected to be located.

A typical wafer has 644 pixel areas on a diameter line perpendicular to the axis of symmetry. The center of the wafer is located at the 322th pixel region of the 644 pixel regions. Therefore, in consideration of the degree of eccentricity of the test wafer, it is preferable to define the change range of the reference area as 200 to 400 pixel areas.

By calculating the sum of the characteristic value differences while changing the reference area, it is possible to know the reference area from which the lowest sum value is calculated. The reference region from which the lowest total value is calculated becomes the 322th pixel region of the test wafer. That is, it is the center of a test wafer. In more detail, the test wafer is symmetric about an axis of symmetry passing through the 322th pixel region. Therefore, the characteristic values of the two regions located at the same distance from the 322 pixel region are almost the same. Computation of the difference in the characteristic values of the symmetrical regions yields values close to zero. However, when the reference region is a pixel region other than the 322th pixel region, the characteristic values of the two regions located at the same distance from the reference to the other pixel region are different from each other. Therefore, the sum of the characteristic value differences becomes a large value.

The above description is summarized as the following equation.

, (x = 200 to 400, n = 100 to 1)

Where x is the characteristic value of the reference region. That is, after calculating the characteristic value differences of the regions 1 to 100 spaced from the reference region to the left and right, respectively, the sum is added, the reference regions are changed from 200 to 400, and the sum is calculated for each region.

Here, the ranges of x and n can be changed differently. In some cases, the range of x may be defined as 300 to 350, and the value of n may be defined as 50 ~ 1. x and n can be easily changed by those skilled in the art according to the working environment.

Thereafter, when the sum value for each region is calculated, the center coordinates of the region for which the lowest sum value is calculated are calculated. Next, after matching the center coordinates with the center coordinates of the inspection apparatus, the microstructure on the test wafer is inspected.

In the inspection apparatus, the tolerance range of the microstructures formed for each process is already set. Therefore, the inspection apparatus determines whether the microstructures are defective based on the characteristic value of each region. In this case, the image of the test wafer is not used. Since the characteristic values of each region of the test wafer are calculated, the inspection apparatus determines the degree of error of the characteristic values for each coordinate. When the degree of error in one area exceeds the tolerance range, the inspection device determines that a defect exists in the area and displays it.

As described above, the test wafer is generally not positioned at one time of the inspection apparatus. Therefore, the coordinates of the inspection apparatus and the coordinates of the test wafer must be aligned. If the test wafer is inspected in an unaligned state, the inspection apparatus may define an error range for the wrong area and mark it as a defect. In more detail, if there is a tolerance range for each region of the test wafer and the coordinates of the test apparatus and the test wafer are not aligned, the test apparatus inspects the test wafer based on the wrong coordinate. The area is examined based on the error range of the wrong area. Thus, the inspection apparatus can inspect the defect area for defects.

In the conventional inspection method, an image of a test wafer was acquired to match the coordinates of the test wafer and the inspection apparatus. Therefore, it took a predetermined time to acquire the image of the test wafer, and had to acquire the image of the test wafer for each unit process. In addition, the inspection device had to acquire and store an image of the reference wafer for each unit process. Therefore, even if the unit process is slightly changed, there was a disadvantage in that the images of the test wafer and the reference wafer must be acquired again.

Currently, semiconductor manufacturing processes continue to evolve, and the cycle of repeating the same unit processes is not very long. In addition, in view of the fact that about 1400 to 2100 wafers are inspected every day in one inspection apparatus, the conventional inspection method is very inefficient.

However, using the coordinate alignment method according to the present embodiment, there is no need to acquire images of the test wafer and the reference wafer. In addition, there is no need to reset the inspection apparatus even if the unit process is changed. You only need to re-enter the information on the tolerances that have changed for each unit process. This is because the symmetry of the regions on the wafer does not change even if the unit process is different. Therefore, the time required for coordinate alignment can be greatly shortened, and inspection efficiency can also be increased. Furthermore, the yield of the overall semiconductor manufacturing process can be improved, and the manufacturing cost can be reduced.

Example 2

3 is a schematic view for explaining an active coordinate alignment inspection device according to an embodiment of the present invention.

Referring to FIG. 3, the inspection apparatus according to the present embodiment includes a stage 100 on which a wafer W is placed; A light emitting unit 120 for irradiating light onto the wafer W; A detector 130 disposed adjacent to the wafer W and configured to collect light reflected from the wafer W; A control unit connected to the detection unit and defining a plurality of sets by setting two regions located at the same distance with respect to one region on the wafer W as a set, and repeatedly defining the plurality of sets while changing the reference region ( 140); An operation unit 150 for defining characteristic values for each region according to the collected reflected light, calculating a difference in characteristic values of each set for each reference region, and summing all the difference in characteristic values for each set for each reference region; And a determination unit 160 for matching the center coordinates of the reference area from which the lowest sum value is calculated to a predetermined coordinate center, and determining whether there is a defect on the wafer according to the matched coordinates.

The preset coordinates represent the positions of the microstructures formed on the reference wafer. The reference wafer is a wafer serving as an inspection standard, and a wafer in which microstructures are preferably formed.

 The detector 130 includes an optical multiplier 131 for collecting and amplifying the light reflected from the wafer W and a power supply device 132 for applying power for operating the optical multiplier 131.

In addition, the inspection apparatus according to the present exemplary embodiment includes a storage unit 170 connected to both the calculation unit 150 and the determination unit 160, and the storage unit 170 includes a sum value calculated for each predetermined mark and region, and a wafer. The defect determination result of (W) is stored.

The wafer W is supported by the stage 100. The wafer W is moved in the horizontal direction by the stage 100. Therefore, light may be radiated to the entire area on the wafer W by the stage 100.

The light emitting unit 120 irradiates light onto the wafer (W). The light emitter 120 emits light vertically or obliquely from the plane of the wafer W. Preferably, the light emitting portion 120 is disposed to be inclined at an angle of about 20 degrees from the horizontal plane of the wafer W so that light is irradiated at an angle of about 20 degrees from the plane of the wafer W. However, in some cases, the light emitting unit 120 may be inclined at an angle of about 10 to 90 from the horizontal plane of the wafer (W). The inclination of the light emitting unit 120 is selectively adjusted according to the inspection apparatus or the inspection process.

As for the light irradiated to the wafer W from the light emitting part 120, laser light of about 488 nm wavelength is most preferable. In this case, not only laser light of about 488 nm wavelength can be irradiated to the wafer. Other wavelengths of light may be used. However, since the laser of 488 nm wavelength is the most stable, it is the most suitable.

The first polarizing member 121 is disposed between the wafer W and the light emitting unit 120, and the second polarizing member 123 and the light collecting member 125 are sequentially disposed between the wafer W and the detection unit 130. Is placed.

Light generated from the light emitter 120 is converted into polarized light through the first polarizing member 121. The reason for converting the light generated from the light emitting portion 120 into polarized light and irradiating the wafer W is that the defect on the wafer W can be easily determined. In more detail, the reaction of the defect formed on the wafer W differs according to the kind of polarization irradiated on the wafer W. FIG. Therefore, in order to detect defects and to grasp the characteristics of the defects, it is preferable to irradiate polarized light on the wafer (W).

An optical path switching member may be disposed between the light emitting unit 120 and the wafer (W). The optical path switching member includes a plurality of mirrors. The light generated from the light emitter 120 may be irradiated at various angles on the wafer W by a plurality of mirrors. The optical path switching member is not essential and may optionally be used in some cases.

Light converted to polarized light is reflected from the wafer (W). In this case, the polarized light is reflected at the same angle as the angle incident on the wafer W, or scatteredly reflected by a defect in the wafer W plane.

In more detail, the light reflected from the wafer W, more specifically, the reflected light reflected at the same angle as the incident angle and the scattered reflected light may be collected by the detector 130.

Those skilled in the art can easily select whether to collect defects by scattered reflected light or reflected light equal to the incident angle.

The light reflected from the wafer W is collected by the detector 130. The detector 130 includes a photo multi tube 131 for collecting reflected light and amplifying the light at a predetermined amplification ratio, and a power supply device 132 for applying a high voltage for operating the photo multi tube 131.

The photomultiplier 131 is disposed at a position where it is easy to collect the reflected light. In this case, the inclination of the detector 130 with respect to the horizontal plane of the wafer W may be variously adjusted. Preferably, the optical multiplier 131 is disposed at an angle of 45 degrees to the left and right with respect to the incident direction of the polarized light.

The photomultiplier tube 131 is a vacuum tube light receiving device for changing the amplification ratio of the collected light according to the high voltage supplied. In general, the optical multiplier 131 can measure up to one photon and can be used in a wavelength range of 0.2 to 1.1 μm. In addition, the optical multiplier can measure low dark current of 0.3 mA and the amplification ratio can be amplified up to several hundred times. Therefore, the photomultiplier tube 130 is very preferable as an apparatus for measuring the light reflected from the surface of the wafer (W).

A second polarizing member 123 similar to the first polarizing member 121 is disposed between the detector 130 and the wafer W.

The light reflected from the wafer W is filtered by the second polarization member 123 to polarized light of a specific wavelength. The filtered reflected light is also one of P polarized light, S polarized light or C polarized light.

The reason for filtering the reflected light is that by using a specific polarization, it is possible to minimize the regular signal present on the wafer (W), it is possible to obtain the effect that the signal of the defect is increased.

The light collecting member 125 is disposed between the second polarizing member 123 and the light multiplier 131. The polarized light filtered by the second polarizing member 123 is concentrated on the photomultiplier 131 through the light collecting member 125.

The polarized light concentrated in the optical multiplier 131 is amplified according to a predetermined amplification ratio. In this case, the amplification ratio is adjusted by the high voltage supplied to the optical multiplier 131.

The photomultiplier tube 131 includes a cathode that emits photoelectrons when light is irradiated and an anode that collects the emitted electrons. When a potential difference is generated between the anode by supplying power to the cathode and the anode, a photocurrent flows from the cathode to the anode. In this case, the photocurrent is proportional to the number of photoelectrons emitted from the cathode. The number of photoelectrons emitted from the cathode is proportional to the intensity of light reaching the cathode. By measuring the photocurrent, the luminosity can be known.

After each unit process is performed, a plurality of microstructures are formed on the wafer (W). In this case, the microstructure may be poorly formed on the wafer (W).

Light is irradiated correspondingly to the fine structure preferably formed on the wafer W. As shown in FIG. Thus, when the microstructure is preferably formed, the light reflected from the wafer is reflected almost equal to the incident angle. However, when the microstructure is poorly formed, most of the light is scatteredly reflected. That is, when the light reflected from the wafer W is analyzed, information about the microstructure formed on the wafer W, that is, the characteristic value, may be known. The characteristic value is information about the thickness, height and position of the microstructure.

In addition, the characteristic value is symmetric about the center axis of the wafer. Therefore, if the difference between the characteristic values of two zeros located at the same distance with respect to the symmetry axis is obtained, a value close to zero can be obtained.

In the inspection apparatus according to the present embodiment, characteristics of two regions having the same characteristic value are used based on the central axis of the wafer (W).

The light control pipe 131 is connected to the control unit 140. The controller 140 defines a plurality of sets by setting two regions located at the same distance with respect to one region on the wafer W. Thereafter, the controller 140 defines a plurality of sets again based on other regions adjacent to the reference region. In this case, the reference region is preferably selected as the region predicted by the center of the wafer (W).

The calculation unit 150 receives the information on the set for each area from the control unit 140 and stores the information in the storage unit 150. In addition, the information on the reflected light collected by the optical multiplier pipe 130 through the control unit 140 is also stored in the storage unit 150.

The calculator 150 defines the characteristic value for each region of the wafer W using the collected reflected light information. Thereafter, the difference in the characteristic values of each set is calculated for each reference region defined by the calculator 150. In this case, the calculation unit 150 continuously exchanges information with the storage unit 170.

Multiple sets are defined for one reference region, and each set is defined as two regions. The calculation unit 150 calculates a plurality of sets of characteristic value differences defined for each reference region, and then adds all the characteristic value differences. Thereafter, the calculator 150 calculates a sum value for every reference area.

Thereafter, the calculation unit 150 calculates the sum value for each reference area, stores the calculated information in the storage unit 170. The determination unit 160 examines the sum of the areas stored in the storage unit 170 and defines the center coordinates of the area where the minimum sum is calculated.

The process of defining the center coordinates of the above-mentioned wafer W is summarized as in the equation of the first embodiment. The explanation of the equations is also the same.

Thereafter, the determination unit 160 matches the center coordinates of the area where the lowest sum is calculated with the center coordinates of the inspection apparatus. Next, the determination unit 160 performs an inspection process on the microstructure on the wafer W based on the matched coordinates.

 In more detail, when the wafer W is loaded into the inspection apparatus, the coordinates of the inspection apparatus and the wafer W are different. Therefore, the coordinate alignment of the inspection apparatus and the wafer W is necessary. In this case, the determination unit 160 calculates the center coordinates of the wafer W based on the lowest sum value for each region stored in the storage unit 170. When the center coordinates of the wafer W are calculated, the determination unit 160 calculates a difference between the center coordinates of the inspection apparatus and the center coordinates of the wafer. Thereafter, the coordinates of the inspection apparatus are corrected by the calculated difference, and then the presence or absence of a defect on the wafer W is determined. In this case, the memory unit 170 stores the preset error range for each region and each microstructure. Therefore, the determination unit 160 analyzes the characteristic value of the microstructure on the wafer W using the error range stored in the storage unit 170. When the characteristic value of one region on the wafer W exceeds the error range, the inspection apparatus marks the region as having a defect.

The error range stored in the storage unit 170 is previously set in a job profile before the inspection process is performed. The margin of error is preferably defined relative to the reference wafer formed. If the microstructure on the wafer W exceeds a predetermined error range, it may cause fatal damage in subsequent processes. That is a fatal defect.

In the inspection apparatus according to the present embodiment, the storage unit 170 does not necessarily need to exist separately. With the recent development of semiconductors, other memory devices may be included in the control unit, the calculation unit, or the determination unit. Although a large amount of information is not stored, the present invention can be achieved without using a separate storage unit 170. This can be easily selected by those skilled in the art.

As a result of the final inspection, when the number of defects existing per wafer W exceeds a reference value, the wafer is defined as a secondary inspection, that is, a retesting object.

The coordinates of the wafer W can be actively defined without separately acquiring an image of the wafer W, thereby greatly reducing the inspection time required for the wafer W. In addition, the coordinates of the wafer W and the coordinates of the inspection apparatus can be accurately aligned, so that defects on the wafer W can be accurately identified and classified. Furthermore, the time required for unnecessary re-examination can be reduced, thereby preventing time and financial loss.

According to the present invention, by calculating the difference in the characteristic value of a pair of microstructures located at the same distance on the basis of one region on the wafer, and defining the region where the sum of the characteristic values is calculated as the lowest, the wafer center, You can align the coordinates of and the preset coordinates accurately.

Further, after aligning the coordinates of the wafer and the inspection apparatus according to the coordinate alignment method, inspection time can be greatly reduced by inspecting for defects on the wafer, and defects on the wafer can be accurately inspected.

Considering the re-inspection in the current semiconductor production line, the shortening of inspection time reduces production costs, and it is possible to automate a large part of inspection equipment by actively aligning coordinates.

As described above, the present invention has been described with reference to the preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that it can be changed.

1 is a flowchart illustrating a conventional coordinate alignment method.

2 is a flowchart illustrating a coordinate alignment method according to an embodiment of the present invention.

3 is a simplified configuration diagram for explaining an active coordinate alignment inspection device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: Stage 120: Light emitting part

121: 1st polarizing member 123: 2nd polarizing member

125: condensing member 130: detection part

131 ： photomultiplier 132 ： power supply

140: control part 150: calculation part

160: Classification department 170: Memory department

W ： Wafer

Claims (10)

1. defining region-specific characteristic values on a semiconductor substrate; 2. defining a plurality of sets of two regions located at the same distance with respect to one region of the semiconductor substrate as a set; 3. calculating each of said plurality of sets of feature value differences; 4. summing up all of said characteristic value differences; 5. calculating a plurality of sum values by repeatedly performing the steps 2 to 4 while changing the coordinates of the reference area; And 6. The method of claim 2, further comprising matching the coordinates of the reference area from which the smallest sum is calculated among the plurality of sums to a preset coordinate. The coordinate alignment method of claim 1, wherein the characteristic value comprises a reflectance for each region on the semiconductor substrate. The coordinate alignment method of claim 1, wherein the plurality of regions formed on the semiconductor are symmetric about a central axis passing through a central portion of the semiconductor substrate. The coordinate alignment method of claim 3, wherein the coordinates of the reference area are changed on a diameter line perpendicular to the central axis. The coordinate alignment method of claim 1, wherein the center of the reference area at which the smallest sum is calculated is the center of the semiconductor substrate. The method of claim 1, wherein the preset coordinates are coordinates for indicating a position of a microstructure formed on a reference semiconductor substrate. A stage for supporting and transporting the semiconductor substrate; A light emitting unit spaced apart from the stage by a predetermined distance, and configured to irradiate light onto the semiconductor substrate; A detector configured to collect light reflected from the semiconductor substrate; A plurality of sets are defined by setting two regions connected to the detection unit and located at the same distance with respect to one region of the semiconductor substrate as a set, and repeatedly defining a plurality of sets while changing coordinates of the reference region. A control unit; An operation unit for defining a feature value for each region according to the collected reflected light, calculating a difference in feature values of each set for each reference region, and adding up the difference in feature values for each set for each reference region; And A determination unit for matching the center coordinates of the reference region corresponding to the lowest summation value among the plurality of summation values calculated by the operation unit with a preset coordinate, and determining whether there is a defect in the semiconductor substrate according to the matched coordinates; Active coordinate alignment inspection device, characterized in that. The active coordinate alignment inspection apparatus according to claim 7, wherein the preset coordinates are coordinates for indicating the position of the microstructure formed on the reference semiconductor substrate. 8. The active coordinate alignment inspection apparatus according to claim 7, wherein the detector comprises an optical multiplier for collecting and amplifying the reflected light and a power supply for applying power for operating the optical multiplier. 8. The active coordinate alignment according to claim 7, further comprising a storage unit connected to both the operation unit and the determination unit, wherein the storage unit stores the predetermined coordinates, the sum value calculated for each region, and the determination result. Mold inspection device.