KR20050009354A - Method of forming contact including plug implantation - Google Patents
Method of forming contact including plug implantation Download PDFInfo
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- KR20050009354A KR20050009354A KR1020030048595A KR20030048595A KR20050009354A KR 20050009354 A KR20050009354 A KR 20050009354A KR 1020030048595 A KR1020030048595 A KR 1020030048595A KR 20030048595 A KR20030048595 A KR 20030048595A KR 20050009354 A KR20050009354 A KR 20050009354A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 콘택저항을 개선시킨 반도체 소자의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for forming a contact of a semiconductor device having improved contact resistance.
반도체 소자가 고집적화될수록 빠른 동작속도를 요구하는 주변영역의 MOSFET들은 극도로 얕은 접합(ultra shallow junction)과 낮은 콘택저항이 필수적이다.As semiconductor devices become more integrated, ultra shallow junctions and low contact resistances are required for MOSFETs in peripheral regions that require fast operating speeds.
특히, 0.15㎛ 이상의 메모리 소자에서는 pMOSFET의 소스/드레인 접합을 금속배선과 연결시키는 콘택홀의 크기가 0.04㎛ 이상으로 통상의 콘택홀 형성 방법을 이용하여 요구되는 금속배선과 소스/드레인접합간의 콘택저항을 만족시킬 수 있었으나, 0.15㎛ 이하의 고집적 메모리 소자에서는 콘택홀의 크기가 0.04㎛ 이하로 매우 작아지므로 소스/드레인접합 형성 및 콘택홀 형성후 추가 이온주입과정을 수행하여 콘택저항을 확보한다.Particularly, in a memory device of 0.15 탆 or larger, the contact hole connecting the source / drain junction of the pMOSFET to the metal wiring is 0.04 탆 or larger, so that the contact resistance between the metal wiring and the source / drain junction required using a conventional contact hole forming method is required. However, in the highly integrated memory device having a size of 0.15 μm or less, the contact hole becomes very small, 0.04 μm or less, thereby securing contact resistance by performing an additional ion implantation process after forming the source / drain junction and forming the contact hole.
이와 같은 추가 이온주입과정은 플러그 이온 주입(plug implantation) 공정이라고도 일컬으며, 일반적으로 반도체 소자의 금속 콘택 형성 공정에서 소스/드레인 접합에 콘택홀을 형성한 후 금속 배선을 형성하기 전에 접합의 콘택 저항을 개선하기 위하여 소스/드레인 접합과 동일한 형태의 도펀트로 추가 이온 주입 공정을 실시한다.This additional ion implantation process is also referred to as a plug implantation process. In general, a contact resistance of a junction is formed before forming a metal wiring after forming a contact hole in a source / drain junction in a metal contact formation process of a semiconductor device. In order to improve the performance, an additional ion implantation process is performed with the same type of dopant as the source / drain junction.
도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 콘택 형성 방법을 도시한 공정 단면도이고, 도 2는 도 1c의 플러그 이온주입영역의 확대도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the related art, and FIG. 2 is an enlarged view of the plug ion implantation region of FIG. 1C.
도 1a에 도시된 바와 같이, 반도체 기판(11)의 소정영역에 소자분리막인 필드산화막(12)을 형성한 후 반도체 기판(11) 내에 pMOSFET을 정의하는 n형 웰(13)을 형성하고, 반도체 기판(11)의 선택된 영역상에 게이트절연막(14) 및 게이트전극(15)을 포함하는 게이트 구조를 공지의 방법으로 형성한다.As shown in FIG. 1A, after forming a field oxide film 12 as an isolation layer in a predetermined region of the semiconductor substrate 11, an n-type well 13 defining a pMOSFET is formed in the semiconductor substrate 11, and a semiconductor is formed. A gate structure including the gate insulating film 14 and the gate electrode 15 is formed on a selected region of the substrate 11 by a known method.
다음에, 반도체 기판(11) 상부에 절연층을 증착한 후, 전면식각을 진행하여 게이트전극(15)의 양측벽에 스페이서(16)를 형성한다.Next, after the insulating layer is deposited on the semiconductor substrate 11, the entire surface is etched to form spacers 16 on both side walls of the gate electrode 15.
그 다음, 스페이서(16) 외측의 반도체 기판(11)에 p형 도펀트, 예를들어, BF2이온 또는 B 이온을 주입하여 p형 소스/드레인 접합(17)을 형성한다.Then, a p-type dopant, for example, BF 2 ions or B ions, is implanted into the semiconductor substrate 11 outside the spacer 16 to form the p-type source / drain junction 17.
도 1b에 도시된 바와 같이, 반도체 기판(11) 상부에 층간절연막(18)을 증착한 후, 층간절연막(18)상에 p형 소스/드레인 접합(17)을 노출시키기 위한 감광막 패턴(19)을 공지의 포토리소그래피 방식에 의하여 형성한다. 그후, 감광막 패턴(19)을 식각마스크로 층간절연막(18)을 식각하여 콘택홀(20)을 형성한다.As shown in FIG. 1B, after depositing the interlayer insulating film 18 on the semiconductor substrate 11, the photoresist pattern 19 for exposing the p-type source / drain junction 17 on the interlayer insulating film 18. Is formed by a known photolithography method. Thereafter, the interlayer insulating layer 18 is etched using the photoresist pattern 19 as an etch mask to form the contact hole 20.
다음으로, p형 소스/드레인 접합(17)의 손상 부위를 치유하면서 콘택저항을 확보하기 위하여 플러그 이온주입을 진행하여 플러그 이온주입 영역(21)을 형성하는데, p형 소스/드레인 접합(17)에 붕소를 포함하는 이온을 이온주입한다.Next, in order to secure the contact resistance while healing the damaged portion of the p-type source / drain junction 17, a plug ion implantation region 21 is formed to form a plug ion implantation region 21. The p-type source / drain junction 17 Ions are implanted with ions containing boron.
다음에, 플러그 이온주입 영역(21)에 주입된 도펀트를 전기적으로 활성화시키기 위한 열처리 공정을 진행한다.Next, a heat treatment process is performed to electrically activate the dopant implanted into the plug ion implantation region 21.
도 1c에 도시된 바와 같이, 감광막 패턴(19)을 제거한 후, 노출된 p형 소스/드레인 접합(17)과 콘택되는 실리사이드막(22)과 확산방지금속막(23)의 적층막을형성한 후 금속배선(24)을 형성한다. 예를 들어 실리사이드막(22)은 티타늄막을 증착한 후 열처리 공정을 진행하여 p형 소스/드레인 접합(17)의 실리콘과 반응시켜 형성한 티타늄실리사이드막(Ti-silicide)이고, 확산방지금속막(23)은 티타늄나이트라이드막(TiN) 또는 티타늄막(Ti)과 티타늄나이트라이드막(TiN)의 적층막이다.As shown in FIG. 1C, after the photoresist pattern 19 is removed, a laminated film of the silicide layer 22 and the diffusion barrier metal layer 23 in contact with the exposed p-type source / drain junction 17 is formed. The metal wiring 24 is formed. For example, the silicide film 22 is a titanium silicide film (Ti-silicide) formed by reacting with silicon of the p-type source / drain junction 17 by depositing a titanium film and performing a heat treatment process. 23 is a titanium nitride film (TiN) or a laminated film of titanium film (Ti) and titanium nitride film (TiN).
전술한 종래 기술은 실리사이드막(22)이 티타늄막과 p형 소스/드레인 접합(17)의 실리콘이 반응하여 형성되는 것이기 때문에, 플러그 이온주입영역(21)의 손실이 불가피하다.Since the silicide film 22 is formed by the reaction between the titanium film and the silicon of the p-type source / drain junction 17, the loss of the plug ion implantation region 21 is inevitable.
즉, 도 2에 도시된 바와 같이, p형 소스/드레인 접합(17)측으로 확장되는 실리사이드막(20)의 면적(d)만큼 플러그 이온주입영역(19)에 주입된 도펀트들이 묻히게 되어 추가 이온주입된 도펀트들의 콘택저항 낮춤 효과를 충분히 발휘할 수 없는 문제가 있다.That is, as shown in FIG. 2, dopants implanted into the plug ion implantation region 19 are buried as much as the area d of the silicide layer 20 extending toward the p-type source / drain junction 17 to further implant the ion. There is a problem that the contact resistance lowering effect of the dopants cannot be sufficiently exhibited.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 플러그 이온주입이 이루어진 소스/드레인접합내 도펀트가 후속 실리사이드 공정시 손실되는 것을 방지하여 콘택저항을 개선시킬 수 있는 반도체 소자의 콘택 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and prevents the dopant in the source / drain junction in which the plug ion implantation is performed is prevented from being lost during the subsequent silicide process, thereby forming a contact of a semiconductor device capable of improving contact resistance. The purpose is to provide a method.
도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 콘택 형성 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the prior art;
도 2는 도 1c의 플러그 이온주입영역의 확대도,2 is an enlarged view of the plug ion implantation region of FIG. 1C;
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 도시한 공정 단면도.3A to 3E are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 필드산화막31 semiconductor substrate 32 field oxide film
33 : n형 웰 34 : 게이트절연막33: n-type well 34: gate insulating film
35 : 게이트전극 36 : 스페이서35 gate electrode 36 spacer
37 : p형 소스/드레인 접합 38 : 층간절연막37: p-type source / drain junction 38: interlayer insulating film
39 : 감광막 패턴 40 : 콘택홀39: photosensitive film pattern 40: contact hole
41 : 티타늄막 43 : 티타늄나이트라이드막41 titanium film 43 titanium nitride film
43 : 플러그 이온주입영역 44 : 티타늄실리사이드막43: plug ion implantation region 44: titanium silicide film
45 : 텅스텐플러그45: tungsten plug
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택 형성 방법은 p형소스/드레인 접합이 형성된 반도체 기판 상에 층간절연막을 형성하는 단계, 상기 p형 소스/드레인 접합의 일부를 노출시키도록 상기 층간절연막 내에 콘택홀을 형성하는 단계, 상기 콘택홀의 표면을 따라 상기 층간절연막 상에 배리어메탈을 형성하는 단계, 상기 배리어메탈이 형성된 상태에서 플러그 이온주입을 진행하여 p형 소스/드레인접합 내에 플러그 이온주입영역을 형성하는 단계, 열처리 공정을 진행하여 상기 플러그 이온주입영역과 상기 배리어메탈의 계면에 실리사이드막을 형성함과 동시에 상기 플러그 이온주입영역 내에 주입된 도펀트를 활성화시키는 단계, 및 상기 콘택홀을 채우는 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.The method of forming a contact of a semiconductor device according to the present invention for achieving the above object comprises forming an interlayer insulating film on a semiconductor substrate on which a p-type source / drain junction is formed and exposing a portion of the p-type source / drain junction; Forming a contact hole in the insulating film, forming a barrier metal on the interlayer insulating film along the surface of the contact hole, and performing plug ion implantation in the state where the barrier metal is formed, thereby injecting plug ion into the p-type source / drain junction. Forming a region, performing a heat treatment process to form a silicide film at an interface between the plug ion implantation region and the barrier metal, and simultaneously activating the dopant implanted in the plug ion implantation region, and a plug filling the contact hole It characterized in that it comprises a step of forming.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 콘택 형성 방법을 도시한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method for forming a contact of a semiconductor device according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 반도체 기판(31)의 소정 영역에 LOCOS(Local oxidation of silicon)법을 이용하여 소자분리막인 필드산화막(32)을 형성한다. 여기서, 필드산화막(32)은 STI(Shallow Trench Isolation)법을 이용하여 형성할 수도 있다.As shown in FIG. 3A, a field oxide film 32, which is an isolation layer, is formed in a predetermined region of the semiconductor substrate 31 by using a local oxidation of silicon (LOCOS) method. The field oxide film 32 may be formed using a shallow trench isolation (STI) method.
다음으로, 반도체 기판(31)에 인(Phosphorous; P)과 같은 n형 도펀트를 이온주입하여 n형 웰(33)을 형성한 후, 반도체 기판(31) 상에 게이트절연막(34)과 게이트전극(35)을 형성한다.Next, an n-type well 33 is formed by ion implantation of an n-type dopant such as phosphorous (P) into the semiconductor substrate 31, and then a gate insulating film 34 and a gate electrode on the semiconductor substrate 31 are formed. (35) is formed.
이때, 게이트절연막(34)으로는 열산화막, 질화산화막(oxynitride), 고유전막 또는 산화막/고유전막의 적층막중에서 하나를 선택하여 사용한다. 그리고, 게이트전극(35)은 폴리실리콘막, 폴리실리콘막과 실리사이드의 적층막, 폴리실리콘막과 금속막의 적층막, 실리콘게르마늄막, 실리콘게르마늄막과 금속막의 적층막 또는 금속막중에서 하나를 선택하여 사용하며, 실리콘질화막과 같은 하드마스크(hard mask)를 최상부에 포함할 수 있다.At this time, the gate insulating film 34 may be selected from a thermal oxide film, an oxynitride film, a high dielectric film, or a laminated film of an oxide film / a dielectric film. The gate electrode 35 is selected from among a polysilicon film, a polysilicon film and a silicide lamination film, a polysilicon film and a metal film lamination film, a silicon germanium film, a silicon germanium film and a metal film lamination film, or a metal film. In this case, a hard mask such as a silicon nitride film may be included on the top.
다음으로, 반도체 기판(31) 상부에 절연층을 증착한 후, 전면식각을 진행하여 게이트전극(35)의 양측벽에 스페이서(36)를 형성한다. 이때, 스페이서(36)를 형성하는 절연층은 실리콘질화막, 실리콘산화막 또는 실리콘질화막과 실리콘산화막의 조합을 이용한다.Next, after the insulating layer is deposited on the semiconductor substrate 31, the entire surface is etched to form spacers 36 on both sidewalls of the gate electrode 35. At this time, the insulating layer forming the spacer 36 uses a silicon nitride film, a silicon oxide film, or a combination of a silicon nitride film and a silicon oxide film.
그 다음, 스페이서(36) 외측의 반도체 기판(31)에 p형 도펀트, 예를들어49BF2,11B 또는30BF 이온을 주입하여 p형 소스/드레인 접합(37)을 형성한다.Then, a p-type dopant, for example 49 BF 2 , 11 B or 30 BF ions, is implanted into the semiconductor substrate 31 outside the spacer 36 to form the p-type source / drain junction 37.
도 3b에 도시된 바와 같이, 반도체 기판(31) 상부에 층간절연막(38)을 증착한다. 이때, 층간절연막(38)은 실리콘산화막 또는 실리콘질화막 상부에 갭필(Gapfill)용 BPSG(Boro Phospho Silicate Glass), HDP CVD(High Density Plasma Chemical Vapor Deposition)막 또는 저유전율막 등이 적층된 막이다.As shown in FIG. 3B, an interlayer insulating film 38 is deposited on the semiconductor substrate 31. At this time, the interlayer insulating film 38 is a film in which a BPSG (Bop Phospho Silicate Glass), HDP CVD (High Density Plasma Chemical Vapor Deposition) film, or a low dielectric constant film is laminated on the silicon oxide film or the silicon nitride film.
다음에, 층간절연막(38) 상에 p형 소스/드레인접합(37)을 노출시키기 위한 감광막 패턴(39)을 공지의 포토리소그래피 방식에 의하여 형성한다.Next, a photosensitive film pattern 39 for exposing the p-type source / drain junction 37 on the interlayer insulating film 38 is formed by a known photolithography method.
다음으로, 감광막 패턴(39)을 식각마스크로 층간절연막(38)을 식각하여 콘택홀(40)을 형성한다. 이때, 콘택홀(40)을 형성하기 위한 식각 공정으로 p형 소스/드레인 접합(37)의 표면은 소정 부분 손상될 수 있다.Next, the interlayer insulating layer 38 is etched using the photoresist pattern 39 as an etch mask to form the contact hole 40. In this case, the surface of the p-type source / drain junction 37 may be partially damaged by an etching process for forming the contact hole 40.
도 3c에 도시된 바와 같이, 감광막패턴(39)을 제거한 후 콘택홀(40)의 프로파일을 따라 배리어막을 증착한다. 이때, 배리어막은 티타늄막(41)과 티타늄나이트라이드막(42)을 차례로 형성한 것이다.As shown in FIG. 3C, the barrier layer is deposited along the profile of the contact hole 40 after removing the photoresist pattern 39. In this case, the barrier film is formed by sequentially forming the titanium film 41 and the titanium nitride film 42.
여기서, 배리어막으로 사용된 티타늄막외에도 코발트막(Co) 또는 니켈막(Ni)을 이용하고, 티타늄나이트라이드막(42)외에 텅스텐나이트라이드막(WN)을 이용할 수 있다.Here, a cobalt film (Co) or a nickel film (Ni) may be used in addition to the titanium film used as the barrier film, and a tungsten nitride film (WN) may be used in addition to the titanium nitride film 42.
한편, 티타늄나이트라이드막(42)은 티타늄막(41)이 대기 중에 노출되는 것을 방지하여 장기간 노출에 따른 자연 산화막의 형성 및 오염원의 발생으로부터 티타늄막(41)을 보호하는 역할도 한다.On the other hand, the titanium nitride film 42 serves to prevent the titanium film 41 from being exposed to the atmosphere, thereby protecting the titanium film 41 from formation of a natural oxide film and generation of pollutants due to prolonged exposure.
다음으로, p형 소스/드레인 접합(37)에 콘택저항을 확보하기 위하여 플러그 이온주입을 진행하는데, p형 소스/드레인 접합(37)에49BF2,11B,30BF 또는 인듐(In) 이온을 주입하여 플러그 이온주입영역(43)을 형성한다.Next, plug ion implantation is performed to secure contact resistance to the p-type source / drain junction 37, and 49 BF 2 , 11 B, 30 BF or indium (In) is applied to the p-type source / drain junction 37. Ions are implanted to form the plug ion implantation region 43.
플러그 이온주입영역(43)을 형성하기 위한 이온주입 조건을 살펴보면,49BF2이온을 주입하는 경우에는 5keV∼30keV의 이온주입에너지와 1E13∼1E16/cm2의 도즈로 진행하고,11B 또는30BF 이온을 주입하는 경우에는 3keV∼15keV의 이온주입에너지와 1E13∼1E16/cm2의 도즈로 진행하며, 인듐(In) 이온을 주입하는 경우에는 20keV ∼40keV의 이온주입에너지와 1E13∼1E16/cm2의 도즈로 진행한다. 위 이온주입조건 모두 공통적으로 틸트를 0∼9°로 주면서 -60°∼60°도로 0∼4회 로테이션(rotation)하면서 실시한다.In the ion implantation conditions for forming the plug ion implantation region 43, when 49 BF 2 ions are implanted, the ion implantation energy of 5 keV to 30 keV and the dose of 1E13 to 1E16 / cm 2 are proceeded and 11 B or 30 In the case of implanting BF ions, it proceeds with an ion implantation energy of 3 keV to 15 keV and a dose of 1E13 to 1E16 / cm 2 , and when implanting indium (In) ions, an ion implantation energy of 20 keV to 40 keV and 1E13 to 1E16 / cm Proceed to the dose of 2 . All of the above ion implantation conditions are carried out with rotation of 0-4 times at -60 ° -60 ° while giving a tilt of 0-9 °.
위와 같은 일련의 이온주입공정에 의해 형성되는 플러그 이온주입영역(43)의 Rp(projection of range)는 후속 티타늄실리사이드막의 플러그 이온주입영역(43)과의 반응깊이를 고려하여 티타늄실리사이드막과 플러그 이온주입영역(43)의 계면에 위치시킨다. 이와 같은 Rp 위치는 이온주입에너지를 조절하면 가능하다.The projection of range (Rp) of the plug ion implantation region 43 formed by the series of ion implantation processes as described above takes into account the depth of reaction with the plug ion implantation region 43 of the subsequent titanium silicide layer and the titanium silicide layer and the plug ion. It is located at the interface of the injection region 43. This Rp position is possible by adjusting the ion implantation energy.
도 3d에 도시된 바와 같이, 플러그 이온주입 영역(41)에 주입된 도펀트를 전기적으로 활성화시키기 위한 열처리(annealing)를 진행한다. 이때, 열처리 도중에 티타늄막과 p형 소스/드레인 접합의 실리콘원자가 반응하여 티타늄실리사이드막(44)이 동시에 형성된다.As shown in FIG. 3D, annealing is performed to electrically activate the dopant implanted into the plug ion implantation region 41. At this time, during the heat treatment, the titanium film and the silicon atoms of the p-type source / drain junction react to form the titanium silicide film 44 at the same time.
전술한 바와 같은 열처리는, 500℃∼1100℃에서 NH3, Ar, N2또는 N2O 분위기로 5초∼1000초동안 실시하되, 승온 및 냉각 속도를 15℃/초∼100℃/초로 설정하여 진행한다.The heat treatment as described above is performed for 5 seconds to 1000 seconds in an atmosphere of NH 3 , Ar, N 2 or N 2 O at 500 ° C. to 1100 ° C., but the temperature and cooling rate are set to 15 ° C./second to 100 ° C./second Proceed by
도 3e에 도시된 바와 같이, 티타늄나이트라이드막(42) 상에 콘택홀을 채울때까지 텅스텐막을 증착한 후, 콘택홀을 제외한 부분의 텅스텐막과 티타늄나이트라이드막(42) 및 티타늄막(41)을 제거하여 콘택홀에 매립되는 텅스텐플러그(45)를 형성한다.As shown in FIG. 3E, after the tungsten film is deposited on the titanium nitride film 42 until the contact hole is filled, the tungsten film, the titanium nitride film 42 and the titanium film 41 except for the contact hole are deposited. ) Is removed to form a tungsten plug 45 embedded in the contact hole.
텅스텐플러그(45)를 형성하기 위한 다양한 방법을 설명하면 다음과 같다. 제1방법은 에치백을 통해 텅스텐막과 배리어메탈을 한번의 에치백 공정을 통해 형성하거나, 텅스텐막을 화학적기계적연마(CMP)를 통해 평탄화한 후 에치백을 통해 배리어메탈을 제거하여 형성하거나, 텅스텐막과 배리어메탈을 한번에 화학적기계적연마하여 형성할 수 있다.Hereinafter, various methods for forming the tungsten plug 45 will be described. In the first method, the tungsten film and the barrier metal are formed through an etch back through a single etch back process, or the tungsten film is planarized through chemical mechanical polishing (CMP) and then the barrier metal is removed through the etch back. The film and barrier metal can be formed by chemical mechanical polishing at once.
전술한 실시예에서는 텅스텐플러그(45)를 예로 들었으나, 콘택물질로 알루미늄(Al), 알루미늄합금, 구리(Cu) 또는 구리합금 등의 금속막을 이용할 수도 있다.In the above embodiment, the tungsten plug 45 is taken as an example, but a metal film such as aluminum (Al), aluminum alloy, copper (Cu), or copper alloy may be used as the contact material.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 티타늄실리사이드막 형성에 따른 도펀트 손실없이 후속 열처리를 통해 이온주입된 활성화된 도펀트량을 증가시켜 콘택저항 특성을 개선시킬 수 있는 효과가 있다.The present invention described above has the effect of increasing the amount of activated dopants implanted with ion implantation through subsequent heat treatment without loss of dopant due to the formation of the titanium silicide layer, thereby improving contact resistance characteristics.
또한, 배리어메탈 형성후 추가이온주입한 도펀트를 배리어메탈의 열처리시 동시에 활성화시키므로써 한 번의 열처리 공정을 생략할 수 있어 공정단순화 및 원가절감의 효과가 있다.In addition, since the dopant implanted with additional ions after the formation of the barrier metal is simultaneously activated during the heat treatment of the barrier metal, one heat treatment step can be omitted, thereby simplifying the process and reducing the cost.
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| US7338871B2 (en) | 2004-06-25 | 2008-03-04 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
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