KR20050007439A - Carrier recovery for dtv receivers - Google Patents

Abstract

The system 300 and method for symbol clock recovery independent of segment position recovery generates a signal 399 that uses the frequency and phase information to correct the symbol clock at the upper and lower band edges of the signal. Route-2 power cosine filters 320, 330, low pass filters 348, 368, 397, multipliers 302, 304, 322, 324, 332, 334, 380, 390, and adders 340, 350, 360 The specific combination of, 370, 395 corrects the phase error using the tail d of the signal 200 received in the frequency domain efficiently.

Description

DVD recovery for carriers {CARRIER RECOVERY FOR DTV RECEIVERS}

Typically, local communication has been done over the wire, because wired communication allows for cost-effective and reliable delivery of information. For long distance communication, transmission of information by radio waves is required. While this is straightforward from a hardware point of view, radio frequency (RF) transmissions cause information corruption and often require high power transmitters to overcome interference from weather conditions, large buildings, and other sources of electromagnetic radiation. .

Various modulation techniques developed have proposed various solutions in terms of cost efficiency and received signal quality, but until recently, these techniques were mainly analog. Frequency modulation and phase modulation provide some immunity to noise, while amplitude modulation simplifies demodulation. Recently, however, with the advent of low cost microcontrollers and the introduction of domestic mobile phones and satellite communications, digital modulation has become popular. Digital modulation technology achieves all the advantages of conventional microprocessor circuits over its counterpart, analog modulation technology. Problems in the communication link can be overcome using software. The information can be encrypted, error correction of the received data is more reliable, and the use of digital signal processing can reduce the limitation on the bandwidth allocated to each service.

Like conventional analog systems, digital modulation can use amplitude, frequency or phase modulation with several advantages. Because frequency and phase modulation techniques have better immunity to noise, these technologies are the preferred technologies for most services in use today.

US Patent Application No. 60 / 370,326, filed Apr. 5, 2002, and US Application No., filed Apr. 4, 2003, claim priority of US Utility Patent Application. This application is also related to a US utility application entitled "System and Methods for Symbol Clock Recovery" filed with the same date.

1 is a frequency-domain diagram illustrating certain features of a typical VSB signal.

2 is a block diagram of a circuit for carrier recovery in accordance with the present invention.

FIG. 3 is a diagram of specific features of a VSB signal passing through a particular point in time of the circuit shown in FIG.

Simple changes from conventional analog frequency modulation can be implemented by applying a digital signal to the modulation input. Because of this, the output takes the form of a sine wave at two separate frequencies. To demodulate this waveform, the signal is passed through two filters and the resulting signal is converted back to a logic level. This type of digital frequency modulation is commonly referred to as frequency shift keying.

In terms of spectrum, the digital phase modulation or phase shift scheme is very similar to the frequency modulation. This involves changing the phase of the transmitted waveform instead of frequency, which represents a finite phase change. In its simplest form, digital data is used to generate a phase modulated waveform to switch between two signals of equal frequency but opposite phases. If the resulting waveform is multiplied by a sine wave of the same frequency, two components are generated. One is a cosine waveform that is twice the frequency received and one is a frequency-independent term whose amplitude is proportional to the cosine of the phase shift. Thus, filtering out the higher frequency term results in the original digital data.

Considering the above concept of making the stage a phase shift method, the number of possible phases can be increased by more than two. The transmitted "carrier" will undergo a change in any number of phases and will demodulate the phase shift to a frequency-independent voltage level by multiplying the received signal by a sine wave of the same frequency.

An example of this technique is the four-phase phase incorporation method (QPSK). By the four-phase phase shift scheme, the carrier can change any of the four phases to display any four values per phase change. This is initially considered invalid, but it provides a modulation scheme that allows the carrier to transmit two bits of information per symbol instead of one, thereby effectively doubling the data bandwidth of the carrier.

A mathematical proof of how to demodulate a phase modulated signal and thus QPSK is shown below.

Euler's relations are characterized by the following sine and cosine:

here . Therefore, the multiplication of two sinusoids of the same frequency and phase is given as follows.

The digital receiver does this by mixing the incoming sine signal with the oscillator output. As the equation shows, this result is a sine output with a frequency that is twice the input frequency and an amplitude that is half of the amplitude of the input, and is superimposed on a DC offset of half the input amplitude.

Similarly, multiplying sin (ωt) and cos (ωt) gives

The result is a sine output with a frequency that is twice the input frequency, with no DC offset.

It can be seen that multiplying the cosine wave with any phase-shifted sine wave produces a "demodulated" waveform with an output frequency that is twice the input frequency, whose DC offset varies with the phase shift φ.

Thus, the variable phase shifted carrier is demodulated to a variable output voltage by multiplying the sine output from the carrier and the local oscillator and filtering out the high frequency components. Unfortunately, phase shift detection is limited to two quadrants, and a phase shift of π / 2 cannot be distinguished from a phase shift of -π / 2. Therefore, in order to correctly decode the phase shifts provided for all four quadrants, it is necessary to multiply the input signal by both sine and cosine waveforms, remove high frequency filtering, and reconstruct the data. Expanding the above equations:

However, the process of low pass filtering the output of the mixer and reconstructing the four voltages back to the logic level to remove data from the carrier is not straightforward. In practice, it is also not easy to accurately synchronize the local oscillator with the incoming signal at the receiver. If the local oscillator is different in phase from the incoming signal, the signal in the phasor diagram will undergo phase rotation of the same magnitude as the phase difference. In addition, if the phase and frequency of the local oscillator are not fixed with respect to the incoming signal, they will continue to rotate on the phaser diagram. Therefore, the output of the front-end demodulator is typically supplied to an analog-to-digital (A / D) converter, and any rotation due to an error in the phase or frequency of the local oscillator is eliminated in processing the digital signal.

Another problem with extracting data from carriers is inter-symbol interference (ISI). The ISI occurs when generating information in pulses, such as amplitude modulated digital transmissions, for example transmitted over analog channels such as telephone lines or over-the-air broadcasts. The original signal begins with a suitable approximation of the discontinuous time sequence but the received signal is a continuous time signal. In the form of an impulse train, the peak spreads or spreads by transmission to a differential signal that is related to the amplitude of the original pulse. The signal is read by digital hardware and periodically samples the received signal.

Each pulse produces a signal that normally approaches one sink wave. Those skilled in the art will understand that the sink wave is characterized by a series of peaks concentrating on one major peak, having a peak size that decreases monotonically with distance from the increasing main peak. . Equally, the sink wave has a series of troughs that include a magnitude that gradually decreases with increasing distance from the main peak. In general, the period of the peaks depends on the order of sampling rate of the receiving hardware. Thus, the magnitude at a single sampling point of the signal is affected by the contribution from the pulse corresponding to the other bits in the transport stream as well as the magnitude of the pulse corresponding to the point in the transmission signal. In other words, a portion of the signal is generated corresponding to a single symbol in the transport stream that tends to cause unnecessary contributions to the portion of the received signal that corresponds to the arrival of other symbols in the transport stream.

The effect may be partially eliminated by the inherent shape of the pulse, for example by pulses generated by including a zero value in a regular interval corresponding to the sampling rate. However, what is needed is the receiver to generate a sample at a precise time instant to have a maximum signal power and a minimum inter-symbol interface. Since the transmitter and receiver typically have separate crystal oscillators, one digital receiver must attempt to tune to the transmitter clock. In other words, the receiver must extract the clock information from the received signal and then adjust the A / D timing. This is known as symbol clock recovery.

The Advanced Television Systems Committee (ATSC) chose Residual Sideband ("VSB") modulation as the transmission standard for digital television ("DVT"). In the ATSC standard, 8 VSB is the standard for terrestrial broadcast, while 16 VSB is used as the standard for cable transmission. (The International Telecommunications Union (ITU) standard defines five VSB modes, namely 2, 4, 8, 16, and 8T).

Typically, 8 VSBs use three supplementary signals for synchronization. First, a low level RF pilot is used for carrier acquisition. Second, as shown in Fig. 1, four-symbol data-segment synchronization is used once every 832 symbols, i.e., once every segment, to synchronize the data clock in frequency and phase. (Usually, 4 symbols are normalized to [1, -1, -1, 1]). Finally, 832-symbol data-framing synchronization is used once every 313 segments for data framing and equalizer training. The data-frame sync also includes information identifying one of 8 VSB, 16 VSB or other suitable ITU modes.

The pilot signal has 0.3 dB power. Although pilot recovery is typically reliable, it may fail under certain circumstances, such as in a strong, contiguous, and slow moving multipathing situation.

Since this type of multipathing is common in urban environments where broadcast digital transmission would be desirable, it is important to develop this commercially for digital television and to address this problem in improving other digital transmission systems.

Therefore, there is a need for a new system and method for carrier recovery that is capable of performing symbol clock recovery from an 8 VSB signal and even independent of carrier recovery and segment position recovery even when the segment sync signal is completely destroyed or severely changed. The present invention is particularly intended to meet these needs.

To enhance understanding of the principles of the present invention, reference will now be made to the embodiments shown in the drawings, and specific language will be used to describe it. Nevertheless, it will be understood that this does not limit the scope of the invention. Those skilled in the art can make changes and modifications to the illustrated apparatus as well as further apply the principles of the invention as illustrated herein.

The carrier recovery system according to the present invention provides more reliable recovery since both the pilot and the upper and lower band edges can be used. It is thus more reliable, especially in urban environments where ghosts are usually present. The carrier recovery system according to the present invention can be recovered even if the pilot is lost by perfect null.

1 illustrates certain features of the VSB signal spectrum, usually indicated at 100. In this example, the major portion 110 of the signal 100 is 5.38 MHz wide, which includes the unattenuated portion 105 in the 3 dB attenuated portion 110. However, the amplitude is not fully damped outside the main frequency domain. In this example, the actual signal is at additional 0.31 MHz up and down in the main portion 110 of the signal, which is represented by 115. These "band edges" can be used for carrier recovery, as described below.

FIG. 2 is a block diagram of a circuit according to the present invention, shown at 200, with a signal corresponding to the particular time points shown in FIG. The signal is input from 201 to 200 from an A / D converter (not shown), which preferably runs at twice the symbol rate. It will be appreciated that sampling at twice the symbol rate is sufficient to meet the Nyquist condition. Upstream A / D converters can sample the input signal at sample rates greater than twice the sample rate, but if the hardware frequency increases beyond this point, the hardware cost is increased without correspondingly increasing performance. Circuit 200 includes a digitally controlled oscillator (“DCO”) 210 that generates two signals, sin (ωn) and cos (ωn), where “n” is a symbol count. The first multiplier 202 multiplies the input signal by the cos (ωn) signal, and the second multiplier 204 multiplies the input signal by sin (ωn). The output from the first and second multipliers 202 and 204 then passes through first and second root-rasised cosine (RRC) filters 220 and 230, respectively. The output of the first RRC filter 220 is multiplied by sin (πn / 4) in the third multiplier 222 and multiplied by cos (πn / 4) in the fourth multiplier 224. Similarly, the output from the second RRC filter 230 is multiplied by sin (πn / 4) in the fifth multiplier 232 and multiplied by cos (πn / 4) in the sixth multiplier 234.

The output from the sixth multiplier 234 is subtracted from the output from the third multiplier 222 by the first accumulator 240 and the output from the third multiplier 222 by the third accumulator 260. Is added. The output of the fifth multiplier 232 is subtracted from the output of the fourth multiplier 224 by the second accumulator 250 and added to the output of the fourth multiplier 224 by the fourth accumulator 270. . The output from the second accumulator 250 is passed to a first IIR (low pass infinite impulse response) filter 248, which preferably has a -3 dB attenuation at about 70 KHz, to filter out high frequency components beyond the band edge. do.

The output of the IIR filter 348 passes through the first limiter 246. The first limiter 246 assigns a value of 1 to some definition input and a value of -1 to some negative input. (The skilled person will recognize this as a sign function.) The output from the first limiter 246 is multiplied by the output from the first accumulator 240 using the seventh multiplier 280. It will be appreciated that the output of the seventh multiplier 280 is multiplied by two RRC filters so that this signal is effectively multiplied by the entire plain raised cosine filter. The output of 280 indicates frequency and phase correction information obtained from the lower band edge.

The output from the fourth accumulator 270 is passed to a second low pass IIR filter 268, preferably with a -3 dB attenuation at 70 KHz, to filter out high frequency components beyond the band edge. Output from the filter 268 passes through a second limiter 266. Similar to the first limiter 246, the second limiter 266 assigns a value of 1 to some definition input and a value of -1 to some negative input. The output from the second limiter is multiplied by the output from the third accumulator 260 using the eighth multiplier 290. It will be appreciated that the output of the eighth multiplier 290 indicates the frequency and phase correction information obtained from the upper band edge.

The output of the seventh multiplier 280 is then multiplied by the weight factor "k" using the ninth multiplier 285. The output of the eighth multiplier 290 is subtracted from the output of the ninth multiplier 285 using a fifth accumulator 295. The output from the fifth accumulator 295 is then passed through a third low pass IIR filter 297 which generates a signal provided to the DCO controller 299, which passes through the feedback loop providing carrier recovery. Complete

Those skilled in the art will appreciate that the lower band edge of the VSB signal includes a pilot signal. This is due to the weighting factor applied by the ninth multiplier 385. Typically, when k is about 0.3, the upper and lower band edge contributions will be properly balanced.

Those skilled in the art can make various changes in implementing the present invention. For example, some or all of the signal generation and calculation may be performed by an on-demand semiconductor or general purpose integrated circuit, or discrete elements or software.

While the invention has been shown and described in detail in the drawings and above description, it is intended to be illustrative and not restrictive, and it is to be understood that only the preferred embodiments have been illustrated and described, but include all modifications and variations that fall within the principles of the invention. .

Claims (5)

A method of demodulating a received signal, Receiving a stream of digital data comprising a sequence of data elements (s _t ) indicative of the received signal; using a digitally tuned oscillator to generate a sequence of data element indicators of sin (2πt / μs), and a sequence of data element indicators of cos (2πt / μs); Determining; Determining; Determining; Determining; and First output signal Providing a step, here, RRCs are root-2 power cosine filters; And L ₁ , L ₂ , and L ₃ are infinite impulse response low pass filters having a predetermined pass band. 2. The method of claim 1, further comprising adjusting the symbol clock in response to the first output signal. The method of claim 1, And providing the second output signal v _t = b _t + d _t . A system for processing a received signal having a predicted center frequency at 0, 0 dB bandwidth (b ₀ ) and -3 dB bandwidth (b ₃ ), An oscillator digitally tuned to generate at least one sinusoidal signal for mixing with the received signal; Generating an adjustment signal for the oscillator as a function of the frequency-domain component of the received signal having frequencies f ₁ and f _h , , And Received signal processing system comprising digital signal processing means. A method of demodulating a received signal, Receiving a stream of digital data comprising a sequence of data elements representing a received signal sampled in accordance with a clock, the clock being adjusted in frequency and / or phase by a clock adjustment signal; Multiplying the sequence of data elements by a digital cosine wave of a target frequency and passing the result through a first root-two power cosine filter to generate a first intermediate sequence; Multiplying the sequence of data elements by a digital sine wave at a target frequency and passing the result through a first root-two cosine filter to generate a second intermediate sequence; Multiplying the first intermediate sequence by a digital sine wave that is one quarter of the target frequency to generate a third intermediate sequence; Multiplying the first intermediate sequence by a digital cosine wave that is 1/4 of the target frequency to generate a fourth intermediate sequence; Multiplying the second intermediate sequence by a digital cosine wave that is 1/4 of the target frequency to generate a fifth intermediate sequence; Multiplying the second intermediate sequence by a digital sine wave that is one quarter of the target frequency to generate a sixth intermediate sequence; Subtracting the fifth intermediate sequence from the third intermediate sequence to generate a seventh intermediate sequence; Subtracting the sixth intermediate sequence from the fourth intermediate sequence to generate an eighth intermediate sequence; Obtaining a ninth intermediate sequence according to a product of a predetermined constant (k), the sign of the result of passing the eighth intermediate sequence with the seventh intermediate frequency and the infinite impulse response low pass filter; Generating a tenth intermediate sequence by adding the third intermediate sequence and the ninth intermediate sequence; Generating an eleventh intermediate sequence by adding the fourth intermediate sequence and the sixth intermediate sequence; Obtaining a twelfth intermediate sequence according to the product of the sign of the result of passing the eleventh intermediate sequence with the tenth intermediate sequence and the infinite impulse response low pass filter; Adding the ninth intermediate sequence and the twelfth intermediate sequence to generate a thirteenth intermediate sequence; And, And adjusting the clock as a function of the result of passing the thirteenth intermediate sequence with an infinite impulse response low pass filter.