KR20050003255A - Method for testing liquid crystal display panel - Google Patents

Abstract

PURPOSE: A method for testing an LCD panel is provided to improve reliability in detecting a defect of a LOG(Line On Glass) LCD panel by transmitting first test signals through lines having a low resistance value and second test signals through LOG lines loaded on a thin film transistor array substrate. CONSTITUTION: In a method for testing an LOG LCD, lines for transmitting driving signals from a data PCB(Printed Circuit Board)(231) to a gate PCB(221) are loaded in a panel. First test signals(TEST1) are applied to the gate PCB through test lines that electrically connect the data PCB with the gate PCB, and at least one second test signal(TEST2) is applied to the gate PCB through the lines loaded in the panel. At least one of gate high voltage signals(Vgh), gate low voltage signals(Vgl), common voltage signals(Vcom), ground signals(GND), power voltage signals(Vdd), gate start pulse signals(GSP), and gate enable signals(GOE) is used as the first test signals.

Description

Inspection method of liquid crystal display panel {METHOD FOR TESTING LIQUID CRYSTAL DISPLAY PANEL}

The present invention relates to a method of inspecting a liquid crystal display panel, and more particularly, a line-on-glass (LOG) type liquid crystal display panel in which wirings for transmitting a gate signal are mounted on the liquid crystal display panel. The inspection method of the liquid crystal display panel to improve the reliability of the detection of defects.

In general, among the screen display devices that display image information on the screen, the thin-film flat panel display device has been the subject of intensive development in recent years because of its advantages of being light and easy to use anywhere. In particular, liquid crystal displays have high resolution and are fast in reaction speeds sufficient to realize moving images, and thus are the most active studies.

The principle of the liquid crystal display device is to use the optical anisotropy and polarization properties of the liquid crystal. That is, by artificially adjusting the alignment direction of liquid crystal molecules having directionality using polarization, light can be transmitted and blocked by optical anisotropy according to the alignment direction of the liquid crystal. This application is used as a display device. Currently, an active matrix liquid crystal display in which thin film transistors and pixel electrodes connected thereto are arranged in a matrix manner is most commonly used because it provides excellent image quality. The structure of a general liquid crystal display device will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a general liquid crystal display device, and as shown therein, a liquid crystal display panel 110; Gate tape carrier packages (TCP, 122) connected between one side of the liquid crystal display panel 110 and a gate (printed circuit board: PCB) 121; Gate driver integrated circuits (ICs) 123 respectively mounted on the gate TCPs 122; Data TCPs 132 connected between the long side of one side of the liquid crystal display panel 110 and the data PCB 131; Data driver ICs 133 mounted on the data TCPs 132, respectively.

The liquid crystal display panel 110 is bonded to face the thin film transistor array substrate 111 and the color filter substrate 112 to have a constant cell gap, and a liquid crystal layer is formed at the cell gap.

One short side and one long side of the thin film transistor array substrate 111 protrude from the color filter substrate 112, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 111. In addition, an image display unit 113 is provided in an area where the thin film transistor array substrate 111 and the color filter substrate 112 face each other.

In the image display unit 113 of the thin film transistor array substrate 111, a plurality of gate lines 120 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 130 are arranged in a vertical direction. It is connected to the data pad part. Accordingly, the gate lines 120 and the data lines 130 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersection thereof.

The image display unit 113 of the color filter substrate 112 includes a color filter of red, green, and blue colors which are separated and applied for each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 111.

Gate driver ICs 123 are mounted on the gate TCP 122, and input pads 124 and output pads 125 electrically connected to the gate driver ICs 123 are formed.

The input pads 124 of the gate TCP 122 are electrically connected to the gate PCB 121, and the output pads 125 are electrically connected to the gate pad portion of the thin film transistor array substrate 111.

The gate driving ICs 123 sequentially supply scan signals to the gate lines 120 of the liquid crystal display panel 110.

Meanwhile, data driver ICs 133 are mounted on the data TCP 132 and input pads 134 and output pads 135 electrically connected to the data driver ICs 133 are formed.

The input pads 134 of the data TCP 132 are electrically connected to the data PCB 131, and the output pads 135 are electrically connected to the data pad part of the thin film transistor array substrate 111.

The data driver ICs 133 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 130 of the liquid crystal display panel 110.

Connectors 126 and 136 are formed on the gate PCB 121 and the data PCB 131, respectively, and control signals and driving voltages are provided through a flexible printed circuit (150, hereinafter, FPC) or another cable. Will be supplied.

However, the liquid crystal display configured as described above forms connectors 126 and 136 on the gate PCB 121 and the data PCB 131, respectively, and supplies control signals and driving voltages through the FPC 150 from the outside. The following problems arise because of receiving.

First, as the connectors 126 and 136 are formed on the thin gate PCB 121 and the data PCB 131, the thickness of the liquid crystal display is inevitably increased by the thickness of the connectors 126 and 136, thereby making the liquid crystal display thinner. It becomes a factor to inhibit.

Second, as the FPC 150 for electrically connecting the connectors 126 and 136 is provided, the number of processes for manufacturing the liquid crystal display is increased, which increases the manufacturing cost of the liquid crystal display.

Accordingly, the connectors 126 and 136 are mounted in the outer dummy region of the thin film transistor array substrate 111 to supply gate control signals and gate driving voltages from the data PCB 131 to the gate PCB 121. ) And a line-on-glass type liquid crystal display in which FPCs 150 are not required.

In the line-on-glass type liquid crystal display, first LOG lines are formed in a corner region where one short side and one long side of the thin film transistor array substrate 111 meet to control gate control signals and gate driving voltages supplied from the outside. The data PCB 131 is supplied to the gate PCB 121.

Accordingly, connectors 126 and 136 need not be formed in the gate PCB 121 and the data PCB 131, and a flexible plate cable 150 which electrically connects the connectors 126 and 136 need not be formed.

Meanwhile, in the line-on-glass type liquid crystal display, the gate PCB 121 simply transfers gate control signals and gate driving voltages applied from the data PCB 131 through the first LOG lines to the gate TCP 122. Perform the function of passing.

Therefore, in recent years, the gate signal transmission lines are further configured inside the gate TCPs 122 of the line-on-glass type liquid crystal display, and the gate TCPs 122 are connected to each other on the thin film transistor array substrate 111. By additionally mounting second LOG wires to transmit gate control signals and gate driving voltages applied through the data PCB 131 and the first LOG wires to the gate TCPs 122 through the second LOG wires. A line-on-glass type liquid crystal display in which the gate PCB 121 is removed has also been developed.

The line-on-glass type liquid crystal display as described above is subjected to auto-probe inspection for defect detection after panel fabrication is completed.

In the line-on-glass type liquid crystal display, since the gate driving signals are transmitted through the LOG wirings mounted on the thin film transistor array substrate, the transmission wirings of the test signals for the auto-probe inspection are not separately required.

However, in order to perform the auto-probe inspection of the line-on-glass type liquid crystal display, the pad area to which the LOG lines are exposed and the test pins to which the test signals are applied should be aligned. Since it is mass-produced, the process of aligning each time is cumbersome, and in case of misalignment between the pad area where the LOG lines are exposed and the test pins applying the test signals, a normal panel is recognized as a defective panel and discarded. Is generated.

In particular, in the case of the line-on-glass type liquid crystal display in which the gate PCB is removed, test signals connect the first LOG wires mounted in the corner region on the thin film transistor array substrate and the gate TCPs on the thin film transistor array substrate. The first LOG wirings and the second LOG wirings are formed of a metal material having a high resistance value, and are also very narrow in the thin film transistor array substrate. It is formed to be finely spaced in the space.

Therefore, when the test signals for the auto-probe inspection are transmitted to the gate driving ICs through the first LOG wirings and the second LOG wirings mounted on the thin film transistor array substrate, the first LOG wirings and the second LOG. Due to the high resistance values of the wirings, the test patterns displayed on the image display unit or the image quality characteristics of the test image are poor, so that the reliability of the defect detection is lowered.

Due to the problems described above, the conventional auto-probe inspection method of a line-on-glass type liquid crystal display device has a low resistance test wiring for electrically connecting the test signals to the data PCB and the gate PCB. For example, a method of applying through jumpers has been applied.

That is, in the line-on-glass type liquid crystal display equipped with the gate PCB, test signals for auto-probe inspection are transferred from the data PCB to the gate PCB through the jumpers, and the test signals are transferred to the gate TCPs through the gate PCB. It is applied to gate driver ICs that are individually mounted on.

Meanwhile, the line-on-glass type liquid crystal display in which the gate PCB has been removed further includes a test gate PCB so that test signals for auto-probe inspection are transferred from the data PCB to the test gate PCB through jumpers. The test signals are then applied to gate drive ICs that are individually mounted to gate TCPs via the test gate PCB.

However, the line-on-glass type liquid crystal display in which test signals for the auto-probe inspection are applied through jumpers has the following problems.

That is, after the first LOG wirings or the first LOG wirings and the second LOG wirings are fabricated on the thin film transistor array substrate, an insulating film such as a passivation film is formed on the entire upper surface of the thin film transistor array substrate. The insulating film is selectively etched to expose the pad area of the first LOG wires or the first LOG wires and the second LOG wires. If an etch defect of the insulating film occurs, the first LOG wires or the first LOG wires The pad area of the 1 LOG wires and the second LOG wires is not exposed.

However, in the inspection method of the conventional liquid crystal display panel, since the test signals for the auto-probe inspection are applied through jumpers, the first LOG wirings or the first LOG wirings and the second LOG wirings due to the etching failure of the insulating film. Defective exposure of the pad area cannot be detected.

Therefore, even when the pad area exposure of the first LOG wires or the first LOG wires and the second LOG wires is poor, the liquid crystal display panel is subjected to a subsequent process and commercialized. The device is discarded. This lowers the yield of the product, causing a problem of raising the manufacturing cost of the product according to the waste of material.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to detect defects of a line-on-glass type liquid crystal display panel in which wirings for transmitting gate signals are mounted on the liquid crystal display panel. An object of the present invention is to provide a method of inspecting a liquid crystal display panel, which can improve the reliability thereof.

1 is an exemplary view showing a general liquid crystal display device.

2 is an exemplary view showing a typical line-on-glass type liquid crystal display device.

3 is an exemplary view showing a line-on-glass type liquid crystal display with the gate PCB removed.

4 is an exemplary view illustrating an example of inspecting a liquid crystal display panel illustrated in FIG. 2.

FIG. 5 is an exemplary view illustrating an example of inspecting a liquid crystal display panel illustrated in FIG. 3.

6A to 6D are exemplary views showing a defective state displayed on a screen by inspecting the liquid crystal display panel shown in FIG.

*** Explanation of symbols for main parts of drawing ***

210: liquid crystal display panel 211: thin film transistor array substrate

212: color filter substrate 213: image display unit

220: gate line 221: gate PCB

222: gate TCP 223: gate drive IC

224: input pad 225: output pad

230: data line 231: data PCB

232: data TCP 233: data drive IC

234: input pad 235: output pad

241: LOG wiring 242, 243: gate signal transmission wiring

250: Jumper

The inspection method of the liquid crystal display panel to achieve the object of the present invention is to inspect the line-on-glass type liquid crystal display device in which wirings for transmitting driving signals from the data driver to the gate driver is mounted in the panel. And applying first test signals to the gate driver through test wires electrically connecting the gate driver to the gate driver, and applying at least one second test signal to the gate driver through wires mounted in the panel. .

The inspection method of the liquid crystal display panel according to the present invention as described above will be described in detail with reference to the accompanying drawings.

FIG. 2 is an exemplary view showing a typical line-on-glass type liquid crystal display device, and as shown therein, a liquid crystal display panel 210; A plurality of gate TCPs 222 connected between one short side of the liquid crystal display panel 210 and the gate PCB 221; Gate driver ICs 223 mounted on the gate TCPs 222, respectively; A plurality of data TCPs 232 connected between the long side of one side of the liquid crystal display panel 210 and the data PCB 231; Data driver ICs 233 mounted on the data TCPs 232, respectively.

The liquid crystal display panel 210 is bonded to face the thin film transistor array substrate 211 and the color filter substrate 212 so as to have a constant cell gap, and a liquid crystal layer is formed in the cell gap.

One short side and one long side of the thin film transistor array substrate 211 protrude from the color filter substrate 212, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 211. Also, an image display unit 213 is provided in an area where the thin film transistor array substrate 211 and the color filter substrate 212 face each other.

In the image display unit 213 of the thin film transistor array substrate 211, a plurality of gate lines 220 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 230 are arranged in a vertical direction. It is connected to the data pad part. Accordingly, the gate lines 220 and the data lines 230 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersection thereof.

The image display unit 213 of the color filter substrate 212 includes a color filter of red, green, and blue colors which are separated and applied for each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 211.

The gate pad part and the data pad part provided at one short side and one long side of the thin film transistor array substrate 211 protruding from the color filter substrate 212 are formed to correspond to the image display unit 213.

Accordingly, a corner region where one short side and one long side of the thin film transistor array substrate 211 meet is a dummy region which is not used for any purpose. However, in the line-on-glass type liquid crystal display, the LOG wiring ( 241 are formed to supply gate control signals and gate driving voltages supplied from the outside to the gate PCB 221 from the data PCB 231.

Therefore, the connectors 126 and 136 of FIG. 1 need not be formed in the gate PCB 221 and the data PCB 231, and a flexible plate cable 150 for electrically connecting the connectors 126 and 136 needs to be formed. There is no.

Data driver ICs 233 are mounted on the data TCP 232, and input pads 234 and output pads 235 that are electrically connected to the data driver ICs 233 are formed.

The input pads 234 of the data TCP 232 are electrically connected to the data PCB 231, and the output pads 235 are electrically connected to the data pad portion of the thin film transistor array substrate 211. Accordingly, the data driver ICs 233 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 230 of the liquid crystal display panel 210.

Gate signal transmission lines 243 are further formed on the data TCPs 232, and LOG signal lines 243 formed on the first data TCP 232 are mounted on the thin film transistor array substrate 211. 241 are electrically connected. The gate signal transmission lines 243 formed on the first data TCP 232 transmit gate control signals and gate driving voltages supplied from a timing controller and a power supply unit to the LOG lines 241.

Meanwhile, gate driver ICs 223 are mounted on the gate TCP 222, and input pads 224 and output pads 225 electrically connected to the gate driver ICs 223 are formed.

The input pads 224 of the gate TCP 222 are electrically connected to the gate PCB 221, and the output pads 225 are electrically connected to the gate pad portion of the thin film transistor array substrate 211.

Gate signal transmission lines 242 are further formed on the gate TCPs 222, and LOG signal transmission lines 242 formed on the first gate TCP 222 are mounted on the thin film transistor array substrate 211. And electrically connected to 241. Gate signal transmission lines 242 formed on the first gate TCP 222 are gate control signals and gate driving voltages supplied from the data PCB 231 through the gate signal transmission lines 243 and the LOG lines 241. Are transferred to the gate PCB 221.

Signal lines and power lines are formed on the gate PCB 221 to transmit the gate control signals and gate driving voltages to the input pads 224 of the gate TCP 222.

Accordingly, the gate driving ICs 223 receive the gate control signals and the gate driving voltages from the input pads 224 to receive the scan signals, that is, the gate high voltage signal Vgh and the gate low voltage signal Vgl, and the gate line 220. ) Sequentially.

3 is an exemplary view showing a line-on-glass type liquid crystal display device in which a gate PCB is removed, as shown therein; A plurality of gate TCPs 322 connected to one side of the liquid crystal display panel 310; Gate driver ICs 323 mounted on the gate TCPs 322, respectively; A plurality of data TCPs 332 connected between one long side of the liquid crystal display panel 310 and a data PCB 331; Data driver ICs 333 mounted to the data TCPs 332, respectively.

In the liquid crystal display panel 310, the thin film transistor array substrate 311 and the color filter substrate 312 are bonded to each other with a predetermined cell gap, and a liquid crystal layer is formed at the cell gap.

One short side and one long side of the thin film transistor array substrate 311 protrude from the color filter substrate 312, and a gate pad portion and a data pad portion are provided in the protruding region of the thin film transistor array substrate 311. Also, an image display unit 313 is provided in an area where the thin film transistor array substrate 311 and the color filter substrate 312 face each other.

In the image display unit 313 of the thin film transistor array substrate 311, a plurality of gate lines 320 are arranged in a horizontal direction and connected to the gate pad part, and a plurality of data lines 330 are arranged in a vertical direction. It is connected to the data pad part. Therefore, the gate lines 320 and the data lines 330 cross each other, and pixels including the thin film transistor and the pixel electrode are formed at the intersections thereof.

The image display unit 313 of the color filter substrate 312 includes a color filter of red, green, and blue colors separated and applied to each pixel by a black matrix; A common electrode for forming an electric field in the liquid crystal layer is provided together with the pixel electrode provided in the thin film transistor array substrate 311.

On the other hand, first LOG wiring 341A is formed in an edge region where one short side and one long side of the thin film transistor array substrate 311 meet, and control signals and driving voltages supplied from the outside are transferred from the data PCB 331. Second LOG wiring 341B is formed on one side of the thin film transistor array substrate 311 to which the first gate driver IC 323 is supplied through the first gate TCP 322, and the gate TCPs 322 are spaced apart from each other. The control signals and driving voltages supplied to the first gate TCP 322 are supplied to the gate driving ICs 323 through the gate TCP 322.

Data driver ICs 333 are mounted on the data TCPs 332, and input pads 334 and output pads 335 electrically connected to the data driver ICs 333 are formed.

The input pads 334 of the data TCPs 332 are electrically connected to the data PCB 331, and the output pads 335 are electrically connected to the data pad portion of the thin film transistor array substrate 311. Accordingly, the data driver ICs 333 convert image information, which is a digital signal, into an analog signal and supply the converted data to the data lines 330 of the liquid crystal display panel 310.

Gate signal transmission lines 343 are additionally formed in the data TCPs 332, and the first LOG in which the gate signal transmission lines 343 formed in the first data TCP 332 are mounted on the thin film transistor array substrate 311. It is electrically connected to the wirings 341. The gate signal transmission lines 343 formed on the first data TCP 332 transmit gate control signals and gate driving voltages supplied from a timing controller and a power supply unit to the first LOG lines 341.

On the other hand, gate driver ICs 323 are mounted on the gate TCP 322, and gate signal transmission wirings 342 and output pads 325 electrically connected to the gate driver ICs 323 are formed.

The gate signal transmission lines 342 formed on the first gate TCP 322 supply gate control signals and gate driving voltages supplied from the first LOG lines 341A to the first gate driving IC 323. In this case, the gate control signals and the gate driving voltages are provided to the respective gate TCPs 322 through the second LOG wires 341B mounted on the thin film transistor array substrate 311 in the space where the respective gate TCPs 322 are spaced apart. It is transmitted to the mounted gate signal transmission lines 342 and supplied to the gate driving ICs 323.

The output pads 325 of the gate TCPs 322 are electrically connected to the gate pad part of the thin film transistor array substrate 311.

Accordingly, the gate driving ICs 323 receive gate control signals and gate driving voltages from the gate signal transmission lines 342 to receive a scan signal, that is, a gate high voltage signal Vgh and a gate low voltage signal Vgl. Sequentially supply to (320).

The line-on-glass type liquid crystal display as described above is subjected to auto-probe inspection for defect detection after panel fabrication is completed.

As described above, in the line-on-glass type liquid crystal display, since the gate driving signals are transmitted through LOG wirings mounted on the thin film transistor array substrate, transmission wirings of test signals for auto-probe inspection are not required separately.

However, in order to perform auto-probe inspection of a line-on-glass type liquid crystal display, it is necessary to align the pad area where the LOG lines are exposed and the test pins to which the test signals are applied. If the alignment process is cumbersome and misalignment occurs between the pad area where the LOG lines are exposed and the test pins applying the test signals, the normal panel is recognized as a defective panel and discarded.

In particular, in the case of the line-on-glass type liquid crystal display in which the gate PCB is removed, the test signals are connected to the first LOG wires mounted in the corner region on the thin film transistor array substrate and the gate TCPs on the thin film transistor array substrate. The second LOG wires are transferred to the gate driving ICs through the second LOG wires mounted on the wires, wherein the first LOG wires and the second LOG wires are formed of a metal material having a high resistance value, and also have a very limited narrow space of the thin film transistor array substrate. It is formed to be spaced apart finely. Therefore, when the test signals for auto-probe inspection are transmitted to the gate driving ICs through the first LOG wirings and the second LOG wirings mounted on the thin film transistor array substrate, the first LOG wirings and the second LOG wirings Due to the high resistance value, the test patterns displayed on the image display unit or the image quality characteristics of the test image are poor, so that the reliability of the defect detection is lowered.

Therefore, the auto-probe inspection method of the conventional line-on-glass type liquid crystal display is used for a test with low resistance that separates test signals from being applied through LOG wirings and electrically connects the data PCB and the gate PCB. A method of applying via wirings (e.g. jumpers) has been applied.

Looking again at the problem of the auto-probe inspection method of the conventional line-on-glass type liquid crystal display as described above, since the test signals for auto-probe inspection are applied through jumpers, LOG caused by poor etching of the insulating film Defective exposure of the pad area of the wirings cannot be detected.

Accordingly, in the method of inspecting a liquid crystal display panel according to the present invention, the test signals for auto-probe inspection are divided into first test signals and second test signals so that the first test signals electrically connect the data PCB and the gate PCB. By applying a method of transmitting the test wires (eg, jumpers) having a low resistance value to be connected, and transmitting the second test signals through the LOG wires mounted on the thin film transistor array substrate, Defective exposure of the pad area of the LOG lines due to the etching failure can be detected.

The inspection method of the liquid crystal display panel according to the present invention as described above will be described in more detail with reference to the accompanying drawings.

First, referring to FIG. 4, in the line-on-glass type liquid crystal display shown in FIG. 2, the first test signals TEST1 for auto-probe inspection may be transferred from the data PCB 231 through jumpers 250. The second test signals TEST2 are transmitted from the data PCB 231 to the gate PCB 221 through the LOG wirings 241, and the first test signals TEST1 and the first test signals TEST1 are transmitted to the gate PCB 221. The two test signals TEST2 are applied to the gate driving ICs 223 through the gate PCB 221.

The first test signal TEST1 includes a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground signal GND, a power supply voltage signal Vdd, and a gate start pulse GSP. And a gate enable signal GOE.

The second test signals TEST2 transmitted from the data PCB 231 to the gate PCB 221 through the LOG wirings 241 include at least a gate shift clock GSC, and the gate high voltage signal Vgh. The first test signal TEST1 among the gate low voltage signal Vgl, the common voltage signal Vcom, the ground signal GND, the power supply voltage signal Vdd, the gate start pulse GSP, and the gate enable signal GOE. Signals not included in the) may be included.

The gate shift clock GSC serves as a kind of a carry signal to sequentially drive the gate driving ICs 223.

As described above, in the method of inspecting the liquid crystal display panel according to the present invention, the gate shift clock GSC is transmitted from the data PCB 231 to the gate PCB 221 through the LOG wirings 241 as the second test signal TEST2. do.

However, when the pad region of the LOG wirings 241 is not exposed due to the poor etching of the insulating layer during the panel fabrication process, the pad region of the LOG wirings 241 and the test pins do not come into contact with each other. Are not transmitted to the gate driver ICs 223.

Accordingly, since the gate driving ICs 223 are not driven and no test patterns or test images are displayed on the image display unit, it is possible to detect a poor pad area exposure of the LOG lines 241.

On the other hand, referring to Figure 5, the line-on-glass type liquid crystal display shown in Figure 3 is further provided with a test gate PCB 321 to the first test signal (TEST1) for the auto-probe inspection The test gate PCB 321 is transmitted from the data PCB 331 through the jumpers 350 to the test gate PCB 321, and the second test signals TEST2 are transmitted from the data PCB 331 through the first LOG wires 341A. 321).

The first test signals TEST1 are applied to the gate driving ICs 323 through the test gate PCB 321, and the second test signals TEST2 are connected through the second LOG wires 341B. It is transmitted to the gate TCPs 322 and supplied to the gate driving ICs 323.

The first test signal TEST1 includes a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground signal GND, a power supply voltage signal Vdd, and a gate start pulse GSP. And a gate enable signal GOE.

The second test signal TEST2 is supplied from the data PCB 331 to the gate driving ICs 323 of the gate TCPs 322 through the first LOG wires 341A and the second LOG wires 341B. ) Includes at least a gate shift clock GSC, and includes the gate high voltage signal Vgh, the gate low voltage signal Vgl, the common voltage signal Vcom, the ground signal GND, the power voltage signal Vdd, and the gate start. Signals not included in the first test signals TEST1 may be included in the pulse GSP and the gate enable signal GOE.

The gate shift clock GSC serves as a kind of carry signal to sequentially drive the gate driving ICs 323.

As described above, in the method of inspecting the liquid crystal display panel according to the present invention, the gate shift clock GSC is the second test signal TEST2 through the first LOG wirings 341A and the second LOG wirings 341B. 331 is supplied to the gate driving ICs 323 of the respective gate TCPs 322.

However, when the pad areas of the first LOG wires 341A and the second LOG wires 341B are not exposed due to the poor etching of the insulating layer during the panel manufacturing process, the first LOG wires 341A and the second LOG wires are not exposed. Since the pad region of the 341B and the test pins do not come into contact with each other, the gate shift clock GSC is not transmitted to the gate driving ICs 323.

Therefore, when the pad area exposure of the first LOG wires 341A occurs, not all the gate driving ICs 323 are driven, so that the test patterns or the test image are displayed on the image display unit 313 as shown in FIG. 6A. Is not displayed.

When the pad area exposure of the second LOG lines 341B is poor, the gate shift clock GSC is sequentially applied to the gate TCPs 322 through the second LOG lines 341B. The test patterns or the test images are partially displayed on the image display unit 313 as shown in Figs. 6B to 6D depending on the position where the pad area defective exposure of the two LOG wirings 341B is generated.

Therefore, the defective exposure of the pad region of the first LOG wirings 341A and the second LOG wirings 341B can be detected through the test patterns or the test image of the image display unit.

As described above, the test method of the liquid crystal display panel according to the present invention divides the test signals for auto-probe inspection into first test signals and second test signals so that the first test signals correspond to the data PCB and the gate PCB. By applying a method of transmitting the test wires (eg, jumpers) having low resistance values electrically connected to each other, and transmitting the second test signals through LOG wires mounted on the thin film transistor array substrate, Defective exposure of the pad region of the LOG lines due to the poor etching of the insulating layer can be detected.

Therefore, when the pad area exposure of the LOG lines is defective, the subsequent process proceeds to commercialization as in the prior art, and defects are detected in the final inspection to prevent the liquid crystal display device from being discarded, thereby improving product yield. There is an effect that can be, there is an effect that can reduce the manufacturing cost of the product by reducing the material cost.

Claims (10)

In the inspection of a line-on-glass type liquid crystal display device in which wirings for transmitting driving signals from a data driver to a gate driver are mounted in a panel, a first test is performed through test wires electrically connecting the data driver and the gate driver. And applying signals to a gate driver, and applying at least one second test signal to the gate driver through wirings mounted in the panel. The gate test circuit of claim 1, wherein the first test signals include a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground signal GND, a power supply voltage signal Vdd, and a gate start pulse. At least one of a GSP and a gate enable signal GOE. The method of claim 1, wherein the second test signal is a gate shift clock (GSC). The method of claim 1, wherein the first test signals are applied to a gate driver through signal lines formed on a gate printed circuit board. The method of claim 1, wherein the second test signal is applied to the gate driver through signal lines formed on the gate printed circuit board. Line-on-glass type liquid crystal display having first wirings for transmitting driving signals from the data driver to the first driving block of the gate driver and second wirings for transmitting driving signals between the driving blocks of the gate driver. In testing an apparatus, first test signals are applied to driving blocks of a gate driver through test wires electrically connecting the data driver and the gate driver, and at least one second test signal through the first wirings. Is applied to the first driving block of the gate driver, and the second test signal is transmitted between the driving blocks of the gate driver through the second wirings. The method of claim 6, wherein the first wires are mounted at edges of the panel. The method of claim 6, wherein the second wires are mounted on one side of the panel corresponding to the gate driver. 7. The method of claim 6, wherein the second test signal is a gate shift clock (GSC). 7. The method of claim 6, wherein the first test signals are applied to driving blocks of the gate driver through signal lines formed on the gate printed circuit board.