KR20050000990A - Bidirectional bus repeater in semiconductor memory device - Google Patents

Abstract

PURPOSE: A bidirectional bus repeater in semiconductor memory device is provided to reduce layout area by using only two driver transistors instead of four transistors to realize driver. CONSTITUTION: A bidirectional bus repeater in semiconductor memory device comprises the first relay part(30) for relaying signals from B to A, and the second relay part(40) for relaying signals from A to B. The first relay part(30) includes a NAND gate(nand1) for receiving a signal from B and a control signal(hitb); a NOR gate(nor1) for receiving the signal from B and a control signal(hit); a driver consisting of Pull-up PMOS transistor(p1) and Pull-down NMOS transistor(n1). Wherein the NAND gate(nand1) and the NOR gate(nor1) constitute the control logic. And the second relay part(40) includes a NAND gate(nand2) for receiving a signal from A and a control signal(hit); a NOR gate(nor2) for receiving the signal from A and a control signal(hitb); a driver consisting of Pull-up PMOS transistor(p2) and Pull-down NMOS transistor(n2). Wherein the NAND gate(nand2) and the NOR gate(nor2) constitute the control logic.

Description

Bidirectional bus repeaters for semiconductor memory devices {BIDIRECTIONAL BUS REPEATER IN SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuit design techniques, and more particularly to a bidirectional bus repeater for semiconductor memory devices.

In a semiconductor memory device, a global input / output bus (hereinafter referred to as a gio bus) is a data transmission line for transferring data between an input / output pin and a memory core during a read or write operation.

If the gio bus is long, the load is large, and thus the swing of a signal on the gio bus is increased during read or write operation, which causes a deterioration of the operating margin. In this case, a repeater is placed in the middle of the gio bus to distribute the load to improve the operation speed. Depending on which bank to read or write, it is necessary to transfer data in only one direction in a bidirectional gio structure connected to the repeater.

1 is a circuit diagram of a gio bus repeater according to the prior art.

Referring to FIG. 1, a gio bus repeater according to the related art includes a first relay unit 10 for relaying a signal from a B stage to an A stage, and a second relay unit for relaying a signal from an A stage to a B stage ( 20).

Here, the first relay unit 10 includes an inverter INV10 for inputting a signal loaded at the B stage, a PMOS transistor M1 connected to a supply power supply Vdd, and having an output of the inverter INV10 as a gate input. , A PMOS transistor M2 connected between the PMOS transistor M1 and the A stage and having a control signal hit as a gate input, and an NMOS transistor connected to a ground power supply Vss and having an output of the inverter INV10 as a gate input. And an NMOS transistor M3 connected between the MMOS transistor M4 and the A stage and whose control signal hitb is a gate input. The MOS transistors M1 to M4 constitute a driver.

The second relay unit 20 includes an inverter INV20 for inputting a signal loaded at the A stage, a PMOS transistor M5 connected to a supply power supply Vdd, and having an output of the inverter INV20 as a gate input. , A PMOS transistor M6 connected between the PMOS transistor M5 and the B stage, the control signal hitb being the gate input, and an NMOS transistor connected to the ground power supply Vss and the output of the inverter INV20 being the gate input. And an NMOS transistor M7, which is connected between the MMOS transistor M8 and the B stage, and whose control signal hit is a gate input. The MOS transistors M5 to M8 constitute a driver.

The control signals hit and hitb are signals of opposite phase. When the control signal hit is logic level high (hitb is logic level low), the data loaded on the gio bus is relayed from the A stage to the B stage, and the control signal hit is a logic level low ( If hitb is a logic level high), the data carried on the gio bus is relayed from the B stage to the A stage.

In order to drive a long gio bus, the transistor constituting the repeater driver must be large, and since the gio bus repeater must be disposed in each gio line, the layout area occupied by the gio bus repeater itself is not small. However, according to the related art, since the driver of the gio bus repeater is implemented by four transistors connected in series, there is a problem of occupying a large layout area.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a bidirectional bus repeater of a semiconductor memory device capable of reducing its own layout area.

1 is a circuit diagram of a gio bus repeater according to the prior art.

2 is a circuit diagram of a gio bus repeater in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30: first relay unit

40: second relay unit

hit, hitb: control signal

According to an aspect of the present invention for achieving the above technical problem, a first control logic for selectively transmitting a signal carried on one end of the global input / output bus in response to the relay direction control signal; A first driver comprising a first pull-up transistor and a first pull-down transistor for driving the other end of the global input / output bus in response to an output signal of the first control logic; A second control logic for selectively transferring a signal carried on the other end of the global input / output bus in response to the relay direction control signal; And a second driver including a second pull-up transistor and a second pull-down transistor for driving one end of the global input / output bus in response to an output signal of the second control logic. Is provided.

The present invention proposes a method of implementing a driver using only two driver transistors required for pull-up / pull-down in a bidirectional bus repeater and controlling the relay direction of data using control logic in front of the driver.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2 is a circuit diagram of a gio bus repeater according to an embodiment of the present invention.

Referring to FIG. 2, the gio bus repeater according to the present embodiment includes a first relay unit 30 for relaying signals from the B stage to the A stage, and a second relay unit for relaying signals from the A stage to the B stage. It consists of 40.

Here, the first relay unit 30 includes a NAND gate nand1 that inputs a signal loaded on the B stage and a control signal hitb, a NOR gate nor1 that inputs a signal loaded on the B stage and a control signal hit, and A driver comprising a pull-up PMOS transistor p1 and a pull-down NMOS transistor n1 is provided. The NAND gate nand1 and the noah gate nor1 form a control logic.

The second relay unit 40 includes a NAND gate nand2 for inputting the signal and control signal hit on stage A, a noah gate nor2 for inputting the signal and control signal hitb on stage A, and A driver comprising a pull-up PMOS transistor p2 and a pull-down NMOS transistor n2 is provided. The NAND gate nand2 and the noah gate nor2 form a control logic.

As described above, the control signals hit and hitb are signals having opposite phases to each other. First, if the control signal hit is logic level high (hitb is logic level low), the NAND gate nand1 and the noah gate nor1 of the first relay unit 30 are disabled, and the signal loaded at the B stage is blocked. The NAND gate nand1 and the NOA gate nor1 of the second relay unit 40 are enabled to invert the signal loaded at the A stage, respectively, to thereby open the B stage through the pull-up PMOS transistor p2 or the pull-down NMOS transistor n2. It will drive up or pull down.

On the other hand, when the control signal hit is at a logic level low (hitb is at a logic level high), the NAND gate nand1 and the noah gate nor1 of the first relay unit 30 are enabled, and the signal loaded on the B stage is transferred to the B stage. Relay the carried signal to the A stage.

According to the present invention described above, the number of driver transistors requiring a large size can be minimized by providing the control logic controlled by the control signals hit and hitb. Therefore, the layout area of the gio bus repeater itself can be greatly reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the case where the control logic is implemented by using the NAND gate and the NOR gate has been described as an example. However, the present invention is also applicable to the case where the logic is implemented using another logic gate.

In addition, in the above-described embodiment, the case where the repeater is applied to the gio bus has been described as an example, but the present invention is applied to the case where the repeater is applied to a bidirectional bus other than the gio bus.

The present invention described above has the effect of reducing the layout area of the bidirectional bus repeater itself, thereby contributing to reducing the chip size of the semiconductor memory device.

Claims (5)

A first control logic for selectively transferring a signal loaded at one end of the global input / output bus in response to the relay direction control signal; A first driver comprising a first pull-up transistor and a first pull-down transistor for driving the other end of the global input / output bus in response to an output signal of the first control logic; A second control logic for selectively transferring a signal carried on the other end of the global input / output bus in response to the relay direction control signal; And A second driver including a second pull-up transistor and a second pull-down transistor for driving one end of the global input / output bus in response to an output signal of the second control logic; The bidirectional bus repeater of the semiconductor memory device having a. The method of claim 1, The first control logic is, A first NAND gate configured to input a signal loaded at one end of the global input / output bus and a sub relay direction control signal; And a first NOR gate for inputting a signal loaded at one end of the global input / output bus and a positive relay direction control signal. The method of claim 2, The second control logic is, A second NAND gate configured to receive a signal loaded at the other end of the global input / output bus and the positive relay direction control signal; And a second NOR gate configured to receive a signal loaded at the other end of the global input / output bus and the sub relay direction control signal. The method of claim 3, And the first pull-up transistor is an output of the first NAND gate as a gate input, and the first pull-down transistor is an output of the first NOR gate as a gate input. The method of claim 4, wherein And wherein the second pull-up transistor is an output of the second NAND gate as a gate input, and the second pull-down transistor is an output of the second NOR gate as a gate input.