KR20040106659A - Nonvolatile ferroelectric memory device - Google Patents

Abstract

PURPOSE: A ferroelectric memory device is provided to increase the lifetime and the reliability of the products by previously preventing the deterioration of the reference cells. CONSTITUTION: A ferroelectric memory device includes a memory cell(520) and a reference cell(540). The memory cell is provided with a first transistor and a first ferroelectric capacitor. The source-drain path of the first transistor is connected between the first bit line and the first node. The first ferroelectric capacitor is connected between the first node and the first plate line. The reference cell is provided with a second transistor and a second ferroelectric capacitor. The source-drain path of the second transistor is connected to the second bit line and the second node and the gate of the second transistor is connected to the word line. And, the second ferroelectric capacitor is connected between the second node and the second plate line.

Description

Ferroelectric memory device {NONVOLATILE FERROELECTRIC MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric random access memory (FeRAM), which is one of semiconductor devices, and more particularly to a method of generating a reference voltage in a ferroelectric memory device.

As is well known, a nonvolatile ferroelectric memory device, that is, FeRAM, has attracted attention as a next-generation memory device because of its data processing speed as high as DRAM (Dynamic Random Access Memory) and data retention even when the power supply is turned off. .

FeRAM is a memory device having a cell structure similar to DRAM, that is, a unit cell having a 1T / 1C structure composed of one switching element (transistor) and one capacitor. Polarization is used. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

1 is a characteristic diagram showing a hysteresis loop of a conventional ferroelectric.

Referring to FIG. 1, it can be seen that the polarization induced by the electric field does not disappear due to the presence of residual polarization (or spontaneous polarization) even when the electric field is removed, and maintains a certain amount (d state, a state). In the nonvolatile ferroelectric memory cell, the switching charge Q1 and the non-switching charge Q0 correspond to logic '1' and logic '0', respectively, to be applied as memory devices.

2 is a unit cell circuit diagram of a conventional ferroelectric memory.

Referring to FIG. 2, a unit cell includes a word line WL and a plate line PL formed in a row direction, a bit line BL formed in a direction crossing the word line WL and a plate line PL, and a gate is formed in the word line WL. And a switching transistor TR connected with the drain connected to the bit line BL, and a ferroelectric capacitor FC connected between the source of the transistor TR and the plate line PL. A plurality of such unit cells are arranged to form a cell array unit.

On the other hand, a reference voltage is required to drive the ferroelectric memory. For example, in order to read the data stored in the unit cell, since the data voltage transferred to the positive bit line BL is minute, it must be compared and amplified with the reference voltage transferred to the subbit line / BL.

3A and 3B are circuit diagrams for explaining a principle of generating a reference voltage according to the related art, and show a reference cell unit 340, a memory cell unit 320, and a sense amplifier unit 360 together.

Referring to FIG. 3A, a reference cell uses two cells having ferroelectric capacitors of substantially the same size as the memory cell (represented by x1 in the drawing), and data '1' of one cell and data ' The average signal between 0 'is transmitted to the bit lines BL0 and BL1 so that the signal is used as a reference signal. At this time, the reference cell and the memory cell have the same operating power using the same supply power supply Vdd. In the figure, RWL represents a word line of a reference cell and RPL represents a plate line of a reference cell, respectively.

Referring to FIG. 3B, a reference cell is a method of applying a ferroelectric capacitor having a larger size (x3) than a ferroelectric capacitor of a memory cell and generating a non-switching charge thereof as a reference voltage. X3 in the figure means that the ferroelectric capacitor of the reference cell is three times larger than the ferroelectric capacitor of the memory cell, and the actual exact size should be determined in consideration of the characteristics of the ferroelectric capacitor and the cell array structure. At this time, the reference cell and the memory cell are operated at the same power supply voltage.

However, since the reference voltage generation method of the two structures has a structure in which the reference cell operates whenever a large number of memory cells connected to the same bit line operate, the reference cell is more fatigued than the memory cell. And more susceptible to dielectric breakdown.

On the other hand, it is possible to generate a reference voltage by using a reference voltage generator implemented in a CMOS circuit without using a ferroelectric, but at this time, it is a problem to change characteristics due to temperature change and process change, thereby securing an operating margin of the device. You will have problems with

The present invention has been proposed in accordance with the above-described requirements, and an object thereof is to provide a FeRAM for improving fatigue and dielectric breakdown of ferroelectric capacitors in a reference cell.

1 is a characteristic diagram showing a hysteresis loop of a conventional ferroelectric.

2 is a unit cell circuit diagram of a conventional ferroelectric memory.

3A and 3B are circuit diagrams illustrating a reference voltage generation principle of a ferroelectric memory device according to the related art.

4 is a graph showing fatigue characteristics of operating voltages of ferroelectric capacitors.

5 is a cross-sectional view illustrating a principle of generating a FeRAM reference voltage according to a first embodiment of the present invention.

6 is a cross-sectional view illustrating a principle of generating a FeRAM reference voltage according to a second embodiment of the present invention.

7 is a circuit diagram showing a cell array in FeRAM according to the present invention.

* Explanation of symbols for main parts of the drawings

520: memory cell unit

540: reference cell portion

560: sense amplifier unit

According to an embodiment of the present invention, a ferroelectric memory device includes a first transistor connected to a source-drain path between a first bit line and a first node, and a first word line connected to a gate. A memory cell comprising a first ferroelectric capacitor connected between one play line; A second transistor having a source-drain path connected between a second bit line and a second node and a second word line connected to a gate, and at least two second ferroelectrics connected in series between the second node and the second plate line A reference cell composed of a capacitor; And a sense amplifier connected to the first bit line and the second bit line to sense and amplify a voltage corresponding to the data of the first bit line by using the signal of the second bit line as a reference voltage signal. It is done.

In the present invention, it is preferable that the operating voltage of the reference cell and the operating voltage of the memory cell are substantially the same, and the reference cell generates the reference voltage using the switching or unswitching charge of the second ferroelectric capacitor.

In the present invention, the reference cell includes two second ferroelectric capacitors connected in series. In this case, when the reference voltage is generated using switching charges of the ferroelectric capacitor, the second ferroelectric capacitors each have a size of the first ferroelectric capacitor. It is preferably about 1.5 times the size of.

In addition, in the present invention, the reference cell includes two second ferroelectric capacitors connected in series. In this case, when the reference voltage is generated using the non-switching charge of the ferroelectric capacitor, the second ferroelectric capacitors each have a size of the second ferroelectric capacitor. It is preferably about six times the size of the ferroelectric capacitor.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a graph illustrating fatigue characteristics of ferroelectric capacitors according to operating voltages.

Referring to FIG. 4, it can be seen that as the supply voltage is lowered, the fatigue characteristics of the ferroelectric capacitor are greatly improved. That is, when the operating voltage is 7V and 5V, the switching charge Qsw is rapidly decreased when the switching operation is performed more than 10 ⁸ times, while the switching charge is not reduced even when the switching operation is performed more than 10 ⁸ times at the 3V operating voltage. It can be seen that.

As a result, if the operating voltage of the reference cell is smaller than the operating voltage of the memory cell, even if the reference cell is operated more frequently than the memory cell, the fatigue characteristics are greatly improved, thereby preventing the life of the FeRAM device due to deterioration of the reference cell.

Therefore, in the present invention, a plurality of ferroelectric capacitors of a reference cell are connected in series. In this way, when a plurality of ferroelectric capacitors of the reference cell are connected in series, while the same operating voltage is used for the reference cell and the memory cell, the operating voltage applied to each ferroelectric capacitor of the reference cell is substantially higher than the operating voltage applied to the ferroelectric capacitor of the memory cell. It becomes small. As a result, the fatigue characteristics of the ferroelectric capacitors of the reference cell can be improved compared to the prior art (a configuration in which one ferroelectric capacitor is used in the reference cell).

(First embodiment)

FIG. 5 is a circuit diagram illustrating a reference voltage generation principle according to a first embodiment of the present invention, in which a reference voltage is generated using switching charges of a ferroelectric capacitor.

Referring to FIG. 5, a memory cell unit 520 storing data, a reference cell unit 540 providing a reference voltage, a voltage level corresponding to data of the memory cell unit, and a reference voltage level provided from the reference cell unit are described. A sense amplifier unit 560 for detecting and amplifying data is included. The reference cell and the memory cell are driven at substantially the same operating voltage.

The unit memory cell of the memory cell unit 520 includes a word line WL and a plate line PL formed in a row direction, a bit line BL0 formed in a direction crossing the word line WL and a plate line PL, and a gate of the word line WL. A switching transistor TR coupled to the bit line BL0 and a ferroelectric capacitor FC coupled between the source of the transistor TR and the plateline PL.

Such unit memory cells are arranged in a matrix in a row and column direction so that a plurality of unit memory cells are provided. The array of memory cells will be described again later with reference to FIG. 7.

The unit reference cell of the reference cell unit 540 includes a reference word line RWL and a reference plate line RPL formed in a row direction, a bit line / BL0 formed in a direction crossing the reference word line RWL and a reference plate line RPL; A switching transistor RTR having a gate connected to the reference word line RWL and a drain connected to the bit line / BL0, and ferroelectric capacitors RFC1 and RFC2 connected in series between the source of the transistor RTR and the reference plate RPL.

The reference cell unit 540 stores data corresponding to logic '1'-that is, uses switching charges of ferroelectric capacitors RFC1 and RFC2 (data '1' signal = V _{BL'1 '} )-, data' 1 ' In order to obtain the reference voltage corresponding to the intermediate value between the data and '0', it is preferable that each size of the ferroelectric capacitors RFC1 and RFC2 of the reference cell is about 1.5 times larger (x1.5) than the size of the ferroelectric capacitor FC of the memory cell. Do. The actual exact size should be determined in consideration of the characteristics of the ferroelectric capacitor and the cell array structure.

Since the reference cell has two ferroelectric capacitors RFC1 and RFC2 connected in series, the capacitance is halved, resulting in a reference voltage of V _{BL'1 '} / 2 at the bit line.

In the present invention, since the two ferroelectric capacitors RFC1 and RFC2 are connected in series to the reference cell, the voltage to which one of the ferroelectric capacitors of the reference cell is applied is halved compared with the ferroelectric capacitor FC of the memory cell. Therefore, as described above with reference to FIG. 4, even though the reference cell operates more frequently than the memory cell, the fatigue characteristics are greatly improved compared to the conventional technology (the reference cell having one ferroelectric capacitor), and thus the life of the FeRAM device due to deterioration of the reference cell. The degradation can be suppressed and / or prevented. In addition, dielectric breakdown is also improved at low operating voltages, thereby suppressing and / or preventing the life of FeRAM devices due to reference cells.

Second Embodiment

FIG. 6 is a circuit diagram illustrating a reference voltage generation principle according to a second embodiment of the present invention, and illustrates an example of generating a reference voltage using a non-switching charge of a ferroelectric capacitor of a reference cell.

6, a memory cell unit 620 storing data, a reference cell unit 640 providing a reference voltage, a voltage level corresponding to data of a memory cell, and a reference voltage level provided from the reference cell. A sense amplifier unit 660 for detecting and amplifying data is included. The reference cell and the memory cell are driven at substantially the same operating voltage.

The configuration of the memory cell portion 620 is substantially the same as in the first embodiment.

The unit reference cell of the reference cell unit 640 includes a reference word line RWL and a reference plate line RPL formed in a row direction, a bit line / BL0 formed in a direction crossing the reference word line RWL and a reference plate line RPL; A switching transistor RTR having a gate connected to the reference word line RWL and a drain connected to the bit line / BL0, and ferroelectric capacitors RFC1 and RFC2 connected in series between the source of the transistor RTR and the reference plate RPL.

The reference cell unit 640 stores data corresponding to the logic '0'-that is, uses the non-switching charges of the ferroelectric capacitors RFC1 and RFC2 (data '0' signal = V _{BL'0 '} )-, data' 1 ' In order to obtain a reference voltage corresponding to an intermediate value between 'and data' 0 ', it is preferable that each size of the ferroelectric capacitors RFC1 and RFC2 of the reference cell is about 6 times larger than the size of the ferroelectric capacitor FC of the memory cell. . The actual exact size should be determined in consideration of the characteristics of the ferroelectric capacitor and the cell array structure.

Similarly, in the second embodiment of the present invention, since two ferroelectric capacitors RFC1 and RFC2 are connected in series to the reference cell, the voltage applied to one of the ferroelectric capacitors of the reference cell is halved compared to the ferroelectric capacitor FC of the memory cell. Therefore, as described above with reference to FIG. 4, even though the reference cell operates more frequently than the memory cell, the fatigue characteristics are greatly improved compared to the prior art (FIG. 3b, the reference cell having one ferroelectric capacitor), and thus the FeRAM is caused by deterioration of the reference cell. The deterioration of the lifetime of the device can be suppressed and / or prevented. In addition, dielectric breakdown is also improved at low operating voltages, thereby suppressing and / or preventing the life of FeRAM devices due to reference cells.

7 is a circuit diagram illustrating a cell array in FeRAM according to the first and second embodiments of the present invention.

Referring to FIG. 7, the upper memory cell unit 730A and the lower memory cell unit 730B are disposed with the sense amplifier unit 750 interposed therebetween, and the upper reference cell unit 710A is disposed on the upper end of the upper memory cell unit 730A. The lower reference cell unit 710B is disposed at the lower end of the lower memory cell unit 730B.

When sensing and amplifying cell data from one memory cell of the upper memory cell unit 730A, a reference voltage is generated from the reference cell of the lower reference cell unit 710B to read data through the sense amplifier unit 750. On the contrary, when sensing and amplifying the cell data of the lower memory cell unit 730B, the sense amplifier unit 750 receives the reference voltage from the upper reference cell unit 710A.

On the other hand, in order to store data '1' or '0' in the reference cell, a switching transistor for applying a voltage to both ends (the plate line and the storage node) of the ferroelectric capacitor connected in series may be separately used.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention brings the following effects.

First, in a method of generating a reference voltage using a reference cell having a ferroelectric capacitor, it is possible to prevent deterioration of the reference cell to increase the life of the product and to increase the reliability.

Second, since the reference cell and the memory cell use the same ferroelectric material than the conventional technology using a reference voltage generator implemented by a CMOS circuit without using a ferroelectric, the characteristics of the device change due to temperature and process changes. Easy to secure margin

Claims (6)

A memory comprising a first transistor having a source-drain path connected between a first bit line and a first node and a first word line connected to a gate, and a first ferroelectric capacitor connected between the first node and the first plate line. Cell; A second transistor having a source-drain path connected between a second bit line and a second node and a second word line connected to a gate, and at least two second ferroelectrics connected in series between the second node and the second plate line A reference cell composed of a capacitor; And A sense amplifier connected to the first bit line and the second bit line to sense and amplify a voltage corresponding to the data of the first bit line by using the signal of the second bit line as a reference voltage signal. A ferroelectric memory device comprising a. The method of claim 1, And an operating voltage of the reference cell and an operating voltage of the memory cell are substantially the same. The method of claim 1, And generating the reference voltage by using the switching charges of the respective second ferroelectric capacitors. The method of claim 3, And the reference cell includes two second ferroelectric capacitors connected in series, each of the second ferroelectric capacitors having a size of about 1.5 times the size of the first ferroelectric capacitor. The method of claim 1, And generating the reference voltage by using the non-switching charge of each of the second ferroelectric capacitors. The method of claim 5, And the reference cell includes two second ferroelectric capacitors connected in series, and each of the second ferroelectric capacitors is about six times the size of the first ferroelectric capacitor.