KR20040103042A - Clock recovery circuit using up/down signal generator of being insensible to delay in a loop - Google Patents

Abstract

PURPOSE: A clock recovery circuit using an up/down generator robust to inter-loop delays is provided to reduce a phase noise without substantially affecting on a phase tracking characteristic. CONSTITUTION: A clock recovery circuit includes a phase comparator(100), an up/down generator(200), a phase selector(400), and a multiple-phase clock generator(300). The phase comparator compares phases of an input signal and a recovery signal and generates an up-signal used to lead the phase or a down-signal used to lag the phase. The up/down generator reprocesses the up signal or the down signal generated at the comparator and generates a phase select signal to be robust to an inter-loop delay. The phase selector selects one of the plurality of phases generated at the multiple phase generator according to the select signal, or generates a different phase by mixing two phases.

Description

Clock recovery circuit using up / down signal generator of being insensible to delay in a loop}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a clock recovery circuit used on the receiving side in optical communication or high speed serial data communication. More specifically, an up / down generator insensitive to delay in loops that can reduce phase noise caused by delay in recovery loops. It relates to a clock recovery circuit using.

In general, a clock-data recovery circuit is widely used in the field of optical communication or high-speed serial data communication in which a clock cannot be transmitted through a channel like data as shown in FIG. 1. The clock-data recovery circuit 30 extracts clock information by the clock recovery circuit 30B from the data stream transmitted from the transmitter 10 and passed through the channel 20 to restore the clock, and the data recovery circuit ( 30A) samples the received data stream at the correct time to restore the data. The performance of this clock recovery circuit 30B depends on the phase tracking characteristics and the noise characteristics. The phase tracking characteristic depends on how quickly the clock recovery circuit tracks the phase change of the input data to minimize the phase error. The noise characteristic depends on the design of the clock recovery circuit to filter out the noise contained in the input data so that it is insensitive to noise. However, since the phase tracking and noise characteristics are related to the bandwidth of the recovery loop of the clock recovery circuit, the phase tracking and noise characteristics always need to be traded off. In other words, if the bandwidth of the recovery loop is widened, the phase tracking characteristics are better, but the noise characteristics are worse. If the bandwidth of the recovery loop is narrow, the noise characteristics are better, but the phase tracking characteristics are worse.

There are two methods of implementing a clock recovery circuit, an analog method and a digital method. The analog method is widely used in clock recovery circuits using phase locking loops or delay locking loops. If there is a phase difference between the data stream and the recovered clock, a linear voltage corresponding to the phase difference is generated to delay cells of the phase locking loop or the delay locking loop. In addition to the control voltage, the recovery clock produced by the phase-locking loop or delay-locking loop follows the phase of the input data stream. However, this method has a disadvantage in that it takes a long time from the initial state to the phase locking state, which is not suitable for high-speed data transmission requiring fast phase locking.

Digital clock recovery circuits are designed to solve the phase tracking problem of analog clock recovery circuits. In the digital clock recovery circuit, if there is a difference in the phase of the data stream and the recovery clock, instead of generating a linear voltage in the phase difference, the phase shift of the current recovery clock is performed according to the up and down signals generated by the phase comparator. Regardless of the minimum resolution. In the case of the digital method, the phase of the current recovery clock can be stored as a digital value, so the time from the initial state to the stable state is very short. In addition, the phase change of the input data can be quickly tracked to maintain the locked state at all times. However, this method has a disadvantage in that the phase noise of the recovery clock depends on the minimum resolution of the phase change, so that the overall phase noise is larger than that of the analog method. To reduce the phase noise, the resolution of the minimum phase change must be made small. Due to the limitations of the circuit design, it is difficult to reduce the resolution beyond a certain limit, so the minimum resolution of the digital clock recovery circuit is generally larger than that of the analog clock recovery circuit. In particular, there is always a delay in the reconstruction loop that extracts the phase information from the sampled data and changes the current phase of the reconstruction clock based on the delay. This delay increases the phase noise of the digital clock reconstruction circuit seriously. Make.

The first circuit used in the digital clock recovery circuit is a clock recovery circuit with a bang bang controller 34 as shown in FIG. This circuit receives an up or down signal from the phase comparator 32 to change the phase by increasing or decreasing the current value of the phase selector 38. The phase noise of this circuit is one minimum resolution in the ideal case where there is no delay in the recovery loop as shown in FIG. However, if there is a delay, the recovery loop becomes unstable and much larger. As shown in FIG. 3, when there is a delay of 2 clock cycles in the recovery loop, the phase noise increases by 3 to 4 times. This phase noise increases with more delay.

A clock recovery circuit (Korean Patent Application No. 1997-0031271) designed to recover a digital clock and carrier by connecting a digital filter after a digital phase detector is designed to filter out phase noise to reduce phase noise. This circuit has the advantage of reducing phase noise by filtering the high frequency phase noise of the input data in the locked state, but due to the delay inevitably present between phase comparison, digital filtering and phase error compensation, phase tracking is required, such as high speed data communication. The disadvantage is that the phase noise becomes large. In addition, the digital filter has a disadvantage in that a lot of hardware is required for implementation.

As shown in FIG. 4, a clock recovery circuit which counts up / down signals generated by the phase comparator 32A instead of the digital filter using the up-down counter 34A and changes the phase when a certain threshold number is reached (US Pat. No. 6,351,165, Korea). Patent application 2000-0074813 has the advantage that it is simpler to implement than a digital filter and can reduce phase noise in a locked state. However, as shown in FIG. 5, recovery is performed like a clock recovery circuit having a bang bang controller or a clock recovery circuit having a digital filter. The disadvantage is that it is sensitive to delays present in the loop.

In order to reduce noise caused by the instability of the recovery circuit caused by the delay in the loop, the input data is sampled several times and converted into digital signals. Then, the edge information is extracted from the oversampling data to restore the clock and based on the clock information. In the case of the clock data recovery circuit (Korean Patent Application No. 2001-0023620, Korean Patent Application 2002-0018488) which selects one from oversampled data and uses it as the recovery data, the problem caused by the delay in the loop does not occur, but it is over three times over. The disadvantage is that sampling is not available and the phase of the multi-phase clock used for oversampling is fixed so that data sampling cannot be made at the optimal position.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention is directed to an up / down generator which is insensitive to delay in the loop so that only phase noise is reduced without significantly affecting the phase tracking characteristics. It is an object of the present invention to provide a clock recovery circuit.

In order to achieve the above object, a clock recovery circuit using an up / down generator insensitive to delay in an loop according to a preferred embodiment of the present invention is a circuit for recovering a clock synchronized with an input signal. A phase comparator that compares the phase of the recovered clock to produce an up signal that leads the phase or a down signal that phases the phase, and re-creates the up or down signal generated by the phase comparator to be insensitive to the delay present in the recovery loop. Select one of the multiple phase clocks of the multiphase clock generator, or mix two phases with a select signal produced by a delay-insensitive updown generator, and a delay-insensitive updown generator that produces a phase select signal. A phase selector to create a multiphase clock generator to produce a multiphase clock. It is.

The phase comparator comprises: a sampler for sampling an input signal with a reconstructed clock and storing it as digital data; a transition detector for detecting data transitions such as data up transition for phase read and data down transition for phase lag from the sampler data; And a state phase comparator for determining an up or down signal by comparing the number of up and down transitions from one or several up and down transitions.

The state phase comparator determines a state of the up or down signal, and makes a state comparison stage that makes all the states for the difference between the number of input up and down transitions and makes the logic 1 only the state corresponding to the difference between the number of the up and down transitions. One or more stages are used to compare the difference between the number of up and down transitions.

The delay-insensitive up-down generator is a delay-insensitive up-down generator that accepts an up or down signal generated every clock cycle in the phase comparator and produces a flag signal that increases, decreases or maintains the current value of the phase selector. And an adder and a subtractor for increasing, decreasing or maintaining the value of the phase selector by the flag signal.

The delay-insensitive up-down generator accepts an up or down signal generated every clock cycle from the phase comparator, and when the same type of signal occurs continuously (continuous up or continuous down), the first signal Increment or decrement the flag signal for use in the phase shift and invalidate the same consecutive signal as many times the number of clock cycles present in the recovery loop to keep the flag signal unused for phase shift.

The delay-insensitive up-down generator is used to increase or decrease the flag signal so that, for successive identical signals exceeding the number of delay clock cycles present in the recovery loop, the first signal exceeding the number of delay clock cycles is used for phase shift. In addition, the same signal in succession for the number of delayed clock cycles present in the subsequent recovery loop is invalidated to keep the flag signal unused for phase changes.

The delay-insensitive up-down generator causes the flag signal to increase or decrease for use in phase shifting for other signals occurring every clock cycle.

The phase selector includes a phase selector latch for storing and maintaining a phase selection value determined by a phase generator insensitive to delay, a multiplexer for selecting a phase of a multi-phase clock generator according to the value of the phase selector latch, and two selected according to the value of the phase selector. It includes a phase mixer that mixes phase clocks to produce clocks of phases different from the two phases.

1 is a block diagram of a transmission and reception circuit of a general serial communication;

2 is a block diagram of a clock recovery circuit having a bang bang controller as an example of a clock recovery circuit provided on the receiving circuit side of a conventional serial communication;

3 is an operation timing diagram of FIG. 2;

4 is a block diagram of a clock recovery circuit having an up-down counter as another example of a clock recovery circuit provided on the receiving circuit side of a conventional serial communication;

5 is an operation timing diagram of FIG. 4;

6 is a clock recovery circuit block diagram having a delay-insensitive up-down generator as a clock recovery circuit provided on the receiving circuit side of serial communication according to the present invention;

7 is an operation timing diagram of FIG. 6;

8 is a detailed circuit block diagram of a clock recovery circuit having an up-down generator insensitive to the delay shown in FIG. 6;

9 is an operation timing diagram of the sampler and the transition detector of FIG. 8;

10 is a detailed circuit block diagram of the state phase comparator of FIG. 8;

11 is a view for explaining the operation of the phase selector latch in FIG.

<Description of Symbols for Major Parts of Drawings>

10 transmitter 20 communication channel

30: clock-data recovery circuit 30A: data recovery circuit

30B: clock recovery circuit 32: phase comparator

34: Bang Bang Controller 36: Multiphase Clock Generator

38: phase selector

Hereinafter, a clock recovery circuit using an up / down generator insensitive to an in-loop delay according to an embodiment of the present invention will be described with reference to the accompanying drawings.

The clock recovery circuit of the present invention is composed of a phase comparator 100, an up-down generator 200 insensitive to delay, a phase selector 400, and a multiphase clock generator 3000 as shown in FIG. The phase comparator 100 compares the phase of the input data and the recovery clock and as a result, generates an up or down signal. The up-down generator 200 which is insensitive to delay serves to generate the selection signal of the phase selector 400 according to the up or down signal generated by the phase comparator. The phase selector 400 selects one of the clocks of the various phases generated by the multiphase clock generator 400 according to the selection signal generated by the updown generator, or generates a clock of another phase with the clocks of two phases of the multiple phases. The multi-phase clock generator 300 serves to provide the phase selector 300 with clocks of various phases having a reference frequency.

The operation timing diagram of the clock recovery circuit of the present invention is shown in FIG. It consists of the input data and the reference clock used for the multiphase clock generator 300, the output of the phase comparator 100, the output of the up-down generator 200, and the recovery clock. It is represented by a selectable phase made from. In this example, it is assumed that there is a frequency difference between the input data and the reference clock and that there is a delay of two clock cycles in the recovery loop. As can be seen in the figure, a phase difference exists between the input data and the reconstructed clock, so that the phase comparator 100 generates an up or down signal every clock cycle. The up-down generator 200 which is insensitive to the delay of the up or down signal generated by the phase comparator 100 is reprocessed. When the same type of signal continues to occur as shown in FIG. 7, the up-down generator 200 performs a delay clock cycle. As long as the signal is invalidated so that no phase change occurs. Since a delay of two clock cycles is assumed above, when two or three of the same signal are continuous as shown in the previous part of FIG. 7, the up-down generator 200 invalidates the second and third signals so that the phase change does not occur. It takes two clock cycles before the clock recovery circuit changes the phase according to the current phase information made by the phase comparator 100, so that the same continuous signal by the number of delayed clock cycles can change the phase change with respect to the current phase information. It comes out before application, so it is invalidated. However, as shown in the latter part of FIG. 7, the fourth same signal is a result of the phase comparison after applying the phase change to the same signal as described above, which is meaningful and should be used for the phase change. In addition, the phase comparison signal as opposed to the current phase comparison is also related to the delay and should be used for the phase change. Therefore, as shown in Fig. 7, the down signal after the up signal and the up signal after the down signal were used to change the phase of the clock recovery circuit. The phase selector 400 selects one of clock signals of various phases generated by the multiphase clock generator 300 or selects two phase clocks based on the value generated by the up-down generator 200 to make and use another phase clock. .

Using the delay-insensitive up-down generator 200 as described above, as can be seen in Figure 7, the maximum phase noise is reduced to the lowest resolution, such as a clock recovery circuit with an ideal bang bang controller without delay.

8 shows an example of the configuration of the clock recovery circuit proposed in the present invention. Here, the sampler 100A, the transition detector 100B, and the state phase comparator 100C constitute the phase comparator 100 of FIG. 6, and the up-down generator 200A and the adder-subtractor 200B which are insensitive to delay are illustrated in FIG. 6. The up-down generator 200 insensitive to the delay of the phase selector 400A, the multiplexer 400B and the phase mixer 400C constitutes the phase selector 400 of FIG. The sampler 100A has a polyphase clock made by the phase mixer 400C to oversample the input data and convert the input data into digital data. The transition detector 100B detects a transition of data from the digital data generated by the sampler 100A. As shown in FIG. 9, when an exclusive OR is performed with neighboring sampling data, a transition of data is detected. In this example, 20 transitions are detected from 21 data and transferred to the state phase comparator 100C. The odd-numbered transitions (1, 3, 5, ..., 19th transitions) of the 20 transitions become the phase leading up transitions and the remaining even transitions (2, 4, 6, ..., 20th transitions). The phase heard is a down transition that lags. Add the number of up and down transitions made by the transition detector 100B to compare the number of up and down transitions, and then use the up or down signal to determine whether the phase should be read or lag in the current state. Comparator 100C produces it.

The state phase comparator 100C used in the present invention is implemented using a state comparison method. 10 is a configuration diagram of the state phase comparator 100C. In the first stage (S1), one up and down transitions are compared. As an example in FIG. 9, dup0 and ddn0 are compared. If dup0 is logic 1, then there is one up, and up0 is logic 1. If Ddn0 is logic 1, then there is one down, and dn0 is logic 1. If Dup0 and ddn0 are logic 0 at the same time or logic 1 at the same time, the state is neutral and n0 is logic 1. As in the case of Dup0 and ddn0, the other first stages also determine the state from their dup and ddn data and transfer it to the second stage (S2). The second stage determines states from the results of the two first stages, so there are four states. That is, there are two up transitions, one up transition, one neutral state, one down transition, and two down transitions. For example, if both first stages are up, up12 is logic 1, and one is up, one is neutral, up11 is logic 1, and if up and down are the same, n10 is one, one is down and one is neutral. If dn11 is both down, then dn12 is logic 1 respectively. Similarly, the third stage (S3) can produce nine status outputs from the two second stages. The fourth stage (S4) produces eleven state outputs from one third stage and one first stage. In the fifth stage (S5), only 11 states were produced with the outputs of two fourth stages. This is because more than five up or down states made up of outputs of the fourth stage with the maximum number of ups and downs are not significant, so more than five states are implemented with logic of up or down five states. However, it is a configuration for 10 up and 10 down signals, and when configured with a larger number of up and down signals, the fifth stage can be implemented to have all states. The output of the fifth stage becomes logic 1 only in the state of the difference between the number of up and down among the 11 outputs. In the last stage (S6) of the example of the present invention, the state of the up and down, which is the output of the fifth stage, is checked, and if any one of the five up outputs is logic 1, the up signal is outputted and if any one of the five down signals is logic 1, the down signal is output. Since the up signal and the down signal are in exclusive relationship, neither signal is one.

An example of the logic of each stage is as follows, and the logic can be equally applied to the same stage.

<Logical expression of the first stage (S1)>

up0 = dup0 * (~ ddn0)

dn0 = (~ dup0) * ddn0

n0 = (dup0 * ddn0) + ((~ dup0) * (~ ddn0))

<Logical expression of the second stage (S2)>

up12 = up0 * up1

up11 = (up0 * n1) + (n0 * up1)

n10 = (up0 * dn1) + (n0 * n1) + (dn0 * up1)

dn11 = (n0 * dn1) + (dn0 * n1)

dn12 = dn0 * dn1

<Logical formula of third stage S3>

up54 = up12 * up22

up53 = (up12 * up21) + (up11 * up22)

up52 = (up12 * n20) + (up11 * up21) + (n10 * u22)

up51 = (up12 * dn21) + (up11 * n20) + (n10 * up21) + (dn11 * u22)

n50 = (up12 * dn22) + (up11 * dn21) + (n10 * n20) + (dn11 * up21) + (dn12 * up22)

dn51 = (up11 * dn22) + (n10 * dn21) + (dn11 * n20) + (dn12 * up21)

dn52 = (n10 * dn22) + (dn11 + dn21) + (dn12 * n20)

dn53 = (dn11 * dn22) + (dn12 * dn21)

dn54 = dn12 * dn22

<Logical expression of the fourth stage (S4)>

up75 = up54 * up4

up74 = (up54 * n4) + (up53 * up4)

up73 = (up54 * dn4) + (up53 * n4) + (up52 * n4)

up72 = (up53 * dn4) + (up52 * n4) + (up51 * up4)

up71 = (up52 * dn4) + (up51 * n4) + (n50 * up4)

n70 = (up51 * dn4) + (n50 * n4) + (dn51 * up4)

dn71 = (n50 * dn4) + (dn51 * n4) + (dn52 * up4)

dn72 = (dn51 * dn4) + (dn52 * n4) + (dn53 * up4)

dn73 = (dn52 * dn4) + (dn53 * n4) + (dn54 * up4)

dn74 = (dn53 * dn4) + (dn54 * n4)

dn75 = dn54 * dn4

<Logical formula of the fifth stage (S5)>

up95 = (up75 * up85) + (up75 * up84) + (up75 * up83) + (up75 * up82) + (up75 * up81) +

(up75 * up80) + (up74 * up85) + (up74 * up84) + (up74 * up83) + (up74 * up82) +

(up74 * up81) + (up73 * up85) + (up73 * up84) + (up73 * up83) + (up73 * up82) +

(up72 * up85) + (up72 * up84) + (up72 * up83) + (up71 * up85) + (up71 * up84) +

(up70 * up85)

up94 = (up75 * dn81) + (up74 * n80) + (up73 * up81) + (up72 * up82) + (up71 * up83) +

(n70 * up84) + (dn71 * up85)

up93 = (up75 * dn82) + (up74 * dn81) + (up73 * n80) + (up72 * up81) + (up71 * up82) +

(n70 * up83) + (dn71 * up84) + (dn72 * up85)

up92 = (up75 * dn83) + (up74 * dn82) + (up73 * dn81) + (up72 * n80) + (up71 * up81) +

(n70 * up82) + (dn71 * up83) + (dn72 * up84) + (dn73 * up85)

up91 = (up75 * dn84) + (up74 * dn83) + (up73 * dn82) + (up72 * dn81) + (up71 * n80) +

(n70 * up81) + (dn71 * up82) + (dn72 * up83) + (dn73 * up84) + (dn74 * up85)

up90 = (up75 * dn85) + (up74 * dn84) + (up73 * dn83) + (up72 * dn82) + (up71 * dn81) +

(n70 * up80) + (dn71 * up81) + (dn72 * up82) + (dn73 * up83) + (dn74 * up84) +

(dn75 * up85)

dn91 = (up74 * dn85) + (up73 * dn84) + (up72 * dn83) + (up71 * dn82) + (n70 * dn81) +

(dn71 * n80) + (dn72 * up81) + (dn73 * up82) + (dn74 * up83) + (dn75 * up84)

dn92 = (up73 * dn85) + (up72 * dn84) + (up71 * dn83) + (n70 * dn82) + (dn71 * dn81) +

(dn72 * n80) + (dn73 * up81) + (dn74 * up82) + (dn75 * up83)

dn93 = (up72 * dn85) + (up71 * dn84) + (n70 * dn83) + (dn71 * dn82) + (dn72 * dn81) +

(dn73 * n80) + (dn74 * up81) + (dn75 * up82)

dn94 = (up71 * dn85) + (n70 * dn84) + (dn71 * dn83) + (dn72 * dn82) + (dn73 * dn81) +

(dn74 * n80) + (dn75 * up81)

dn95 = (n70 * dn85) + (dn71 * dn84) + (dn71 * dn85) + (dn72 * dn83) + (dn72 * dn84) +

(dn72 * dn85) + (dn73 * dn82) + (dn73 * dn83) + (dn73 * dn84) + (dn73 * dn85) +

(dn74 * dn81) + (dn74 * dn82) + (dn74 * dn83) + (dn74 * dn84) + (dn74 * dn85) +

(dn75 * dn80) + (dn75 * dn81) + (dn75 * dn82) + (dn75 * dn83) + (dn75 * dn84) +

(dn75 * dn85)

<Sixth stage (logic of S56)

Up = up95 + up94 + up93 + up92 + up91

Down = dn95 + dn94 + dn93 + dn92 + dn91

The state phase comparator 100C outputs an up or down signal every clock cycle. As shown in FIG. 11, the up-down generator 200A, which is insensitive to delay, accepts the up or down signal and decides whether to validate the current up or down signal to change the current phase or to maintain the current phase. Based on this determination, the up-down generator 200A generates and outputs signals of +1, +0, and -1 to the subtractor 200B so that the value of the phase selector latch 400A is increased, maintained, or decreased by one. Make. The output of the phase selector latch 400A is transmitted to the multiplexer 400B and the phase mixer 400C to change the current phase, and the clock of the new phase produced by the phase mixer 400C is output to the reconstruction clock and at the same time the sampler ( It is also input to 100A and used to sample the input data again.

On the other hand, the present invention is not limited to the above-described typical preferred embodiments, it can be carried out in various ways without departing from the gist of the present invention various modifications, alterations, substitutions or additions are common in the art Those who have knowledge will easily understand. If the implementation by such improvement, change, replacement or addition falls within the scope of the appended claims, the technical idea should also be regarded as belonging to the present invention.

As described in detail above, according to the present invention, even if there is a delay in the recovery loop, only phase noise may be reduced without significantly affecting the phase tracking characteristics.

Claims (8)

In a circuit for restoring a clock synchronized with an input signal, A phase comparator for comparing an input signal with a phase of a restored clock to generate an up signal for leading a phase or a down signal for laging a phase; An up-down generator that is insensitive to the delay that results in a phase comparator and an up- or down-signal produced by the phase comparator to be insensitive to the delay present in the recovery loop, A phase selector that selects one of the multiple phase clocks of a multiphase clock generator or mixes two phases to form a different phase by a select signal produced by a delay-insensitive downdown generator, A clock recovery circuit comprising a polyphase clock generator for generating a polyphase clock. The method of claim 1, The phase comparator comprises: a sampler for sampling an input signal with a recovery clock and storing the received signal as digital data; A transition detector for detecting data transitions, such as data up transitions for phase reads and data down transitions for phase lags, from the sampler's data; And a state phase comparator for determining an up or down signal by comparing the number of up and down transitions from one or several up and down transitions. The method of claim 2, The state phase comparator determines a state of the up or down signal, and makes a state comparison stage that makes all the states for the difference between the number of input up and down transitions and makes the logic 1 only the state corresponding to the difference between the number of the up and down transitions. A clock recovery circuit comprising one or more stages and comparing the difference in the number of up and down transitions. The method of claim 1, The delay-insensitive up-down generator is a delay-insensitive up-down generator that accepts an up or down signal generated every clock cycle in the phase comparator and produces a flag signal that increases, decreases or maintains the current value of the phase selector. And an adder and a subtractor for increasing, decreasing or maintaining the value of the phase selector by the flag signal. The method of claim 1, The delay-insensitive up-down generator accepts an up or down signal generated every clock cycle from the phase comparator, and when the same type of signal occurs continuously (continuous up or continuous down), the first signal A clock recovery circuit characterized by increasing or decreasing the flag signal for use in phase shift and invalidating the same consecutive signal as the number of delayed clock cycles present in the recovery loop to keep the flag signal unused for phase shift. . The method of claim 4, wherein The delay-insensitive up-down generator is used to increase or decrease the flag signal so that, for successive identical signals exceeding the number of delay clock cycles present in the recovery loop, the first signal exceeding the number of delay clock cycles is used for phase shift. And retaining the flag signal so that it is invalidated for use by the phase change by invalidating the same consecutive signal as the number of delayed clock cycles present in the subsequent recovery loop. The method of claim 4, wherein And the delay-insensitive up-down generator increases or decreases the flag signal for use in phase shifting for other signals occurring every clock cycle. The method of claim 1, The phase selector includes: a phase selector latch for storing and maintaining a phase selection value determined by a phase generator insensitive to delay; a multiplexer for selecting a phase of a multi-phase clock generator according to a value of a phase selector latch; And a phase mixer for mixing phase clocks to produce clocks of phases different from the two phases.