KR20040102719A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20040102719A
KR20040102719A KR1020030034299A KR20030034299A KR20040102719A KR 20040102719 A KR20040102719 A KR 20040102719A KR 1020030034299 A KR1020030034299 A KR 1020030034299A KR 20030034299 A KR20030034299 A KR 20030034299A KR 20040102719 A KR20040102719 A KR 20040102719A
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KR
South Korea
Prior art keywords
guard ring
chip
scribe line
semiconductor device
guard
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KR1020030034299A
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Korean (ko)
Inventor
윤훈상
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주식회사 하이닉스반도체
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Priority to KR1020030034299A priority Critical patent/KR20040102719A/en
Publication of KR20040102719A publication Critical patent/KR20040102719A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Abstract

PURPOSE: A semiconductor device is provided to prevent crack of a guard ring and to reduce guard part size by forming an auxiliary guard ring at an outer of the guard ring. CONSTITUTION: A chip part(32) is located to form a device on a semiconductor substrate(30). A scribe line part(36) is located to separate the device between the chip parts. A guard ring(40) is simultaneously formed with a metal line at an outer of the chip part. A flatness part(36-1) is located to form a test pattern in a center of the scribe line part. An outer slope part(36-2) is formed in an outer of the scribe line part. An auxiliary guard ring(50) is formed simultaneously with the guard ring in the slope part and electrically floated.

Description

반도체소자{Semiconductor device}Semiconductor device

본 발명은 반도체소자에 관한 것으로서, 특히 소자를 보호하기 위한 가드링의 외곽에 패턴의 변화 없이 보조 가드링을 구비하여 가드링의 크랙 발생을 방지하고, 가드부의 면적을 감소시킬 수 있는 반도체소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an auxiliary guard ring on the outer side of a guard ring for protecting the device to prevent cracking of the guard ring and reducing the area of the guard portion. It is about.

통상의 반도체소자는 웨이퍼상에 소자들을 형성한후에 그 상부면은 패시베이션막을 통하여 보호하고, 소자들의 측벽은 금속배선 형성시에 형성하는 가이드링에 의해 보호된다. 이러한 칩의 가드부는 칩을 외부의 환경, 예를 들어 흡습이나 크랙등으로부터 보호하고 파워 배선 용도로 사용하기 위하여 칩의 최외곽에 둘려쳐지는 펜스와 같은 것으로 외부와 칩을 격리 시키는 역할을 수행한다.A typical semiconductor device is formed after forming elements on a wafer, the upper surface of which is protected by a passivation film, and the sidewalls of the elements are protected by guide rings which are formed during metal wiring formation. The guard part of the chip serves to isolate the chip from the outside by a fence that is surrounded by the outermost part of the chip in order to protect the chip from an external environment such as moisture absorption or cracking and to use it for power wiring. .

이러한 가드부에 형성되는 가드링은 패키지 타입의 TSOP에서는 칩이 외부로 직접 드려나지 않아 큰 문제저가 발생될 확률이 적으나, 점차 사용이 증가되고 있는 칩스케일 패키지인 FBGA(fine-pitch ball grid array)나 μBGA등에서는 칩이 외부에 직접 노출되므로 외부 환경으로부터 칩을 보호하기 위해서는 가드부의 역할이 더욱 증가된다.The guard ring formed on the guard part is less likely to cause a large problem because the chip is not directly exposed to the outside in the package type TSOP, but the fine-pitch ball grid array, a chip scale package that is increasingly being used, is increasing. ) And μBGA, the chip is directly exposed to the outside, so the role of the guard is increased to protect the chip from the external environment.

도 1 및 도 2는 종래 기술에 따른 반도체소자를 설명하기 위한 도면들로서, 서로 연관시켜 설명한다.1 and 2 are diagrams for describing a semiconductor device according to the related art, which will be described in association with each other.

먼저, 소정의 소자들이 형성되어있는 반도체기판(10)의 소자가 형성되어있는 칩부(12)와, 상기 칩부(12)를 감싸는 테두리 부분인 가드부(14)에는 금속배선 형성시 함께 형성된 팬스 형상의 가드링(20)이 형성되며, 인접칩과의 사이에는 스크라이브라인부(16)가 위치한다.First, the chip portion 12 in which the elements of the semiconductor substrate 10 on which the predetermined elements are formed is formed, and the guard portion 14, which is an edge portion surrounding the chip portion 12, has a fan shape formed together with the metal wiring. The guard ring 20 is formed, and the scribe brine portion 16 is positioned between the adjacent chip.

상기의 가드링(20)은 반도체기판(10)상에 게이트전극(21)과 제1비아콘택(22)과, 비트라인(23), 제2비아콘택(24)과 제1금속배선(25), 제3비아콘택(26)과 제2금속배선(27)으로 구성되어 팬스 역할과 동시에 파워배선으로 사용되고, 그 상부에 보호막(28)이 형성된다.The guard ring 20 has a gate electrode 21, a first via contact 22, a bit line 23, a second via contact 24, and a first metal wiring 25 on the semiconductor substrate 10. ), The third via contact 26 and the second metal wiring 27 are used as the power wiring at the same time as the fan, and a protective film 28 is formed thereon.

상기와 같이 종래 기술에 따른 반도체소자는 소잉이나 칩핑과 같은 패키지 공정시 스크라이브라인부와 가드링이 인접하여 있어 직접 손상을 입을 수 있고, 크랙이 쉽게 발생되어 소자의 신뢰성을 떨어뜨리고, 수율을 저하시키는 문제점이 있다.As described above, the semiconductor device according to the prior art may be directly damaged by the scribe brain portion and the guard ring adjacent to each other during the packaging process such as sawing or chipping, and cracks may be easily generated to reduce the reliability of the device and lower the yield. There is a problem.

본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 반도체 웨이퍼의 칩 사이에 위치하는 스크라이브 라인부의 반도체칩 인접부에 전기적으로 플르팅된 더미 가드링을 형성하되, 각종 테스트 패턴이 형성되지 않는 경사부에 형성하여 패턴 형성에 어떠한 영향도 미치지 않는 이중의 가드링이 되도록하여 패키지시의 불량발생을 방지할 수 있는 반도체소자를 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a dummy guard ring electrically floated in the vicinity of the semiconductor chip portion of the scribe line portion located between the chips of the semiconductor wafer, the various test patterns The present invention provides a semiconductor device that can be formed on an inclined portion not formed so that a double guard ring does not have any effect on pattern formation, thereby preventing defects in packaging.

도 1은 종래 기술에 따른 반도체소자의 평면도.1 is a plan view of a semiconductor device according to the prior art.

도 2는 도 1에서의 선 A-A'에 따른 단면도.2 is a cross-sectional view taken along the line A-A 'in FIG.

도 3은 본 발명에 따른 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10, 30 : 반도체기판 12, 32 : 칩부10, 30: semiconductor substrate 12, 32: chip portion

14, 34 : 가드부 16, 36 : 스크라이브라인부14, 34: guard part 16, 36: scribe brain part

20, 40 : 가드링 21, 41 : 게이트전극20, 40: guard ring 21, 41: gate electrode

22, 42 : 제1비아콘택 23, 43 : 비트라인(23)22, 42: first via contact 23, 43: bit line 23

24, 44 : 제2비아콘택 25, 45 : 제1금속배선24, 44: 2nd via contact 25, 45: 1st metal wiring

26, 46 : 제3비아콘택 27, 47 : 제2금속배선26, 46: third via contact 27, 47: second metal wiring

28, 48 : 보호막 36-1 : 평탄부28, 48: protective film 36-1: flat portion

36-2 : 경사부 50 : 보조 가드링36-2: inclined portion 50: auxiliary guard ring

51 : 소자분리 산화막51: device isolation oxide film

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 특징은,Features of the semiconductor device according to the present invention for achieving the above object,

가드링을 구비하는 반도체소자에 있어서,In a semiconductor device provided with a guard ring,

반도체기판의 일측에 소저의 소자들이 형성되어있는 칩부들과,Chip portions, on which one side of the semiconductor substrate is formed,

상기 칩부들의 사이에서 칩을 분리시키는 스크라이브 라인부와,A scribe line portion separating the chips between the chip portions;

상기 칩부들의 외곽에 배선 형성시 형성된 가드링과,A guard ring formed when wirings are formed outside the chip parts;

상기 스크라이브 라인부의 중앙에 각종 테스트 패턴이 형성되는 평탄부와,A flat part in which various test patterns are formed in the center of the scribe line part;

상기 스크라이브 라인부의 외곽 경사부와,An outer inclined portion of the scribe line portion;

상기 경사부에 상기 가드링 형성시 형성되되, 전기적으로 플루팅 되도록 형성되어있는 보조 가드링을 구비함에 있다.The guard ring is formed when the guard ring is formed, and is provided with an auxiliary guard ring which is formed to be electrically fluted.

이하, 본 발명에 따른 반도체소자에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 반도체소자의 단면도이다.3 is a cross-sectional view of a semiconductor device according to the present invention.

먼저, 소정의 소자들이 형성되어 있는 반도체기판(30)상에 소자가 형성되어있는 칩부(32)와, 상기 칩부(32)의 테두리 부분인 가드부(34)와, 인접한 칩들과의 사이에는 칩들을 분리시키기 위한 스크라이브 라인부(36)가 위치한다.First, a chip is formed between a chip portion 32 in which elements are formed on a semiconductor substrate 30 on which predetermined elements are formed, a guard portion 34 which is an edge portion of the chip portion 32, and adjacent chips. The scribe line portion 36 for separating them is located.

여기서 상기 가드부(34)에는 금속배선 형성시 함께 형성된 펜스 형상의 가드링(40)이 형성되어 있으며, 상기 스크라이브 라인부(36)는 중앙에 키나 테스트 패턴이 형성되는 평탄부(36-1)와, 경계의 패턴이 없는 경사부(36-2)가 위치하며, 상기 경사부(36-2)에는 상기 가드링(40) 형성시 함께 형성된 보조 가드링(50)이 소자분리 산화막(51)상에 형성되어 전기적으로 플루팅되어있다.Here, the guard portion 34 is formed with a fence-shaped guard ring 40 formed together with the metal wiring, and the scribe line portion 36 is a flat portion 36-1 in which a key or a test pattern is formed in the center thereof. And an inclined portion 36-2 having no boundary pattern, and an auxiliary guard ring 50 formed when the guard ring 40 is formed on the inclined portion 36-2. It is formed on and electrically fluted.

또한 상기 가드링(40)은 반도체기판(30)상에 게이트전극(41)과 제1비아콘택(42)과, 비트라인(43), 제2비아콘택(44)과 제1금속배선(45), 제3비아콘택(46)과 제2금속배선(47)으로 구성되어 펜스 역할과 동시에 파워배선으로 사용되고, 상기 보조 가드링(50)은 상기 가드링(40)과 그 구성은 동일하나, 반도체기판(30)에 형성된 소자분리 산화막(51)상에 제1비아콘택(42)과, 비트라인(43), 제2비아콘택(44)과 제1금속배선(45), 제3비아콘택(46)과 제2금속배선(47)으로 구성되어 이중 펜스 역할만을 수행하며, 각각의 상부에는 보호막(48)이 형성된다.In addition, the guard ring 40 may include a gate electrode 41, a first via contact 42, a bit line 43, a second via contact 44, and a first metal wiring 45 on the semiconductor substrate 30. ), The third via contact 46 and the second metal wiring 47 are used as the power wiring at the same time as the fence, the auxiliary guard ring 50 is the same as the configuration of the guard ring 40, The first via contact 42, the bit line 43, the second via contact 44, the first metal wiring 45, and the third via contact are formed on the device isolation oxide layer 51 formed on the semiconductor substrate 30. It is composed of 46 and the second metal wiring 47 serves only a double fence, the protective film 48 is formed on each upper portion.

상기의 보조 가드링(50)은 비아 콘택으로만 구성되며, 평면적으로 라인형 가드로나 또는 콘택형 가드로도 형성할 수 있으며, 하나의 펜스가 아니라 여러겹의 펜스 형상으로 형성할 수도 있고, 기본적으로 소자분리 산화막(51)상에 형성되어 전기적으로 플루팅되어 있으며, 상기 스크라이브 라인부(36)의 패턴이 없는 경사부(36-2)에 형성되므로, 패턴에 영향을 주지않고 형성할 수 있고, 이중 펜스가 되므로, 가드링(40)의 면적을 감소시킬 수 있어 소자의 고집적화에 유리하다.The auxiliary guard ring 50 is composed of only via contacts, and may be formed as a line guard or a contact guard in a plan view, and may be formed as a plurality of fence shapes instead of a single fence. And formed on the device isolation oxide film 51 and electrically fluted, and formed on the inclined portion 36-2 without the pattern of the scribe line portion 36, so that it can be formed without affecting the pattern. Since the double fence, the area of the guard ring 40 can be reduced, which is advantageous for high integration of the device.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자는 칩의 외곽에서 펜스 역할과 파워배선 역할을 수행하는 가드링 외곽에 가드링 형성시 함께 전기적으로 플루팅된 보조 가드링을 형성하되, 스크라이부라인부의 패턴이 형성되지 않는 경사부에 형성하였으므로, 패키지 공정시의 충격으로부터 칩을 이중으로 보호하여 불량발생을 방지할 수 있으며, 가드링의 면적을 감소시켜 칩의 고집적화에 유리하고, 가드링의 크랙에 의한 DC 불량과 외부로 부터의 흡습을 방지하여 공정수율 및 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the semiconductor device according to the present invention forms an auxiliary guard ring that is electrically fluted together when the guard ring is formed on the outer side of the guard ring, which serves as a fence and a power wiring on the outer side of the chip. Since it is formed on the inclined portion where the pattern of the printed part is not formed, it is possible to protect the chip from the impact during the packaging process to prevent the occurrence of defects, and to reduce the area of the guard ring, which is advantageous for the high integration of the chip. There is an advantage that can improve the process yield and the reliability of the device by preventing DC defects due to cracks and moisture absorption from the outside.

Claims (1)

가드링을 구비하는 반도체소자에 있어서,In a semiconductor device provided with a guard ring, 반도체기판의 일측에 소정의 소자들이 형성되어있는 칩부들과,Chip parts in which predetermined elements are formed on one side of the semiconductor substrate, 상기 칩부들의 사이에서 칩을 분리시키는 스크라이브 라인부와,A scribe line portion separating the chips between the chip portions; 상기 칩부들의 외곽에 배선 형성시 형성된 가드링과,A guard ring formed when wirings are formed outside the chip parts; 상기 스크라이브 라인부의 중앙에 소정의 테스트 패턴이 형성되는 평탄부와,A flat part in which a predetermined test pattern is formed in the center of the scribe line part; 상기 스크라이브 라인부의 외곽 경사부와,An outer inclined portion of the scribe line portion; 상기 경사부에 상기 가드링 형성시 형성되되, 전기적으로 플르팅 되도록 형성되어있는 보조 가드링을 구비하는 반도체소자.And an auxiliary guard ring which is formed when the guard ring is formed on the inclined portion and is electrically floated.
KR1020030034299A 2003-05-29 2003-05-29 Semiconductor device KR20040102719A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8314476B2 (en) 2010-05-07 2012-11-20 Hynix Semiconductor, Inc. Semiconductor chip and semiconductor wafer
CN103337466A (en) * 2013-06-26 2013-10-02 上海华力微电子有限公司 Protection ring for preventing short circuit of test structure, and manufacturing method and package testing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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