KR20040101742A - Method and Hardware Architecture for Searching IP Address by Using SRAM and Hashing - Google Patents

Abstract

PURPOSE: A method for searching an IP(Internet Protocol) address using a hashing table formed with an SRAM and a hardware structure thereof are provided to search an entry having the longest matched prefix bits from the entries matched in each table, after making several address search tables with the SRAMs and performing address search by applying a hashing technique to each table. CONSTITUTION: A hashing hardware(100) hashes the prefix of the input address. A main processor(110) is equipped with a main table(111), searches the entry of the main table having the prefix matched with the prefix of the address by comparing the prefix of the address with the prefix stored in a position, which is appointed by a hashing result value, of the main table, and transmits matched entry information. A sub-processor(120) is equipped with a sub table(121), searches the entry of the sub table having the prefix matched with the prefix of the address from the position appointed by a pointer of the main table, and transmits the matched address information. A priority encoder(130) searches the entry having the longest matched prefix bits from respective entries by receiving the matched entry information.

Description

Method and Hardware Architecture for Searching IP Address by Using SRAM and Hash}

The present invention relates to an IP address retrieval method and hardware architecture using SRAM and hashing. More specifically, a number of address lookup tables are created using different SRAMs for each prefix length of an IP address, and address lookups are simultaneously performed by applying a hashing method to each table, and among the entries matched in each table. The present invention relates to a method for retrieving an IP address by searching for an entry having the longest number of bits of a prefix, and a hardware structure therefor.

In order to provide Internet services, such factors as link speed and packet transfer rate related to router data throughput are important. Packet forwarding in Internet routers is not currently being performed as fast as link speeds with current technologies. In particular, address lookup, which is the most important process in performing packet forwarding, is a key in a forwarding table stored in a router using a destination address in a header of a packet input to the router as a key. This is the process of finding an entry that matches, which is a major contributor to time delays in today's routers. Therefore, one of the important issues in designing next-generation Internet routers is how fast address search can be performed.

The most intuitive address retrieval structure would be to use the Internet Protocol (IP) address itself as a pointer to the memory. In other words, since the IP destination address is 32 bits, set a memory with 2 ³² entries, and use the destination IP address of the packet as a key when any packet comes in so that it corresponds to the entry in the memory pointed to by the destination IP address. It is to store the forwarding information. However, this method is not practical because it requires a huge amount of memory of 12 Gbytes if one entry is 3 bytes in size.

Various routing-lookup algorithms have been proposed for performing Longest Prefix Matching required for IP address lookup. IP address retrieval has been studied mainly using Trie because of the hierarchical structure of IP addresses and the specificity that comes from the Classless Inter-Domain Routing (CIDR) structure.

Forwarding-Lookup Structure uses 150 ~ 160 Kbytes of memory to construct a large routing table with 40,000 entries and then attempts a software approach. The problem is that at least two to nine memory accesses are required.

Fast Routing-Lookup Scheme uses a large amount of Dynamic Random Access Memory (DRAM), which requires up to two memory accesses for address lookup, but requires as much as 33 Mbytes of storage space. There is a problem that. On the other hand, when the size of the transfer table is reduced to 9 Mbytes by adding an intermediate-length table, the number of memory accesses is increased to three times.

The method based on the binary search mechanism has the advantage of easy scaling even if the size of the address and routing table is increased. However, in the worst case, a hash search of log ₂ (address bits) is required. Although this software-based approach can be further complemented using the multi-way search method, the multi-column search method, and the cache structure, this method is implemented in hardware due to the assumption of perfect hashing. There is a problem that this is not easy.

The use of Contents Addressable Memories (CAMs) is a typical hardware implementation, where the values stored in memory and incoming key values are compared directly in parallel. However, the CAM method is slower, more expensive, and has less storage space than conventional memory. Therefore, there is a problem that the cost is too high to apply the CAM scheme in IPv6 using a 128-bit address.

Considering the above-described conventional methods, considerations for determining the routing method include considering the average number of memory accesses, the amount of storage space required, the ease of updating, the need for preprocessing, and the possibility of hardware implementation. Can be. Therefore, there is a need for an IP address retrieval method that reduces the average number of memory accesses, minimizes the size of the storage space, facilitates the update operation, requires no preprocessing, and can be easily implemented in hardware.

In order to solve the above problems, the present invention, in the IP address search method and hardware structure using SRAM and hashing, to create a plurality of address lookup table using different SRAM for each prefix length of the IP address, for each table To provide an address and a hardware structure for searching an IP address by applying a hashing method and searching for an address that has the longest number of prefix bits among entries matched in each table. The purpose.

1 is a block diagram showing a hardware structure for IP address lookup according to a preferred embodiment of the present invention;

2 is a flowchart illustrating a method of searching for an IP address according to a preferred embodiment of the present invention;

3 is a diagram illustrating a search structure of a hash table for each SRAM according to a preferred embodiment of the present invention;

4 is a graph illustrating a memory access distribution in a hardware structure for IP address retrieval according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: hash hardware 110: main processor

111: main table 120: coprocessor

121: Auxiliary Table 130: Priority Encoder

302, 312 prefix field 304, 314 next hop address field

306, 316: output port field 308: collision count field

310: pointer field

In order to achieve the above object, the present invention provides a method for retrieving an IP address using a hash table composed of an SRAM generated in a form in which entries are stored in a main table and an auxiliary table configured for each prefix length of an IP address, (a) hashing the addresses for each prefix length of the address using hash hardware configured for each prefix length of the input address; (b) comparing the prefix stored at the point of the main table indicated by the result of the hash with the prefix of the address so that the entry of the main table having a prefix that matches the prefix of the address by the prefix length of the address; Retrieving and transmitting information of matched entries, respectively; (c) if the matching prefix is not found, starting from the point of the auxiliary table pointed to by the pointer of the main table, and having a prefix that matches the prefix of the address; Searching each entry of the auxiliary table for each prefix length of the address and transmitting information of a matched entry; And (d) searching for an entry having the longest number of bits of the prefix among the entries searched for each prefix length of the address by using the information transmitted in the steps (b) and (c). An IP address retrieval method using an SRAM and a hash is provided.

According to another object of the present invention, there is provided a hardware structure for IP address retrieval using SRAM and hashing, comprising: hashing hardware for hashing a prefix of an input address; A main table in which entries are stored in the form of a hash table according to the prefix length of the address, and the prefix stored at the point of the main table indicated by the hash value is compared with the prefix of the address; A main processor for retrieving the entry of the main table having a matching prefix and transmitting information of the matched entry; The auxiliary table having an auxiliary table in which entries are stored in the form of a hash table according to the prefix length of the address, starting at the point of the auxiliary table indicated by the pointer of the main table, and having a prefix that matches the prefix of the address; A coprocessor for retrieving said entry of and transmitting information of a matched entry; And a Priority Encoder for receiving the information of the matched entry and searching for an entry having the longest number of bits of the prefix among the entries searched for each prefix length of the address. It provides a hardware structure for IP address retrieval.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a block diagram illustrating a hardware structure for IP address retrieval according to a preferred embodiment of the present invention.

The hardware structure for IP address retrieval according to the preferred embodiment of the present invention has a structure including a hash hardware 100, the main processor 110, the coprocessor 120 and the Priority Encoder (130).

The hash hardware 100 functions to hash the prefix of the input address. The hash hardware 100 according to the preferred embodiment of the present invention uses a method of performing an exclusive OR by combining the number of bits of the prefix by the number of bits desired to be produced as a result of hashing.

The main processor 110 includes a main table 111 in which entries are stored in the form of hash tables according to the prefix length of the address. The main processor 110 compares the prefix stored in the point of the main table 111 indicated by the hash value from the hash hardware 100 and the prefix of the input address, and then selects the prefix that matches the prefix of the input address. Branch retrieves an entry in the main table 111.

The coprocessor 120 includes an auxiliary table 121 in which entries are stored in the form of hash tables according to the prefix length of the address. The coprocessor 120 searches for an entry in the sub table 121 starting at the point of the sub table 121 indicated by the pointer of the main table 111 and having a prefix that matches the prefix of the address.

Priority encoder 130 waits for the end of the search in all tables for any one address, and then searches for the entry with the longest number of bits of the prefix among the entries searched for each prefix length of the address.

As shown in FIG. 1, the hash hardware 100, the main table 111 and the auxiliary table 121 are generated for each prefix length of the address. The value from the separate hash hardware 100 for each prefix length that is used as an input points to an entry in one of the main tables 111, and part of the information stored in the main table 111 is again sub-table 121. Will be displayed. The main table 111 and the sub table 121 may be composed of one SRAM. That is, the address lookup table is configured separately for each prefix length, and address lookup is performed in parallel in the tables stored in the respective SRAMs. An algorithm for performing the above-described address search method is as follows.

Function Search_Prefix / * prefix search that matches address D entered * /

Do parallel (L = 8 ~ 32)

Extracts the first L bits of D into D ';

Table_pointer = Hash (D ');

/ * Hash (D ′) performs an Exclusive-OR and returns the table

use as pointer * /

Compare D'and an entry value pointed by Table_pointer;

if (not same) begin / * crash * /

use pointer to the Sub_table and # of entries to be

searched and perform Binary search for the entries;

end

Send Search_result and ACK to the Priority Encoder;

End Do parallel

Select the entry with longest prefix

The IP packet input in the algorithm according to the preferred embodiment of the present invention has a prefix length of 8 to 32. However, this value may vary.

The description of the algorithm is described with a flowchart according to the algorithm.

2 is a flowchart illustrating an IP address searching method according to a preferred embodiment of the present invention.

First, an address is decoded in parallel for each SRAM according to a prefix length by using hashing hardware 100 configured for each prefix length of an input address (S200). The hash hardware 100 according to the preferred embodiment of the present invention uses a method of performing an exclusive-OR by combining the number of bits of the prefix by the number of bits desired to be produced as a result of hashing. If the prefix length is not bound by the number of bits you want to result in the hash, then wrap it from the beginning by the number of bits you want to result in, and fill the remaining bits with random bits short of the number of bits you want to result. Perform Exclusive-OR. When filling the remaining bits, 1010... Fill it in the way. For example, for prefix 8, we use 2 bits as the result of the hash, so we compute it in the manner of hash value (8) = [7: 6] ^ [5: 4] ^ [3: 2] ^ [1: 0]. In the case of prefix 14, we want 6 bits to be created as a result of hashing, so that hash value (14) = [13: 8] ^ [7: 2] ^ {[1: 0], 0,1, 0,1}.

The prefix stored in the point of the main table 110 indicated by the hash value obtained in step S202 is compared with the prefix of the address, and an entry of the main table 110 having a prefix matching the prefix of the address is searched (S202). .

After determining whether or not a matching prefix is found as a result of the search (S204), if the search fails, that is, a collision occurs, starting from the point of the auxiliary table 121 indicated by the pointer of the main table 111, the prefix of the address The entry of the auxiliary table 121 having the prefix matching is searched for (S206). At this time, among the information stored in the entry of the main table 111, a pointer to the sub table 121 and information on how many collisions the entry has is used for the search. According to a preferred embodiment of the present invention, a binary search method is applied to entries corresponding to a collision phenomenon from a point pointed to by the pointer to the auxiliary table 121 pointed to by the pointer. If no collision has occurred, since the entry matching the prefix of the address is searched in the main table 111, it is not necessary to search the auxiliary table 121.

Since the collision does not occur, the information of the entry matching the prefix of the address retrieved from the main table 111 or the collision occurs, and the information of the entry matching the prefix of the address retrieved from the auxiliary table 121 is transmitted to the Priority encoder (S208). ). At this time, the information to be transmitted is next hop address information and output port information.

The above-described processes from S202 to S208 are performed in parallel for each SRAM according to the predetermined prefix length. Therefore, after the process of S208, a matched entry is searched for each prefix length of the address. The priority encoder waits for the end of the search in all tables for any one IP address, and then searches for the entry with the longest number of prefix bits among the searched entries (S210). That is, the prefix that matches the longest number of bits of the prefix among the entries retrieved for each prefix length is determined as a BMP (Best Matching Prefix), and the next hop address and output port information of the entry are used for packet transmission.

3 is a diagram illustrating a search structure of a hash table for each SRAM according to a preferred embodiment of the present invention.

As an example, FIG. 3 illustrates a hash function having an input prefix length of 24 bits and a calculated hash value of 16 bits, and structures of a main table 111 and an auxiliary table 121 connected thereto.

An entry in the main table according to a preferred embodiment of the present invention may include a prefix field 302, a next hop address field 304, an output port field 306, and a collision count field 308 corresponding to this hash entry. And a pointer field 310 pointing to the auxiliary table 121, and the auxiliary table 121 includes only the prefix field 312, the next hop address field 314, and the output port field 316.

As shown in FIG. 3, an example of (1) is a case where the search is finished in the main table 111. In this case, the information stored in the next hop address field 304 and the output port field 306 stored in the entry is sent to the Priority encoder. However, if the prefix stored at the point indicated by the hash value is a prefix of an address other than the prefix value of the input IP address, this is a case of (2) where a collision occurs and a pointer to the auxiliary table 121 among the information stored in the entry. The information stored in the field 308 and the collision count field 310 corresponding to this hash entry should be used for the search. According to a preferred embodiment of the present invention, a binary search is applied to entries corresponding to a collision phenomenon from a point pointed to by the pointer to the auxiliary table 121 pointed to by the pointer.

Although not shown in FIGS. 1 and 3, a forwarding RAM (not shown) including information such as a next hop address and an output port may be separately provided. When forwarding RAM (not shown) is used separately, the next hop address field 304 and the output port field 306 of the entry of the main table 111 and the entry of the auxiliary table 121 are forwarding ram (not shown). Can be replaced with a pointer field that points to. In this case, a slight difference occurs in the algorithm described above. That is, the information transmitted in step S210 is a pointer to a forwarding RAM (not shown) rather than next hop address information and output port information. Therefore, when searching for an entry having a longest prefix in step S216, since the priority encoder 130 does not have the next hop address information and the output port information of the entry, the next hop address information and the output port information of the entry are forwarded. Taken from RAM (not shown).

All of this is done in parallel for each SRAM along the prefix length. The Priority encoder waits for the end of the search in all tables for any one IP address, then selects the entry whose prefix number matches the longest bit among the entries whose prefix matches, and the next hop address and output port information for that entry Used for packet transmission.

Hereinafter, the performance of the IP address retrieval method and hardware structure for the same according to a preferred embodiment of the present invention.

Table 1 compares the performance of the required memory size and the number of memory accesses with other search schemes.

Address search method Number of memory accesses (min / max) Size of hatch table Noble IP-Routing Lookup 1/3 450 KB to 470 KB Quick search structure 1/2 33 MB Structure appending medium length table in quick search structure 1/3 9 MB Forward search structure 2/9 150 KB to 160 KB Structure of the present invention 1/5 189 KB

The hardware structure according to the preferred embodiment of the present invention requires the smallest memory except for the forward search structure as shown in Table 1. Since the hardware structure according to the preferred embodiment of the present invention uses a separate SRAM for each length of the prefix, an overhead thereof must be considered, and a disadvantage is that a separate hashing hardware 100 must be used for each prefix length. However, the solution using Exclusive-OR is less expensive to implement in hardware. In addition, the average number of memory accesses per packet is 1.93, which shows similar performance to other hardware-based methods.

4 is a graph illustrating a memory access distribution in a hardware structure for IP address retrieval according to a preferred embodiment of the present invention.

As shown in the distribution of FIG. 4, it can be seen that more than 78% of routes can be searched by two memory accesses, and more than 95% of routes can be searched by three memory accesses.

In Table 1, the hardware architecture for IP address retrieval according to the preferred embodiment of the present invention can be seen that the maximum number of memory accesses is five times, which is a case where the main table 111 is relatively small and many collisions occur. The maximum number of memory accesses can be adjusted by allocating more memory for the main table 111. Hardware pipeline techniques can also be used to improve address lookup throughput. For example, if the main table 111 and the sub-table 121 are configured using separate SRAMs, the address lookup in the main table 111 and the address lookup in the sub-table 121 are sequentially applied to the packets. Can be performed in parallel.

The above description is merely illustrative of the present invention, and those skilled in the art to which the present invention pertains may various modifications without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed herein are not intended to limit the present invention but to describe the present invention, and the spirit and scope of the present invention are not limited by these embodiments. It is intended that the scope of the invention be interpreted by the following claims, and that all descriptions within the scope equivalent thereto shall be construed as being included in the scope of the present invention.

As described above, according to the present invention, when about 189 Kbytes of storage space is used, the number of memory accesses shows an average of 1.93 times, at least 1 time, and at most 5 times. Accordingly, the present invention provides an excellent hardware structure and a retrieval method for retrieving an address through a small number of memory accesses while requiring a small amount of storage as a whole by using several small memories. In addition, since the address lookup table is configured in different SRAMs for each prefix of the IP address, there is an advantage in that a table update for adding and deleting new entries is easier than the method of configuring an address forwarding table in one memory.

Claims (22)

A method for retrieving an IP address using a hash table composed of an SRAM generated in a form in which entries are stored in a main table and an auxiliary table configured for each prefix length of an IP address, (a) hashing the addresses for each prefix length of the address using hash hardware configured for each prefix length of the input address; (b) comparing the prefix stored at the point indicated by the result of the hash of the main table with the prefix of the address, and comparing the entry of the main table with the prefix corresponding to the prefix of the address by the prefix length of the address. Searching for each and transmitting information of the matched entry; (c) if the matching prefix is not found, the auxiliary table having a prefix that matches the prefix of the address, starting from the point indicated by the pointer of the main table in the auxiliary table; Searching each entry of the table for each prefix length of the address and transmitting information of a matched entry; And (d) searching for an entry having the longest number of bits of the prefix among the entries searched for each prefix length of the address by using the information transmitted in the steps (b) and (c). IP address search method using the SRAM and hash, characterized in that it comprises a. The method of claim 1, And the hash hardware, the main table, and the auxiliary table are generated for each prefix length of the address. The method of claim 1, And the primary table and the auxiliary table are stored in one SRAM for each prefix length of the address. The method of claim 1, And searching the address simultaneously in parallel for each prefix length of the address. The method of claim 1, And the hash hardware performs an exclusive OR by combining the number of bits of the prefix by the number of bits desired to be produced as the result of the hash, and performing an exclusive OR. The method of claim 1, wherein in step (c), And searching the entry of the auxiliary table having a prefix that matches the prefix of the address by applying a binary search method. The method of claim 1, The entry of the primary table includes a prefix used for the search, a next hop address, an output port, a pointer to the auxiliary table, and a collision count corresponding to the entry, and the entry of the auxiliary table is a prefix used for the search. And a next hop address and an output port. The method of claim 1, The entry of the primary table includes a prefix used for the search, a pointer to a forwarding RAM, a pointer to the auxiliary table, and the number of collisions corresponding to the entry, the entry of the auxiliary table being used for the search. A prefix used for the IP address retrieval method using a hash and SRAM, characterized in that it comprises a pointer to the forwarding RAM. The method of claim 8, And the forwarding RAM comprises a next hop address and an output port. The method of claim 1, And the main table and the auxiliary table are stored in separate SRAMs for each prefix length of the address. The method of claim 1, Wherein the information of the matched entry includes a pointer to next hop address information and output port information or forwarding RAM. In the hardware structure for IP address retrieval using SRAM and hashing, Hash hardware for hashing the prefix of the input address; A main table in which entries are stored in the form of a hash table according to the prefix length of the address, and the prefix stored at the point indicated by the result of the hash of the main table and the prefix of the address are compared with the prefix of the address. A main processor for retrieving said entry of said main table having a matching prefix and transmitting information of a matched entry; An auxiliary table in which entries are stored in the form of hash tables according to the prefix length of the address, starting from the point indicated by the pointer of the main table in the auxiliary table, the auxiliary table having a prefix that matches the prefix of the address; A coprocessor for retrieving said entry of and transmitting information of a matched entry; And Priority encoder that receives the information of the matched entry and searches for an entry with the longest number of bits of the prefix among the entries found for each prefix length of the address. Hardware structure for IP address lookup using SRAM and hashing comprising a. The method of claim 12, And said hash hardware, said main table and said auxiliary table are generated for each prefix length of said address. The method of claim 12, And the main table and the auxiliary table are stored in one SRAM for each prefix length of the address. The method of claim 12, Wherein the address search is performed simultaneously in parallel for each prefix length of the address. The method of claim 12, And the hash hardware performs an exclusive OR by combining the number of bits of the prefix by the number of bits desired to be the result of the hash, and performing an exclusive OR. The method of claim 12, And the entry search of the auxiliary table having a prefix that matches the prefix of the address is searched by applying a binary search method. The method of claim 12, The entry of the primary table includes a prefix used for the search, a next hop address, an output port, a pointer to the auxiliary table, and the number of collisions corresponding to the entry, the entry of the auxiliary table being a prefix used for the search. Hardware architecture for IP address lookup using SRAM and hashing, comprising a next hop address and an output port. The method of claim 12, The entry of the primary table includes a prefix used for the search, a pointer to a forwarding RAM, a pointer to an auxiliary table, and a collision count corresponding to the entry, the entry of the auxiliary table being used for the search. The hardware structure for IP address retrieval using a hash and SRAM, characterized in that it comprises a prefix indicating the prefix, the forwarding RAM. The method of claim 19, And said forwarding RAM comprises a next hop address and an output port. The method of claim 12, And the main table and the auxiliary table are stored in separate SRAMs for each prefix length of the address. The method of claim 12, And the information of the matched entry includes a pointer to next hop address information and output port information or a forwarding RAM.