KR20040095990A - Image sensor with test circuit for analog digital converter - Google Patents

Abstract

PURPOSE: An image sensor comprising a test circuit of an ADC(Analog Digital Converter) is provided to remove an inconvenient process of directly radiating light on a pixel array by controlling the amount of light in various stages, thereby reducing a performance test time of an ADC. CONSTITUTION: A pixel array(201) generates an electric signal from an incident light. A CDS(Correlated Double Sampler)(202) outputs pure image information only by excluding noise components from the electric signal. A PGA(Programmable Gain Amplifier)(203) amplifies an output of the CDS(202) to output the amplified output. An ADC test signal supplier(204B) supplies an ADC test signal. The first selector(204A) transmits an output of the supplier(204B) or an output of the PGA(203). An ADC(205) inputs the output of the selector(204A), and converts into a digital signal. A test signal detector(204D) detects the output of the ADC(205). A DSP(206) finally outputs image information. The second selector(204C) transmits the output of the ADC(205) to the detector(204D) or the DSP(206).

Description

IMAGE SENSOR WITH TEST CIRCUIT FOR ANALOG DIGITAL CONVERTER}

The present invention relates to an image sensor, and more particularly, to an image sensor having an ADC test circuit capable of measuring the performance of an analog digital converter (hereinafter, referred to as an ADC).

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to each other. Complementary MOS image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

Such a CMOS image sensor or charge coupled device includes an ADC as a component to receive external light and produce image information using the same.

1 is a block diagram showing the overall configuration of a conventional image sensor having an ADC with reference to the configuration of the image sensor according to the prior art as follows.

The image sensor according to the related art is a pixel array 101 for generating an electric signal from light incident by gathering dozens or millions of unit pixels, and a correlation that outputs only pure image information excluding noise components among the electric signals generated in the pixel array. A Correlated Double Sampler (CDS) 102, a Programmable Gain Amplifier (PGA) 103 for amplifying and outputting the output of the correlated double sampler to a desired range, and the output of the Programmable Gain Amplifier. Digital signal processor (Digital Signal Processor (DSP) 105) that converts the analog signal into a digital signal and outputs it, and receives the output of the ADC and processes the signal and finally outputs the image information. have.

Since the image sensor receives light from the outside and generates image information using the light, it is difficult to directly measure the performance of each component constituting the image sensor. In particular, the ADC is one of the important components that determine the performance of the image sensor, but the performance of the ADC must be measured through a test, but in the past, since the output of the PGA is directly connected to the input of the ADC, the performance of the ADC In order to measure, the performance of the ADC had to be measured by irradiating light directly onto the pixel array.

In addition, in order to test performance over the entire output range of the ADC, there was a problem in that the amount of light emitted to the pixel array has to be adjusted in several steps.

As described above, the conventional image sensor must irradiate light directly to the pixel array and adjust the amount of light in several stages, but the accurate performance test of the ADC is possible, so that the test time is too long.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide an image sensor having an ADC test circuit capable of measuring the performance of an ADC without directly irradiating light to a pixel array.

1 is a block diagram showing a configuration of an image sensor according to the prior art;

2 is a block diagram showing a configuration of an image sensor having an ADC test circuit according to the present invention;

3 is a circuit diagram showing the configuration of the ADC test signal providing unit and the first selection unit in the image sensor according to an embodiment of the present invention;

4 is a signal diagram showing an output according to a control signal in the image sensor according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

201: pixel array 202: correlation double sampler

203: programmable gain amplifier 204A: first selector

204B: ADC test signal provider 204C: second selector

204D: test signal detector 205: analog digital converter

206: Digital Signal Processor

The image sensor of the present invention for achieving the above object, the pixel array for generating an electrical signal from the incident light; A correlated double sampler that outputs only pure image information excluding a noise component among electrical signals generated by the pixel array; A programmable gain amplifier for amplifying and outputting the output of the correlated double sampler to a desired range; An ADC test signal providing unit providing an ADC test signal; A first selector controlled by a test enable signal to transfer an output of the ADC test signal providing unit or an output of the programmable gain amplifier; An ADC which receives the output of the first selector and converts the digital signal into a digital signal; A test signal detector detecting an output of the ADC according to an ADC test signal; A digital signal processor which receives the output of the ADC according to the output of the programmable gain amplifier and processes the signal to finally output image information; And a second selector which is controlled by a test enable signal and transfers the output of the ADC to the test signal detector or the digital signal processor.

The present invention relates to an image sensor having an ADC test circuit capable of quickly testing the performance of the ADC without irradiating light to the pixel array by providing an ADC test circuit capable of testing the performance of the ADC at the front of the ADC. will be.

In addition, the present invention is equipped with an ADC test circuit that can measure the performance of various ADCs, such as overflow, underflow, differential nonlinearity (DNL), integral nonlinearity (INL), without irradiating light to the pixel array in multiple stages It relates to an image sensor.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

Figure 2 is a block diagram showing the configuration of an image sensor having an ADC test circuit in front of the ADC capable of measuring the characteristics of the ADC in accordance with the present invention.

Referring to FIG. 2, an image sensor according to an exemplary embodiment of the present invention includes a pixel array 201 that generates an electrical signal from light incident by gathering tens or millions of unit pixels, and a noise component among electrical signals generated from the pixel array. A correlated double sampler (CDS) 202 for outputting only pure image information excluding the PSA, a programmable gain amplifier 203 for amplifying and outputting the output of the correlated double sampler to a desired range; ADC test signal providing unit 204B for providing the ADC test signal, and a first selector 204A which is controlled by the test enable signal and delivers the output of the ADC test signal providing unit 204B or the output of the PGA 203. And an ADC 205 that receives the output of the first selection unit 204A, converts the digital signal into a digital signal, and outputs a test signal detector that detects the output of the ADC 205 according to the ADC test signal. A digital signal processor (DSP) 206 for receiving the output of the ADC 205 according to the output of the PGA 203 and processing the signal and finally outputting image information, and a test enable A second selector 204C which is controlled by the signal and delivers the output of the ADC 205 to the test signal detector 204D or the DSP 206.

In the image sensor according to the embodiment of the present invention having such a configuration, the ADC test signal providing unit 204B and the first selection unit 204A are added to the front of the ADC 205 to test the performance of the ADC. The test signal detector 204D and the second selector 204C are added to the output terminal of the ADC 205.

That is, in the image sensor according to the exemplary embodiment of the present invention, the output of the PGA 203 or the output of the test signal providing unit 204B is input to the ADC 205, and the output of the ADC is also the test signal detecting unit 204D or Delivered to DSP 206.

Referring to Figure 2 briefly described the operation of the image sensor according to an embodiment of the present invention.

First, in the test mode, the first selector 204A is connected to the ADC test signal provider 204B, and the second selector 204C is connected to the test signal detector 204D. Therefore, the test signal output from the ADC test signal providing unit 204B is used to measure the performance of the ADC, the output of the ADC 205 used for the test is input to the test signal detection unit 204D, the DSP 206 It is not entered.

Next, when not in the test mode, the first selector 204A is connected to the PGA 203 and the second selector 204C is connected to the DSP 206. Therefore, the output signal of the PGA 203 is input to the ADC 205 as it is, and the output of the ADC 205 is input to the DSP 206 and used for image reproduction.

The ADC test signal providing unit 204B selectively selects any one of a test power supply (+ V _DD , -V _DD ) and an analog test signal for measuring the overflow and underflow of the ADC 205 to the ADC 205. Having a configuration to apply, the configuration and operation of the ADC test signal providing unit 204B and the first selection unit 204A will be described in detail below.

Various test signals for testing the performance of the ADC 205 include analog test signals for measuring DNL (Differnt Nonlinearity) or INL (Integral Nonlinearity), and + for measuring the overflow of the ADC 205. V _DD , or -V _DD for measuring the underflow of the ADC 205, and the like are provided.

3 is a circuit diagram showing the configuration of the first selector 204A and the ADC test signal provider 204B together. The first selector 204A includes a switching element for selecting and outputting any one of an output of the ADC test signal providing unit 204B and an output of the PGA 203. The ADC test signal providing unit 204B includes various Comprising a plurality of switching elements for selectively outputting a test signal, each switching element is opened and closed in accordance with the control signal to apply a test signal to the ADC (205).

Before describing the detailed configuration of the ADC test circuit with reference to FIG. 3, the control signal for opening and closing each switching element and the direction of the arrow displayed on each switching element will be described first.

First, a test enable signal, a test mode signal, and a test flow signal are used as control signals for closing each switching element.

The test enable signal determines whether to perform a test operation or a normal operation.

The test mode signal determines whether to measure the ADC's overflow or underflow during test operation, or whether the ADC's differential nonlinearity (DNL) or integral nonlinearity (INL) is measured.

The test flow signal determines whether to measure the overflow or underflow of the ADC.

Next, the direction of the arrow displayed on each switching element will be described. When the above-mentioned control signals are activated, the direction of the arrow indicates opening and closing of the switching element accordingly.

For example, the case of the switching device SW11 and the switching device SW21 shown in FIG. 3 will be described below. The switching element SW11 and the switching element SW21 are opened and closed according to the test enable signal. When the test enable signal is activated, the switching element SW11 and the switching element SW21 are closed. When the test enable signal is inactive, the switching element SW11 and the switching element SW21 are switched. Element SW21 is opened. This operation is indicated in the direction of the arrow, and then the switching element SW11 will be referred to as SW11. Other switching elements will be denoted as well.

The configuration of the first selector 204A and the ADC test signal provider 204B according to an embodiment of the present invention will be described in detail with reference to the above.

First, the first selector 204A connects any one of the positive output terminal of the PGA and the positive output terminal of the ADC test provider 204B to the positive input terminal of the ADC, and the negative output terminal of the PGA and the ADC test provider 204B. It consists of SW21 which connects one of the negative output stages of < RTI ID = 0.0 >

The ADC test signal providing unit 204B has a SW13 connected between the positive output terminal and the positive test input terminal of the ADC test signal providing unit 204B, and one side of the positive output terminal of the ADC test signal providing unit 204B is connected in parallel with SW13. and SW14 and, SW15 and SW14 connected between the V _DD is connected to the stage, SW16 and SW14 connected between the ground terminal (GND) and the part constituting the ADC test signal supply unit (204B).

In addition, the ADC test signal providing unit 204B is connected between the SW23 connected between the negative output terminal and the negative test input terminal of the ADC test signal providing unit 204B, and one side of the ADC test signal providing unit 204B is connected in parallel. SW24 connected to the output terminal, SW25 connected between SW24 and ground terminal GND, and SW26 connected between SW24 and V _DD stages constitute the remainder of ADC test signal providing unit 204B.

In the first selector 204A and the ADC test signal providing unit 204B having such a configuration, SW11 and SW21 are opened and closed according to the test enable signal, and SW13, SW14, SW23 and SW24 are opened and closed according to the test mode signal. . In addition, SW15, SW16, SW25, and SW26 are opened and closed according to the test flow signal.

The switching element used in the embodiment of the present invention may be implemented as a transmission gate, and other switching means may be used.

Next, referring to FIG. 3, operations of the first selector 204A and the ADC test signal provider 204B according to an embodiment of the present invention will be described.

First, when the test enable signal is deactivated, since the normal operation is performed instead of the test operation, the positive output terminal of the PGA is connected to the positive input terminal of the ADC, and the negative output terminal of the PGA is respectively connected to the negative input terminal of the ADC. That is, when the test enable signal is deactivated, the SW11 and SW21 operate so that the output of the PGA is directly connected to the input of the ADC.

Next, when the test enable signal is activated, the output of the test signal providing unit 204B becomes an input of the ADC to perform a test operation. The test operation may be divided into three cases.

The first is a test operation to measure the differential nonlinearity (DNL) or the integral nonlinearity (INL) of the ADC. In this case, the SW13 and SW23 are closed as the test mode signal is activated, and the analog test input is input to the ADC. That is, the positive test input terminal is connected to the positive input terminal of the ADC, and the negative test input terminal is connected to the negative input terminal of the ADC.

The second is a test operation to measure the overflow of the ADC. In this case, + V _DD is applied to the ADC as the test mode signal is inactivated and the test flow signal is activated.

That is, as SW13, SW23, SW16, SW26 are opened and SW15 and SW25 are closed, V _DD is connected to the positive input terminal of the ADC, and ground terminal (GND) is connected to the negative input terminal of the ADC, resulting in + V _DD to the ADC. Can be applied to measure overflow.

Third, a test operation for measuring the underflow of the ADC, in which case the test mode signal is inactivated and -V _DD is applied to the ADC as the test flow signal is inactivated.

That is, as SW13, SW23, SW15, and SW25 are opened and SW16 and SW26 are closed, the ground terminal (GND) is connected to the positive input terminal of the ADC, and V _DD is connected to the negative input terminal of the ADC, resulting in -V to the ADC. _DD can be applied to measure the underflow of the ADC.

As described above, the ADC test circuit according to an embodiment of the present invention can measure not only a simple overflow underflow test to determine whether the ADC is operating but also a differential performance nonlinearity (DNL) or integral nonlinearity (INL), which is a representative performance measure of the ADC. Do.

2 shows a test signal detector 204D and a second selector 204C, which will be described below.

As described above, the second selector 203C is controlled according to the test enable signal. When the test enable signal is activated, the second selector 204C is connected to the test signal detector 204D, and the test in When the enable signal is deactivated, the second selector 204C is connected to the DSP 206.

The signal input to the test signal detector 204D is an output signal of the ADC 205 according to the test operation, and thus the performance of the ADC 205 can be grasped through the signal input to the test signal detector 204D.

FIG. 4 is a signal diagram illustrating signals input to an ADC according to a control signal in an image sensor according to an exemplary embodiment of the present invention, and illustrates an ADC input when the control signal is defined as being activated. It is a signal diagram.

The signal diagram shown in Fig. 4 shows the aforementioned test operation as it is. First, when the test enable signal is 'low' and deactivated, the output of the PGA becomes the input of the ADC.

Next, when the test enable signal is activated by being 'high', the test mode signal is disabled by being 'low', and when the test flow signal is activated by being 'high', + V _DD is input to the input of the ADC. Used for overflow measurements.

Next, the test enable signal becomes 'high' and is activated. When the test mode e signal and test flow signal are 'low' and activated, -V _DD is input to the ADC and used for underflow measurement.

Finally, when the test enable signal is activated by being 'high', the test mode signal is activated by being 'high', and when the test flow signal is 'low' and deactivated, the test input is input to the ADC and DNL (Differntial) It is used for the measurement of nonlinearity or INL (Integral Nonlinearity).

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

Application of the present invention to an image sensor can reduce the performance test time of the ADC by eliminating the troublesome work of directly irradiating the pixel array by adjusting the amount of light in several steps to test the performance of the ADC. .

Claims (5)

A pixel array that generates an electrical signal from incident light; A correlated double sampler that outputs only pure image information excluding a noise component among electrical signals generated by the pixel array; A programmable gain amplifier for amplifying and outputting the output of the correlated double sampler to a desired range; An ADC test signal providing unit providing an ADC test signal; A first selector controlled by a test enable signal to transfer an output of the ADC test signal providing unit or an output of the programmable gain amplifier; An ADC which receives the output of the first selector and converts the digital signal into a digital signal; A test signal detector detecting an output of the ADC according to an ADC test signal; A digital signal processor which receives the output of the ADC according to the output of the programmable gain amplifier and processes the signal to finally output image information; And A second selector which is controlled by a test enable signal and transfers the output of the ADC to the test signal detector or the digital signal processor Image sensor made, including. According to claim 1, The ADC test signal providing unit, And a plurality of switching means for providing a signal for measuring the overflow of the ADC, a signal for measuring the underflow of the ADC, and a signal for measuring the DNL or INL of the ADC. . The method of claim 2, wherein the programmable gain amplifier has a positive output terminal and a negative output terminal, the ADC has a positive input terminal and a negative input terminal, and the ADC test signal providing unit has a positive output terminal and a negative output terminal. The first selection unit, A first switching device for connecting one of the positive output terminal of the programmable gain amplifier and the positive output terminal of the ADC test signal providing unit with the positive input terminal of the ADC; And A second switching element connecting one of the negative output terminal of the programmable gain amplifier and the negative output terminal of the ADC test signal providing unit with the negative input terminal of the ADC; Image sensor comprising a. The method of claim 3, wherein The ADC test signal providing unit, A third switching device connected between the positive output terminal and the positive test input terminal of the ADC test signal providing unit; A fourth switching device connected in parallel with the third switching device and having one side connected to a positive output terminal of the ADC test signal providing unit; A fifth switching device connected between the fourth switching device and a V _DD stage; A sixth switching device connected between the fourth switching device and a ground terminal GND; A seventh switching device connected between the negative output terminal and the negative test input terminal of the ADC test signal providing unit; An eighth switching device connected in parallel with the seventh switching device and having one side connected to a negative output terminal of the ADC test signal providing unit; A ninth switching device connected between the eighth switching device and a ground terminal GND; And A tenth switching device connected between the eighth switching device and a V _DD stage; Image sensor comprising a. The method of claim 2, And said plurality of switching means comprises a transmission gate.