KR20040092741A - Delay Locked Loop with Synchronous Mirror Delay - Google Patents

Abstract

PURPOSE: A delay locked loop using synchronous mirror delay is provided to check locking of a clock in a synchronous mirror delay and to reset the synchronous mirror delay itself. CONSTITUTION: An input buffering unit(110) buffers an external clock. A delay monitoring unit(120) delays an output of the input buffering unit as much as skew to compensate. A forward delay array(330) controls time delay of an output clock from the delay monitoring unit in a forward direction according to an inputted measurement signal. A mirror control unit(340) outputs a clock whose time delay is controlled, by receiving an output of the forward delay array. A backward delay array(350) controls time delay in a backward direction by comparing an output of the mirror control unit with an output of the input buffer. And an output unit(160) outputs a delay locked loop clock signal by receiving an output of the backward delay array.

Description

Delay Locked Loop with Synchronous Mirror Delay

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay locked loop (DLL) of a semiconductor memory device, and more particularly, to a delay locked loop using a synchronous mirror delay (SMD).

Semiconductor memory devices (eg DDR SDRAM) repeat hundreds of cycles by the locking time (tLOCK) to compare the phase of the external and internal clocks to eliminate clock skew. As the operating voltage fluctuations and process margins are gradually decreasing, synchronous delay lines are introduced.

1 is a block diagram and timing diagram of a synchronization mirror delay according to the prior art.

This is disclosed in Patent 2000-29691 filed on May 31, 2000, by the applicant of the present invention. According to the prior art, the synchronous mirror delay delay monitor circuit (DMC, 120) for delaying the input buffer 110 for buffering an external clock and the output of the input buffer 110 by a skew to be compensated. And a forward delay array (FDA) 130 for receiving an output from the delay monitor circuit 120 and adjusting a time delay in a first direction, and an output and input of the forward delay array 130. Mirror control circuit (MCC) 140 for receiving the output of the buffer 110 so that the clock is input as much as the time delay is adjusted, and receives the output of the mirror control unit 140 in the second direction A backward delay array (BDA) 150 for adjusting the time delay, and an output unit 160 for receiving the output from the reverse delay array 150 and outputting a delay locked loop clock signal.Can be.

The internal clock can be synchronized with the external clock in only two clocks, but it has a disadvantage of limiting the unit delay jitter. However, reducing this lengthens the delay chain and increases the area consumption. Conventional register-controlled delay-locked loops are feedback circuits, so many clocks are required, while synchronous mirror delay (SMD) eliminates clock skew with two consecutive pulses (tLOCK). The forward delay array (FDA) 130 may have a single input and multiple outputs. In contrast, the reverse delay array (BDA) 150 may have a single output and multiple inputs. The forward delay array (FDA) 130 and the reverse delay array (BDA) 150 may have a forward delay time tDF and a reverse delay time tDB, respectively. Accordingly, the forward delay array (FDA) 130 and the reverse delay array (BDA) 150 may be located in parallel to each other but operate in opposite directions. This is to make the circuit simple and small, the output of the forward delay array (FDA) and the input of the reverse delay array (BDA) may be connected to each other through the mirror control unit 140.

FIG. 2 is a detailed circuit diagram of the synchronous mirror delay of FIG. 1.

The synchronous mirror delay includes an input buffer 110 for receiving an external clock, a delay unit 120 for delaying the output of the input buffer 110, and a forward delay array for receiving a delayed clock output from the delay unit 120. 130, a mirror controller 140 for receiving the output of the forward delay array 130 and the output of the delay unit 120, a reverse delay array 150 for receiving the output of the mirror controller 140, and a reverse delay. An output terminal 160 for receiving and outputting the output of the array 150 may be provided.

In detail, the forward delay array 130 may include a NAND gate 131 receiving the output of the delay unit 120 and a power supply voltage and an inverter 132 receiving the output of the NAND gate 131. The second stage may include a NAND gate 133 that receives an output of the inverter 132 and a power supply voltage, and an inverter 134 that receives an output of the NAND gate 133, and a third stage of the inverter 134. The NAND gate 135 may receive an output of the NAND gate 135 and an inverter 136 may receive an output of the NAND gate 135. The configuration of the third stage can be connected in series with a plurality of stages to form multiple stages.

The mirror controller 140 may include a plurality of NAND gates that receive an output of an inverter of each stage of the forward delay array 130 and an output of the delay unit 120.

The reverse delay array 150 may include a NAND gate that receives the output of the mirror controller 140 and an output of the inverter of the previous stage, and an inverter that receives the output of the NAND gate.

The output stage 160 may include an even number of inverters receiving the output of the final stage of the reverse delay array 150.

Each unit delay element consists of one inverter and a NAND gate, and the reverse delay array 150 is a mirror image of the layout of the forward delay array 130 and the mirror controller 140 regardless of process conditions or voltage fluctuations. The delay can be designed to match.

The clock passing through the forward delay array 130 is delayed by the forward delay time tDF and finally delayed by one clock cycle. In this case, since the clock signal delayed through the forward delay array 130 and the external clock have in-phase, it can be found that N becomes td + NtDF = tCLK. Therefore, the delay array is activated up to the Nth stage and these activation signals will be delivered to the reverse delay array 150. If tDF (forward delay time) = tDB (reverse delay time), the backward delay array 340 also operates only up to the Nth stage according to the forward delay array 130 value, so that the total delay of the reverse delay array 150 is tCK-td. Will be. Accordingly, the total delay experienced by the external clock is represented by the following equation 1 when the delay time in the input buffer 110 is d1 and the time delay in the output terminal 160 is d2.

d1 + tCLK + (tCLK-d1-d2) + d2 = 2 tCLK

That is, the clock can be locked in only two clocks in the synchronous mirror delay. However, in the conventional circuit as shown in Fig. 2, there is no method of actually confirming the locking of the clock, and no method of resetting in the synchronous mirror delay itself. Therefore, there has been a problem in that an external clock must be reset to be newly input.

In order to solve the above problem, an object of the present invention is to determine the locking of a clock in a synchronous mirror delay and to reset the synchronous mirror delay itself.

1 is a block diagram and a timing diagram of a synchronous mirror delay according to the prior art;

2 is a detailed circuit diagram of the synchronous mirror delay of FIG. 1;

3 is a detailed circuit diagram of a synchronous mirror delay according to the present invention;

4 is a timing diagram of each part of FIG. 3.

Description of the main parts of the drawing

110: input buffer 120: delay monitor circuit

130, 330: forward delay array 140, 340: mirror control unit

150, 350: reverse delay array 160: output

A delay locked loop using a synchronous mirror delay of the present invention for achieving the above object comprises: an input buffering means for buffering an external clock in a semiconductor memory device; Delay monitoring means for delaying the output of the input buffering means by the amount of skew to be compensated for; A forward delay array for adjusting a time delay in the forward direction of the output clock from the delay monitoring means according to an input measurement signal; Mirror control means for receiving an output of the forward delay array and outputting a clock having a time delay adjusted; A reverse delay array for receiving and comparing the output of the mirror control means and the output of the input buffer and adjusting the time delay in the reverse direction; And output means for receiving the output from the reverse delay array and outputting a delay locked loop clock signal.

Preferably, the forward delay array of the present invention includes a plurality of forward unit delay units connected in series, and a first forward unit delay unit for receiving an external clock output from the delay monitoring means among the plurality of forward unit delay units; A first NAND gate configured to receive an external clock from the delay monitoring means and the measurement signal; And a second NAND gate outputting a value corresponding to an output of the forward unit delay unit by using the output of the first NAND gate and the ground voltage as inputs.

Preferably, the mirror control means of the present invention includes a plurality of mirror control unit for receiving and processing the output of each forward unit delay unit in the forward delay array, wherein the first mirror control unit of the plurality of mirror control unit, A first transistor controlled by the output of the second NAND gate to apply the voltage of the first voltage terminal connected to one end to the other end; A first inverter having the other end of the first transistor as an input; A second transistor controlled by a reset signal for resetting an input synchronous mirror delay to apply the voltage of the first voltage terminal connected to one end to the other end; A second inverter having the other end of the second transistor as an input and connected in reverse parallel with the first inverter; A third inverter in the second mirror control unit adjacent to the output of the second inverter and the plurality of mirror control units, wherein the third inverter corresponds to the first inverter of the first mirror control unit; can do.

Preferably, the reverse delay array of the present invention includes a plurality of serially connected reverse unit delay units, and one of the plurality of serially connected reverse unit delay units, the reverse unit delay unit, the output of the Noah gate and the A third NAND gate having an output of the input buffer as an input; A fourth NAND gate configured to receive an output of the first inverter and an output from a reverse unit delay part of a previous stage; And a fifth NAND gate having an output of the third NAND gate and an output of the fourth NAND gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

3 is a detailed circuit diagram of a synchronous mirror delay according to the present invention, and FIG. 4 is a sub timing diagram of FIG. 3.

First, when the reset signal Reset of the "H" state is applied to the SMD, the si (s1, s2, s3, ...) nodes transition to the "H" state, and ri (r1, r2, r3, ... The node transitions to the "L" state. When the measurement signal "meas" in the "H" state is applied for one clock tCLK, the external clock passes through the delay unit 120 through the input buffer 110 and enters the forward delay array 330. If the measurement signal (meas) is in the "L" state when reaching the m4 through the nodes m0, m1, m2 and m3 in the forward delay array 330, the external clock stops without further progressing. At this time, the nodes s1, s2, s3, and s4 are all in the "L" state, and the remaining nodes s5, s6, ... are all in the "H" state. The ri node has the opposite logic state as the si node, and the pi node goes to the "H" state when the si node is in the "L" state, and then the r (i + 1) node of the next stage transitions to the "H" state. Is deactivated. Therefore, only the p4 node maintains the "H" state, and after the measurement signal (meas) becomes the "L" state, the external clock passing through the input buffer 110 through the gate connected to p4 is the reverse delay array 350 Enter). Thereafter, the clock intclk passing through the nodes t3, t2, t1, and t0 in the reverse delay array 350 via the output terminal 160 may be aligned with an external clock.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto and is intended by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

The present invention, which can have the configuration as described above, enables the locking of the clock in the synchronous mirror delay, and the synchronous mirror delay can not be reset only when a new external clock is entered, but also directly reset in the synchronous mirror delay itself. Has the beneficial effect of being able to.

Claims (4)

In a semiconductor memory device, Input buffering means for buffering an external clock; Delay monitoring means for delaying the output of the input buffering means by the amount of skew to be compensated for; A forward delay array for adjusting a time delay in the forward direction of the output clock from the delay monitoring means according to an input measurement signal; Mirror control means for receiving an output of the forward delay array and outputting a clock having a time delay adjusted; A reverse delay array for receiving and comparing the output of the mirror control means and the output of the input buffer and adjusting the time delay in the reverse direction; And Output means for receiving an output from the reverse delay array and outputting a delay locked loop clock signal; A delay locked loop using a synchronous mirror delay, characterized in that it comprises a. The method of claim 1, wherein the forward delay array, A first forward unit delay unit including a plurality of forward unit delay units connected in series and receiving an external clock output from the delay monitoring unit among the plurality of forward unit delay units; A first NAND gate which receives an external clock from the delay monitoring means and the measurement signal; And A second NAND gate that outputs a value corresponding to an output of the forward unit delay unit by inputting the output of the first NAND gate and the ground voltage; A delay locked loop using a synchronous mirror delay, characterized in that it comprises a. The method of claim 2, wherein the mirror control means, A plurality of mirror control unit for receiving and processing the output of each forward unit delay unit in the forward delay array, Among the plurality of mirror control unit, the first mirror control unit, A first transistor controlled by the output of the second NAND gate to apply the voltage of the first voltage terminal connected to one end to the other end; A first inverter having the other end of the first transistor as an input; A second transistor controlled by a reset signal for resetting an input synchronous mirror delay to apply the voltage of the first voltage terminal connected to one end to the other end; A second inverter having the other end of the second transistor as an input and connected in reverse parallel with the first inverter; Noah gate as an input of an output of the second inverter and an output of a third inverter in an adjacent second mirror controller of the plurality of mirror controllers, wherein the third inverter corresponds to the first inverter of the first mirror controller A delay locked loop using a synchronous mirror delay, characterized in that it comprises a. The method of claim 3, wherein the reverse delay array, A plurality of serially connected reverse unit delay units, one of the plurality of serially connected reverse unit delay units, A third NAND gate having an output of the noah gate and an output of the input buffer; A fourth NAND gate configured to receive an output of the first inverter and an output from a reverse unit delay part of a previous stage; And A fifth NAND gate having an output of the third NAND gate and an output of the fourth NAND gate; A delay locked loop using a synchronous mirror delay, characterized in that it comprises a.