KR20040089556A - Method and apparatus for capturing and using design intent in an integrated circuit fabrication process - Google Patents

Abstract

PURPOSE: A method and a device for capturing a design intention on an IC manufacturing process and optimizing the manufacturing process by using the same are provided to use design intention information to optimize the manufacturing process in order to optimize a critical feature designed from a designer by producing the design intention information with design distributions from a design company. CONSTITUTION: The design company(108) captures the design intention used during a design process by developing the design distributions, and produces the design distributions by a path(120) and the design intention information(202). The design intention information is connected to an equipment maker(130) or an IC manufacturing equipment(122) after the equipment is installed. The design intention information is used in the equipment by optimizing the IC manufacturing process in order to obtain a specified design standard confirmed as a decisive factor in the design intention information. The design intention information of a manufacturing capacity information format is transferred to the design company from the equipment maker and/or the IC manufacturing equipment.

Description

TECHNICAL AND APPARATUS FOR CAPTURING AND USING DESIGN INTENT IN AN INTEGRATED CIRCUIT FABRICATION PROCESS}

The present invention claims the benefit of US Provisional Patent Application No. 60 / 462,393, filed April 11, 2003, which application is incorporated herein by reference.

The present invention relates to integrated circuit (IC) fabrication processes and techniques. More specifically, the present invention relates to methods and apparatus for capturing and using design intent in IC fabrication processes.

Modern integrated circuit (IC) design and fabrication processes are complex and require input from many entities. In general, design companies prepare integrated circuit designs, which are then distributed to IC manufacturing facilities, where the distributed IC manufacturing equipment uses integrated circuit fabrication equipment in a manner defined by the design distribution to produce integrated circuits. do. In many cases, the design distribution captures the specific layout of the integrated circuit, but not the designer's design intent. Because design intent involves a variety of parameters other than simply the physical layout of the circuit elements, for example design intent is a guideline, among other things, in close proximity to standards such as circuit yield, speed and power consumption, and timing closure. It includes. Thus, even if the physical arrangement of circuit elements has been correctly converted from design to fabrication, it is not a confirmation that the fabricated IC necessarily implements all the parameters of the designer's intent. By itself, the important aspects of integrated circuits considered by the designer are not tested, nor are they considered important by the IC manufacturing facility during IC fabrication. As a result, the IC may not work as intended by the designer.

1 shows a block diagram of an IC fabrication process. Process 100 is divided into circuit design step 102 and circuit fabrication step 104. Equipment 106 is provided to circuit fabrication step 104 to facilitate fabrication of the IC. In the circuit design step 102, the designer 108 uses the electronic design automation (EDA) tool 110 and the component macro module 112 to design the integrated circuit. EDA tools that depend on the description file 114 and the component macro module 112 will rely on the description file 116. Component macro module 112 includes a plurality of macros, where each macro defines a particular type of integrated circuit, such as static random access memory (SRAM), memory management unit (MMU), and other standard logic circuits. The technical file 114 or 116 used to support the design is augmented with circuitry and transistor models and model parameters provided by the IC manufacturing facility 122. These models are developed and tested using transformations to ensure that physical devices have theoretically desired electrical characteristics. These models are created using physical derivation and empirical analysis to correlate measurable physical features to design or performance requirements. One such model form for modeling transistors is the SPICE model. Other models can be used to model photolithography, interconnect structures, and the like. Facility 122 provides this information so that macros are developed to be optimized for the equipment of a particular facility. By itself, component macros are developed and provided to the design firm at no cost. Macro developers are not directly paid for their component macros, but are paid on a royalty basis as each integrated circuit using such macros is produced by an IC manufacturing facility. Optionally, access fees may be charged to such component macros.

The ultimate design distribution is a layout that uses a plurality of component macros and other logic circuits that interconnect the components to form an integrated circuit. The design distribution is sent to IC manufacturing facility 122 along path 120.

To fabricate an integrated circuit, the IC fabrication facility 122 includes an EDA tool 124 that uses the design distribution to produce a mask for fabrication of the integrated circuit, a wafer fabrication center 126 that uses such a mask, , Equipment provided by the equipment manufacturer 130 along the path 128. Optionally, EDA tool 124 may be used in a facility other than an IC manufacturing facility. Equipment manufacturer 130 provides fabrication tool 132, method 134 of using tool 132, and various metrological equipment 136, which are used together to fabricate and test wafers and circuits. Test results can be used to optimize the integrated circuit fabrication process performed by the fabrication tool 132.

IC fabrication facility 122 uses the equipment provided on path 128 to fabricate the mask and ultimately to fabricate the integrated circuit.

As discussed above, various transistor models, parasitic capacitance models, and model parameters are provided from the IC fabrication facility 122 to the circuit design step 102 as description files 114, 116. This feedback of the model and model parameters enables the design firm to produce transistor designs that can be fabricated by the IC manufacturing facility 122.

The integrated circuit produced by the IC manufacturing facility must meet the design specifications that the design company tried to obtain from the design distribution. However, while IC design regards IC dimensions as absolute and invariant, the physical characteristics of integrated circuits are generally statistical in nature, so that the design firm never achieves the exact physical characteristics that were designed. Statistical properties of physical properties (such as layout) cause statistical variations in the electrical properties of integrated circuits. Moreover, design firms may have critical characteristics (eg, critical areas or critical passages) where integrated circuits have been designed around them and manufacturing facilities do not know and consider these critical characteristics when fabricating ICs. As a result, IC manufacturing facilities ultimately produce integrated circuits that are not optimized for these critical characteristics.

Therefore, integrated circuits produced in a factory by capturing and using designers' design intent in the technical field need to be optimized using this design intent.

1 is a block diagram of components of an integrated circuit fabrication process according to the prior art.

2 is a block diagram of components of an integrated circuit fabrication process in accordance with the present invention.

3 is a block diagram of a general layout of a semiconductor integrated circuit fabrication facility.

4 is a block diagram of the equipment layout, using design intent information when the metrological equipment is operating.

5 is a flow chart of a process for using design rules within an integrated circuit fabrication process.

6 is a flow diagram of an example method for generating a design rule.

<Explanation of symbols for the main parts of the drawings>

100: IC manufacturing process 102: circuit design step

104: circuit fabrication step 106: equipment

108: Design Company 110124: EDA Tools

112: Component macro model 114,116: Description file

122: manufacturing facility 126: wafer fabrication center

130: Equipment Manufacturers 132: Production Tools

134: how to use 136: metrological equipment

202: Design Intent Information 204: Mask Manufacturing

206: Wafer Fabrication

The present invention provides a method and apparatus for capturing and using design intent within an IC fabrication process. Design intent information is produced by the design company along with the design distribution. The design distribution and design intent information are linked to the IC fabrication facility, where the design distribution is used to generate the layout of the integrated circuit, and the design intent information is linked to equipment in the IC fabrication facility, in particular metrological equipment. As such, design intent information can be used to optimize the process during IC fabrication to obtain optimization of critical characteristics intended by the designer. Thus, parameters defined by the circuit designer, such as circuit yield, speed, power consumption, etc., are substantially achieved within the fabricated circuit.

In one embodiment of the present invention, design intent information includes identification of specific critical components in the integrated circuit that must be focused by metrological equipment to ensure that certain critical characteristics are achieved during fabrication. In another embodiment of the invention, the design intent to achieve the optimization of the longest speed path within one integrated circuit is connected to the equipment so that the metrological equipment can monitor critically important locations and threshold values of the longest speed path. To ensure that the integrated circuit operates as characterized by the design firm. In yet another embodiment, specific design rules may be developed by the equipment manufacturer to optimize certain types of circuits in the equipment. These design rules are linked to the design firm, who in turn inserts these design rules into the component macro module or other component model to ensure that the particular structure developed by the macro takes into account the design rule requirements of the equipment manufacturing performance. . Models and macros will contain manufacturing capability information, which is related to the equipment that will be used to produce the IC. As such, when these macro modules are used to design components in an integrated circuit, the equipment in the IC fabrication facility automatically considers the design rule parameters and optimizes the circuit fabrication process or layout. Payment for the design rules is simultaneously paid when the component macro module designer is paid (ie when loyalty is paid for an integrated circuit produced at the factory).

In a way that the above-described features of the present invention can be achieved and understood in more detail, a more detailed description of the invention is made with reference to their embodiments, which are briefly summarized above and described in the accompanying drawings.

It should be noted, however, that the appended drawings illustrate only typical embodiments of the invention and are not to be considered as limiting the scope of the invention, as the invention may permit other embodiments that are equally effective.

2 shows a block diagram of an integrated circuit fabrication process 200 in accordance with the present invention. Process 200 includes design firm 108, IC manufacturing facility 122 and equipment manufacturer 130 as discussed with respect to FIG. 1. In accordance with the present invention, design firms capture design intent used during the design process while developing a design distribution. The design company produces the design distribution along the path 120 and design intent information 202. Design intent information 202 is connected to equipment manufacturer 130 or IC manufacturing facility 122 after the equipment is installed. Design intent information 202 may be processed (eg, filtered or optimized) before being used in an IC manufacturing facility. The design intent information is supplied by the device manufacturer 130 to optimize the IC fabrication process (mask and wafer fabrication 204 and 206) to obtain specific design criteria identified as critical within the design intent information 202. Will be used by the equipment. In another embodiment described below with respect to FIG. 5, design intent information in the form of manufacturability information is also communicated from equipment manufacturer 130 and / or IC manufacturing facility 122 to design company 108.

3 shows a general arrangement 300 of IC fabrication equipment supplied by equipment manufacturer 130 using design intent information in accordance with the present invention. Equipment arrangement 300 includes a controller 302 and processing equipment 304. The controller 302 includes a central processing unit (CPU) 306, a support circuit 308, and a memory 310. The CPU 306 is typically a micro-controller that operates according to instructions stored in one or more processors, microprocessors, or the memory 310. Support circuit 308 is a well known support circuit including a cache, a power supply, a clock circuit, an input / output interface circuit, and the like. Memory 310 includes random access memory, read-only memory, erasable memory, disk drive, or a combination thereof. Memory 310 stores various types of software, including equipment control software 312 and design intent parameters 314. When the controller 302 executes the equipment control software 312, it transmits a control message along the path 316 to the various process equipment 304 in the IC manufacturing facility 122 of FIG. 1. Process equipment 304 may include deposition equipment, etching equipment, polishing equipment, metrological equipment, lithographic equipment, and the like.

Within an IC manufacturing facility, there may be one or more controllers that control various combinations of processing equipment. When controlling process equipment 304, design intent parameters 314 are used within equipment control software 312 to ensure that the process equipment operates in a manner where the design intent information supplied by the designer is met. . Essentially, design intent information is supplied to the controller to facilitate the creation of design intent parameters 314 that inform the processing tool what the processing tool should do to optimize the product. This information is supplied to the equipment manufacturer and the tool is designed to facilitate the use of design intent information. Design intent information may be processed (eg, filtered or optimized) to generate the parameter 314. Additionally or alternatively, design intent information for a particular design is supplied to the IC manufacturing facility along with the design distribution, allowing the facility to optimize the integrated circuit fabrication process.

4 shows a block diagram of one embodiment of the present invention using design intent information in metrological equipment. Equipment arrangement 400 includes a controller 302, processing equipment 402, and metrological equipment 406. Processing apparatus 402 includes one or more integrated circuit fabrication process tools, including etching reactors, deposition reactors, chemical-mechanical polishing (CMP) equipment, lithography equipment, and the like. The controller 302 controls the processing equipment in a conventional manner along the path 410 using equipment control software. Additionally, controller 302 supplies design intent information to metrological equipment 406 along path 408. This information allows metrological equipment 406 to optimize the testing of the wafer as produced by processing equipment 402 in terms of design intent information.

For example, if an SRAM module is to be fabricated on a particular integrated circuit being fabricated by the processing equipment 402, the SRAM module has a critical dimension requirement to balance the NMOS and PMOS transistors. Design intent information indicates that a particular part number (eg, SRAM part number) is generated by the processing equipment 402. The part number may be applied to a database, such as a lookup table (LUT) 412 that represents the specific test parameters that may be used to test the particular SRAM module being manufactured. Because the SRAM is identified as a critical component of the IC, metrological equipment focuses testing on these components. For example, a linewidth test can be performed near the location of the SRAM. Although the LUT 412 is shown as being located within metrological equipment, those skilled in the art will appreciate that the LUT 412 may be located at the controller 302 or elsewhere (eg, via a LAN or WAN).

Such metrological instruments that are flexible enough to perform tests on demand include TRASFORMA metrological instruments manufactured by Applied Materials, Inc. of Santa Clara, California. By identifying part numbers for modules used on integrated circuits, metrological equipment can use test parameters that are optimized to ensure, for example, that NMOS and PMOS transistors are balanced. As such, certain metrological tests will be performed on the critical dimensions of the NMOS and PMOS transistors of the SRAM module. The test may also be used to optimize the processing of the wafer during fabrication, or may be used to optimize the mask generation process, where, for example, mask trimming may be optimized in terms of the measurements made by the metrological equipment.

In another embodiment of the present invention, the designer identifies the longest speed path in the logic circuit on the integrated circuit as design intent information. This longest speed path is identified by the critical characteristics of the integrated circuit. Design intent information is passed to metrological equipment 406 to ensure that the test is performed to obtain the optimization of the longest speed path. As such, metrological equipment 406 will be instructed to monitor the critical dimensions of the circuit components and lines along the longest speed path. The measurements made by metrological equipment 406 may be matched with a database of information (DB) 414 to ensure that the parameters of the longest path and critical dimensions are met by the processing equipment. Such metrology may be performed by comparing an image of an ideal line or transistor stored in a database with a measured or captured line or transistor generated by processing equipment 402. The comparison results can be used to control the processing equipment 402 to achieve ideal line and / or transistor structures that provide optimal long path performance.

5 shows a flowchart of a process 500 for using a design rule to capture designer's design intent information. In certain cases, semiconductor wafer processing equipment is optimally performed when the integrated circuit layout has been created in a particular method or manner. For example, in order to control dishing when using chemical-mechanical polishing (CMP) equipment, a dummy structure, such as a plurality of conductive pieces, is positioned near conductive lines in an integrated circuit. In other cases, these design rules or models may be circuit structures, special processing recipes, component models, and so forth. In step 502, the equipment manufacturer creates a design rule DR, such as a design rule for CMP polishing, which may include the need for a dummy structure along a line of a particular length. The design rule may include manufacturing capability information that informs the designer when design parameters exceed the performance of the manufacturing equipment. In this case, the designer can be informed of any balance between yield and performance, which results from using the proposed design parameters.

6 illustrates an example method for generating design rules used by method 500. The method 600 is performed by at least one of an IC manufacturing facility, an equipment manufacturer, a device designer, or a third party not associated with them. The method 600 begins at step 602, where a list of equipment to be used or used in this step is generated by the IC manufacturing facility. In step 604, performance characteristics of the listed equipment are identified. In step 606, a design rule is generated in which the device will be fabricated, taking into account the particular listed equipment and the performance characteristics of that equipment (eg, performance thresholds). Generation of design rules is facilitated by the device module 610 used in step 606. These device modules are developed using physical derivation and empirical analysis. Depending on the design rules generated, the module may include a SPICE model, a photoresist mask model, an interconnect structure model, and the like. These models correlate measurable physical characteristics to design or performance requirements. At step 608, the method 600 outputs a design rule.

Returning to the method 500 of FIG. 5, a design rule is given to the component macro designer at step 504, which incorporates the design rule into the macro. The macro automatically adds the appropriate dummy structure to the layout when used by the designer to achieve optimal line production when using the equipment. In other applications, the designer may use a specific model, or use the embedded specific process recipe to optimize the circuit design for a particular set of equipment.

For example, manufacturing capability information in design rules may provide a process model for IC manufacturing equipment to be used to manufacture the IC. These process models allow a comparison of yield versus performance, allowing designers to choose the level of balance between yield and performance. Additionally, in terms of manufacturability information, designers can change design attributes such as floor plans, RTL codes, layouts, routing, line widths, number and location of holes, layer thicknesses, and the like. Manufacturing capability information enables the development and use of statistical sets based on models of design and validation models or rules that operate in three dimensions, such as the position of the substrate, the width of the shape and the thickness of the shape. Process models that include such manufacturing capability information may be formed for equipment that performs CMP, lithography, etching, plating, chemical and physical vapors, deposition, oxidation, and the like.

In step 506, design rules are used to design the integrated circuit, such as when the designer selects a particular structure from a macro library in which the structure will automatically follow the design rules.

At step 508, the IC design is passed to an IC manufacturing facility. In step 510, for each IC created using a macro containing design rules, royalties are paid to the IP company for the macros and to the equipment manufacturer for the use of the design rules. Optionally, the equipment manufacturer may be paid for access to design rules or other forms of royalties.

Manufacturing capability information can be generated for the model by performing an EDA test at the equipment manufacturer's facility. In general, EDA tests are completed at the equipment manufacturer's facility, and models can be generated using EDA data by the EDA company or equipment manufacturer. As such, the model is produced and distributed to the designer prior to the IC manufacturing facility having the equipment. The designer can therefore design the IC using the model of the equipment manufacturer and require the IC manufacturing facility to use the equipment specified in the design. Since the model is closely tied to a sub-model of a particular equipment (e.g., a specific etch reactor, a specific deposition reactor, etc.), the statistical distribution of physical properties allows the designer to design the IC without the model based on manufacturing capability information (i.e. The design is more stringent than the design of unknown equipment used by IC manufacturing facilities. By designing with the particular submodel under consideration, the granularity of the design parameters is reduced, allowing the design to produce ICs with very high performance, reproducibility and yield.

While various embodiments of the invention have been described above, other embodiments of the invention can be considered without departing from the basic scope thereof, and the scope of the invention is determined by the following claims.

The present invention provides a method and apparatus for capturing and using design intent within an IC fabrication process. Design intent information is produced by the design company along with the design distribution. Design intent information can be used to optimize the process during IC fabrication to obtain optimization of critical characteristics intended by the designer. Thus, parameters defined by the circuit designer, such as circuit yield, speed, power consumption, etc., are substantially achieved within the fabricated circuit.

In one embodiment of the present invention, design intent information includes identification of specific critical components in the integrated circuit that must be focused by metrological equipment to ensure that certain critical characteristics are achieved during fabrication. In another embodiment of the invention, the design intent to achieve the optimization of the longest speed path within one integrated circuit is connected to the equipment so that the metrological equipment can monitor critically important locations and threshold values of the longest speed path. To ensure that the integrated circuit operates as characterized by the design firm. In yet another embodiment, specific design rules may be developed by the equipment manufacturer to optimize certain types of circuits in the equipment. These design rules are linked to the design firm, who in turn inserts these design rules into the component macro module or other component model to ensure that the particular structure developed by the macro takes into account the design rule requirements of the equipment manufacturing performance. . When these macro modules are used to design components in an integrated circuit, the equipment in the IC manufacturing facility automatically considers the design rule parameters and optimizes the circuit manufacturing process or layout.

Claims (48)

As a method of manufacturing an integrated circuit, Capturing design intent information of the integrated circuit designer regarding the design distribution; Communicating the design intent information and the design distribution to an integrated circuit manufacturing facility; Using the design intent information in integrated circuit fabrication equipment of the integrated circuit fabrication facility to optimize the design distribution and the integrated circuit produced in accordance with the design intent. The method of claim 1, wherein the design intent information comprises at least one location of a critical circuit element. The method of claim 1, wherein the design intent information includes identifying critical circuit elements in the integrated circuit. The method of claim 1, wherein the design intent information comprises at least one circuit property selected from the group consisting of specifications of yield, speed, and power consumption. The method of claim 2, wherein the at least one location is measured by metrology equipment in the integrated circuit manufacturing equipment. 3. The method of claim 2 wherein the critical circuit element is measured by metrological equipment in the integrated circuit manufacturing equipment. 3. The method of claim 2, wherein the design intent information includes the location and critical dimensions of a particular conductive line in the integrated circuit. 8. The method of claim 7, wherein the location and critical dimensions are used by metrological equipment in the integrated circuit manufacturing equipment. The method of claim 1, wherein the design intent information includes equipment usage information provided to the integrated circuit designer by an integrated circuit manufacturing equipment manufacturer. 10. The method of claim 9, wherein the equipment usage information is a design rule that defines an optimal circuit configuration formed by the integrated circuit manufacturing equipment. The method of claim 10, wherein the design rule identifies where to place a dummy structure to prevent dishing when using a chemical-mechanical polishing tool for fabricating an integrated circuit. . 10. The method of claim 9 wherein the equipment usage information includes manufacturing capability information. An apparatus for manufacturing an integrated circuit, Integrated circuit manufacturing equipment comprising at least one metrological equipment for inspecting the structure of the integrated circuit; A design intent information source connected to the at least one metrological equipment, wherein a comparison between the design intent information and at least one attribute obtained from a portion of the integrated circuit being manufactured is used to control the integrated circuit manufacturing equipment. Source Apparatus for manufacturing an integrated circuit comprising. The apparatus of claim 13, wherein the design intent information source comprises a database of critical elements located on the integrated circuit. 15. The apparatus of claim 14, wherein the design intent information source comprises a look-up-table of critical elements located on the integrated circuit. As a business method for manufacturing an integrated circuit, Creating design rules for the integrated circuit processing tool, Using the design rules to develop an integrated circuit defined by a design distribution; Sending the design distribution to an integrated circuit fabrication facility using the integrated circuit circuit processing tool; Fabricating an integrated circuit in accordance with the design distribution; In response to a comparison between a design intent and attributes obtained from a portion of the integrated circuit being fabricated, adjusting the fabrication step performed by the integrated circuit processing tool; For each integrated circuit fabricated using the design rule, paying a royalty to the integrated circuit equipment manufacturer from the integrated circuit fabrication facility. 17. The method of claim 16 wherein the design rule defines an optimal location for a circuit element on the integrated circuit. 17. The method of claim 16, wherein the design rule defines the location of a dummy structure relative to a circuit element on the integrated circuit. The method of claim 16, wherein the design rule is generated by at least one of an integrated circuit equipment manufacturer, the integrated circuit manufacturing facility, and a third party not associated with the equipment manufacturing facility. The method of claim 16, wherein the generating step, Generating a list of equipment to be used and / or to be used by the integrated circuit manufacturing facility; Identifying performance characteristics of the listed equipment; Generating the design rule using the performance characteristics of the listed equipment and a device model of an integrated circuit structure defined by the design rule. As a method of improving an integrated circuit (IC) manufacturing method, Capturing manufacturing capability information for the integrated circuit manufacturing equipment; Incorporating the manufacturing capability information into design rules for designing an integrated circuit (IC); Capturing the design intent information of the integrated circuit designer about the design distribution; Including the manufacturing capability information as part of the design intent information; Communicating the design intent information and the design distribution to an integrated circuit manufacturing facility; Using the design intent information through the integrated circuit manufacturing equipment of the integrated circuit manufacturing facility to optimize the integrated circuit in accordance with the design distribution and the design intent. How to improve it. 22. The method of claim 21 wherein the design intent information includes at least one location of critical circuit elements. 22. The method of claim 21 wherein the design intent information includes identifying critical circuit elements in the integrated circuit. 22. The method of claim 21, wherein the design intent information includes at least one circuit attribute selected from the group consisting of specifications of yield, speed, and power consumption. 23. The method of claim 22, wherein the at least one location is measured by metrological equipment in the integrated circuit manufacturing equipment. 23. The method of claim 22, wherein the critical circuit element is measured by metrological equipment in the integrated circuit manufacturing equipment. 23. The method of claim 22, wherein the design intent information includes the location and critical dimensions of a particular conductive line in the integrated circuit. 28. The method of claim 27, wherein the location and critical dimensions are used by metrological equipment in the integrated circuit manufacturing equipment. 22. The method of claim 21, wherein the design intent information includes equipment usage information provided to the integrated circuit designer by an integrated circuit manufacturing equipment manufacturer. 30. The method of claim 29 wherein the equipment usage information is a design rule that defines an optimal circuit configuration to be formed by the integrated circuit manufacturing equipment. 31. The integrated circuit (IC) fabrication of claim 30, wherein the design rule identifies a location to place a dummy structure to prevent dishing when using a chemical-mechanical polishing tool for fabricating the integrated circuit. How to improve. 30. The method of claim 29, wherein the equipment usage information comprises fabrication capability information. 22. The method of claim 21, further comprising: generating a list of equipment to be used and / or to be used by the integrated circuit manufacturing facility; Identifying performance characteristics of the listed equipment; Generating the design rule using the performance characteristics of the listed equipment and a device model of an integrated circuit structure defined by the design rule. . As an integrated circuit manufacturing facility, An integrated circuit manufacturing facility comprising integrated circuit manufacturing equipment adapted to operate in accordance with an integrated circuit design distribution and design intent information. 35. The integrated circuit fabrication facility of claim 34, wherein the design intent information includes at least one location of critical circuit elements. 35. The integrated circuit fabrication facility of claim 34, wherein the design intent information includes identification of critical circuit elements within the integrated circuit. 35. The integrated circuit fabrication facility of claim 34, wherein the design intent information includes at least one circuit attribute selected from the group consisting of specifications of yield, speed, and power consumption. 36. The integrated circuit manufacturing facility of claim 35, further comprising metrological equipment, wherein the at least one location is measured by the metrological equipment. 36. The integrated circuit manufacturing facility of claim 35, further comprising metrological equipment, wherein the critical circuit element is measured by the metrological equipment. 36. The integrated circuit fabrication facility of claim 35, wherein the design intent information includes a location and critical dimension of a particular conductive line in the integrated circuit. 41. The integrated circuit manufacturing facility of claim 40, further comprising metrological equipment, wherein the location and critical dimensions are used by the metrological equipment. 35. The integrated circuit manufacturing facility of claim 34, wherein the design intent information includes equipment usage information provided to the integrated circuit designer by an integrated circuit manufacturing equipment manufacturer. 40. The integrated circuit manufacturing facility of claim 39, wherein the equipment usage information is a design rule that defines an optimal circuit configuration to be formed by the integrated circuit manufacturing equipment. 44. The integrated circuit manufacturing facility of claim 43, wherein the design rule identifies a location to place a dummy structure to prevent recession when using a chemical-mechanical polishing tool to manufacture the integrated circuit. 43. The integrated circuit manufacturing facility of claim 42, wherein the equipment usage information includes manufacturing capability information. 36. The integrated circuit manufacturing facility of claim 35, further comprising a design intent information source. 47. The integrated circuit fabrication facility of claim 46, wherein the source comprises a database of critical elements located on the integrated circuit. 47. The integrated circuit fabrication facility of claim 46, wherein the source comprises a look up table of critical elements located on the integrated circuit.