KR20040086977A - Synchronizing System and Method for the Clock of the Gap Filler Signal Processor Thereof - Google Patents

Abstract

PURPOSE: A clock synchronization system of a gap filler signal processor is provided to extract a clock from a satellite broadcasting signal to drive a PLL(Phase Locked Loop) by using the extracted clock as a reference frequency, and to stably process the reference frequency, thereby removing a shading area. CONSTITUTION: A controller(310) receives a lock signal showing whether a frequency of a PLL is normally outputted, and monitors/controls a PLL state. A TDM(Time Division Multiplex) demodulator(320) extracts TDM data and a 2.304MHz reference clock from a frame of a TDM signal. Plural PLL modules(330) generate clocks. An FIR filter(350) filters digital data in connection with an FPGA(Field Programmable Gate Array)(340). A DAC unit converts I and Q digital signals into analog signals. An up-RF unit(370) transmits the signals outputted through the DAC unit.

Description

Synchronizing System and Method for the Clock of the Gap Filler Signal Processor Thereof}

The present invention relates to a clock synchronization system of a gap filler signal processor and a method thereof. More specifically, in order to synchronize the gap filler system, the present invention extracts a clock from a satellite broadcast signal, drives the PLL using the clock as a reference frequency, and configures a gap filler configured to generate and synchronize a high-definition clock. A clock synchronization system and a method thereof are provided.

Recently, the gap filler system in satellite broadcasting system is one of the key equipment for implementing satellite digital audio broadcasting (DAB) and processes a synchronization acquisition signal using a single frequency network. This gap filler system is a 12 kHz (KU-band) time division multiplex transmitted by the broadcast satellite to the ground.

ing) modulates the signal into 2.6 GHz (S-band) CDM (Code Division Multiplexing) signal so that the satellite DAB terminal can receive it. In other words, the terrestrial transmitting station's signal is re-transmitted by the satellite for the satellite DAB service on the ground, and the broadcast signal is converted so that the subscribers can receive it smoothly through the mobile terminal.

However, the gap filler system must provide a clock source of high stability during CDM modulation, and for this purpose, the gap filler system needs a high frequency reference frequency.

An example thereof will be described with reference to FIG. 1.

1 is a block diagram showing the overall configuration of a conventional gap filler system. In FIG. 1, a satellite broadcasting system includes a satellite for transmitting a program to a user.

(1) and a terrestrial broadcasting station (2) for transmitting aptitude and edited program information by a broadcasting company of each broadcasting center, and a broadcasting signal transmitted by the terrestrial broadcasting station (2), a CDM signal of 2.6 Ghz band and a TDM of 12 Ghz band. In the terrestrial broadcast station 3, which is transmitted on the ground by a signal, a general receiver 4 including a portable receiver, a fixed receiver, a vehicle receiver and various other types of devices, and the terrestrial broadcast station 2 Gap filler device for relaying a shadowing area in which no signal is transmitted

(5) and a user terminal 3 for the user to watch the program.

Here, the gap filler system 5 includes a signal processing unit for converting a TDM signal into a CDM signal, and receives a TDM signal in a 12 Ghz band and converts it into a CDM signal in a 2.6 Ghz band and transmits it to a shadow area. This will be described in detail with reference to FIG. 2.

FIG. 2 is a diagram illustrating a signal processor of the gap filler system of FIG. 1.

As shown in FIG. 2, the signal processing unit 200 of the gap filler system 5 includes a TCM unit 210 for converting a TDM signal received by an LNB into a CDM, an RF modulator 220 for upconverting a CDM signal, and The control unit 230 is responsible for the control and monitoring of the signal processing unit 200. In addition, the TCM unit 210 of the signal processing unit 200 includes a tuner 212 for converting an output signal of the LNB into a baseband signal, and a TDM demodulation unit performing QPSK demodulation and FEC (Forward Error Correction). 214, and a CDM modulator 216 for CDM modulating the TDM demodulated signal.

According to the configuration of the gap filler system, since the gap filler system must be synchronized using a single frequency network in a satellite broadcasting system, a 16.384 MHz clock source required by a highly stable clock source for synchronization during CDM modulation is required. Do. In other words, each gap filler system requires a high frequency reference frequency to remove the shadow area where satellite broadcast signals cannot be received. In other words, the clock synchronization is a very important factor because it is an important part of the modulation and demodulation function, it is necessary to increase the stability of the clock and the clock synchronized with each part is required.

Accordingly, the present invention is to improve this disadvantage of the prior art, extract the clock from the satellite broadcast signal and drive the PLL with the clock as the reference frequency and through this to generate a high resolution clock through which the satellite broadcast signal is not received The present invention relates to a clock synchronization system and a method of gap filler signal processing for processing a high-stable reference frequency to remove shadow areas.

1 is a block diagram showing the overall configuration of a typical gap filler system.

FIG. 2 is a diagram illustrating a signal processing unit of a gap filler system in the system of FIG. 1. FIG.

3 is a block diagram of a signal processor of FIG. 1 according to an embodiment of the present disclosure.

4 is a configuration diagram illustrating a Pll module showing the inside of the PLL module of FIG. 3 in detail.

5 is a flowchart illustrating a clock synchronization method of a gap filler signal processing unit according to the present invention;

* Explanation of symbols for the main parts of the drawings *

200: signal processing unit

310: control unit

320: TDM demodulation unit

330: PLL Module

340: Field Programmable Gate Array

350: FIR filter unit

360: DAC part

370: RF unit

TDM: Time Division Multiplex

CDM: Code Division Multiplex

LNB: Low Noise Block

PLL: Phase Locked Loop.

The clock synchronization system of the gap filler signal processing unit according to the present invention for achieving the above object includes a control unit 310 for monitoring and controlling the PLL state by receiving a lock signal indicating whether the frequency of the PLL is normally output;

A TDM demodulator 320 for extracting TDM data and a 2.304 MHz reference clock from a frame of a TDM signal transmitted from a satellite,

Multiple PLL modules 330 for generating clocks using signals of 10 MHz and 65.536 MHz from a 2.304 MHz reference clock;

FPGA (Field-Programmable Gate Array) unit 340,

FIR filter unit connected to the FPGA unit 340 to filter digital data

350,

DAC unit 360 for converting the I, Q digital signal from the FIR filter 350 into an analog signal,

The DAC 360 includes an uplink RF unit 370 that transmits the signal from the 2.6 Ghz band.

In addition, the clock synchronization method of the gap filler signal processing unit,

Monitoring the clock and controlling the PLL state by receiving a lock signal indicating whether the frequency of the PLL is normally output by the controller 310 for clock synchronization of the gap filler signal processor (S402);

The PLL module 330 performs a PLL operation using a 2.304 MHz clock (S 404);

The PLL module 330 generates a clock using signals of 10 MHz and 65.536 MHz from the 2.304 MHz reference clock extracted by the TDM demodulator 320 (S406);

Thereafter, the FIR filter unit 350 connected to the plurality of PLL modules 330 and the field-programmable gate array (FPGA) unit 340 may include filtering digital data (S408);

Converting the I, Q digital signal from the FIR filter 350 into an analog signal by the DAC unit 360 (S410);

Thereafter, the RF unit 370 transmits the signal output through the DAC 360 at 2.6 Ghz (S412).

Hereinafter, a clock synchronization system and a method of synchronizing a gap filler signal processor according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a clock configuration in a signal processing unit of a system according to a preferred embodiment of the present technology.

As shown in FIG. 3, a gap filler for clock synchronization according to an embodiment of the present invention wirelessly transmits a broadcast signal at a reference frequency of high definition equal to a frequency transmitted from a satellite.

In the clock synchronization system, the signal processor 200 receives a lock signal indicating whether the frequency of the PLL is normally output, and receives a lock signal to control and monitor the PLL state, and the TDM from a frame of the TDM signal transmitted from the satellite. TDM demodulator 320 for extracting data and 2.304 MHz reference clock, multiple PLL modules 330 for generating clocks for use as signals of 10 MHz and 65.536 MHz from 2.304 MHz reference clocks, and field-programmable FPGAs Gate Array unit 340, FIR filter unit 350 connected to the FPGA unit 340 to filter digital data, and I, Q digital signals from the FIR filter 350 are converted into analog signals. It includes a DAC unit 360, and an RF modulator 370 for transmitting the signal from the DAC 360 to 2.6 GHz.

The controller 310 monitors the lock signal of the PLL module and initializes the PLL when a signal does not come in for a predetermined time.

The TDM demodulator 320 extracts a 2.304 MHz clock from the satellite broadcast signal introduced through the tuner 212 shown in FIG. 1 and uses the TDM demodulator 320 as a reference clock of the PLL module 330.

The PLL module 330 synchronizes the operation clocks of the CDM modulator 346, the A / D converter 350, and the FIR filter 350 using only one. In this way, if one PLL module 330 is used to synchronize the operation clock, one PLL module is used instead of extracting a 65.536 MHz clock and a 10 MHz clock into each PLL module using a 2.304 MHz reference clock. The two clocks can be extracted to increase the stability of the clock.

The FPGA unit 340 includes a clock generator 342 for generating 2.048 MHz and 16.384 MHz clocks, a TDM DEMUX unit 344 for extracting and demodulating data for each channel in a TDM frame from the clock generator 342, And a CDM modulator 346 for performing CDM modulation to convert clock data from the clock generator 342 into CDM data.

Here, the clock generator 346 generates 2.048 MHz and 16.384 MHz clocks, which are clocks used by the TDM DEMUX 344 and the CDM modulator 346.

In addition, the FPGA unit 340 is one chip by using the clock generator 342, the TDM DEMUX 344, and the CDM modulator 346.

The FIR filter 350 filters the digital data from the CDM modulator 330.

Accordingly, the PLL module 330 according to the present invention is used to synchronize the operation clocks of the RF modulator, the CDM modulator, and the FIR filter.

4 is a configuration diagram illustrating a PLL module in detail showing the inside of the PLL module of FIG. 3. Referring to FIG. 4, the PLL module 330 of the gap filler signal processing unit of the clock synchronization system according to the present invention uses a clock of 2.304 MHz, which is a signal recovered from a satellite for clock synchronization, as a reference signal, 10 MHz and 65.536 MHz. Generate clock and use it as synchronous clock of whole board.

This will be described in detail. The first IC unit 332 to which the 2.304 MHz reference clock signal is input, the VCXO 336 connected to the first IC unit 332 through the LPF 334, and the first IC unit 332 are controlled. A control IC unit 333 to which a signal is applied, a second IC unit 333 to which a control signal of 2.304 MHz is input, and a VCXO 337 connected to the first IC unit 333 via an LPF 335. Include. The first IC unit 332 to which the signal of 2.304 MHz is input generates 65.536 MHz of high definition by the VCXO 336 connected through the LPF 334, and a control signal is applied to the first IC unit 332. The applied control IC unit 333 is defined by a second IC unit 333 to which a control signal of 2.304 MHz is input, and a VCXO 337 connected to the first IC unit 333 via an LPF 335. Generate a clock of 10 MHz.

Here, the 65.536 MHz clock is used for the CDM modulator 346, the analog to digital converter (A / D converter 360, and the FIR filter 350), as shown in FIG. 2, and the 10 MHz clock is the RF modulator. Or, it is used as the reference clock of the PLL of the upboard.

Next, FIG. 5 illustrates a clock synchronization method of a gap filler signal processing unit according to the present invention.

In the clock synchronization system of FIG. 4, the signal processor 200 monitors and controls the PLL state by receiving a lock signal indicating whether the frequency of the PLL is normally output by the controller 310 (S402).

Here, the PLL module 330 performs a PLL operation using a 2.304 MHz clock. Under the control of the control unit 310, the TLL data and the 2.304 from the frame of the TDM signal transmitted from the satellite by the TDM demodulator 320 are 2.304. The PLL module 330 extracts the MHz reference clock (S404). The PLL module 330 generates a clock using signals of 10 MHz and 65.536 MHz from the 2.304 MHz reference clock extracted by the TDM demodulator 320 (S406). ). Thereafter, the FIR filter unit 350 connected to the plurality of PLL modules 330 and the field-programmable gate array (FPGA) unit 340 filters the digital data (S408). The I and Q digital signals from the FIR filter 350 are converted into analog signals by the DAC unit 360 (S410). Thereafter, the RF unit 370 transmits the signal outputted through the DAC 360 at 2.6 GHz (S412).

As described above, according to the clock synchronization system and method of the gap filler signal processing unit according to the present invention, one PLL by synchronizing the operation clock of the CDM modulator and the FIR filter using one PLL module 330, Using the module to extract two clocks increases the stability of the clock. In addition, the size of the board can be reduced due to the miniaturization of components, and it has advantages in securing price competitiveness.

Although the present invention has been described in detail only with respect to the embodiments described, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims.

Claims (8)

In a clock synchronization system, A control unit 310 which receives and locks a signal indicating whether the frequency of the PLL is normally output, and monitors and controls the PLL state; A TDM demodulator 320 for extracting TDM data and a 2.304 MHz reference clock from a frame of a TDM signal transmitted from a satellite, Multiple PLL modules 330 for generating clocks using signals of 10 MHz and 65.536 MHz from a 2.304 MHz reference clock; FPGA (Field-Programmable Gate Array) unit 340, An FIR filter unit 350 connected to the FPGA unit 340 to filter digital data; DAC unit 360 for converting the I, Q digital signal from the FIR filter 350 into an analog signal, The clock synchronization system of the gap filler signal processing unit comprising an uplink RF unit (370) for transmitting the signal from the DAC (360) to 2.6 GHz band. The method according to claim 1, The TDM demodulator (320) is a clock synchronization system of the gap filler signal processing unit, characterized in that to extract the 2.304 MHz clock from the satellite broadcast signal coming through the tuner (not shown) and synchronized to the reference clock of the PLL module (330). The method according to claim 1, The PLL module 330 extracts two clocks by synchronizing operation clocks of the CDM modulator 346, the A / D converter 350, and the FIR filter 350 using only one. Clock synchronization system of the signal processor. The method according to claim 1, The FPGA unit 340 includes a clock generator 342 for generating 2.048 MHz and 16.384 MHz clocks, a TDM DEMUX unit 344 for extracting and demodulating data for each channel in a TDM frame from the clock generator 342, And a CDM modulator (346) for performing CDM modulation to convert the clock data from the clock generator (342) into CDM data. In the clock synchronization method, Monitoring the clock and controlling the PLL state by receiving a lock signal indicating whether the frequency of the PLL is normally output by the controller 310 for clock synchronization of the gap filler signal processor (S402); The PLL module 330 performs a PLL operation using a 2.304 MHz clock (S 404); The PLL module 330 generates a clock using signals of 10 MHz and 65.536 MHz from the 2.304 MHz reference clock extracted by the TDM demodulator 320 (S406); Thereafter, the FIR filter unit 350 connected to the plurality of PLL modules 330 and the field-programmable gate array (FPGA) unit 340 may include filtering digital data (S408); Converting the I, Q digital signal from the FIR filter 350 into an analog signal by the DAC unit 360 (S410); And, Thereafter, the RF unit 370 transmits the signal output through the DAC 360 as 2.6 Ghz (S 412). The method according to claim 5, The clock generator 346 generates 2.048 MHz and 16.384 MHz clocks, which are clocks used by the TDM DEMUX 344 and the CDM modulator 346, and uses a clock of 2.304 MHz, which is a signal recovered from the satellite, as a reference signal. A clock synchronization method of a gap filler signal processor, characterized by generating clocks of 10 MHz and 65.536 MHz and using them as synchronous clocks of the entire board. The method according to claim 5, And the signal processor uses the 10 MHz extracted from the TCM unit as a reference clock of the RF modulator. The method according to claim 5, And the signal processor monitors and controls a lock state of a PLL module generating a clock of 65.536 MHz and 10 MHz using a reference frequency of 2.304 MHz.