KR20040085740A - Error diffusion method and apparatus of plasma display panel - Google Patents

Abstract

PURPOSE: A method for diffusing an error of a plasma display panel and an apparatus thereof are provided to prevent the generation of an error diffusion pattern. CONSTITUTION: An error filter(76) detects an error value of input data. An error value aligner(81) changes a position of the error value with a constant period. A line memory(77) stores the error value from the error value aligner and outputs the stored error value. And adders(71,72,73,74) add the error value from the line memory and the input data.

Description

ERROR DIFFUSION METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to an error diffusion method and apparatus for a plasma display panel to prevent occurrence of error diffusion patterns.

As the information processing system develops and its spread is expanded, the importance of the display device as a means of transmitting visual information is increasing. Cathode ray tubes (CRTs), which dominate the display device, have large size, high operating voltage, and display distortion. Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma display panels (hereinafter referred to as "PDPs") can solve the disadvantages of cathode ray tubes. Flat panel display devices are being developed.

The PDP displays an image by excitation of phosphors by vacuum ultraviolet rays generated when the inert gas is discharged. Such a PDP is not only thin and large in size, but also simple in structure, and has a high luminance and high luminous efficiency as compared to other flat display devices. In particular, AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect electrodes from sputtering caused by discharge.

Referring to FIG. 1, an AC surface discharge type PDP includes a front glass substrate 1 on which an upper electrode 9 is formed, and a back glass substrate 2 on which an address electrode 4 is formed.

The front glass substrate 1 and the rear glass substrate 2 are spaced apart in parallel with the partition 3 therebetween. A mixed gas such as Ne + Xe, He + Xe, He + Ne + Xe is injected into the discharge space provided by the front glass substrate 1, the rear glass substrate 2, and the partition wall 3. The upper electrode 9 is paired with two in one plasma discharge channel. Each of the upper plate electrodes 9 includes a wide transparent electrode and a narrow metal bus electrode connected to one side edge of the transparent electrode. Any one of the pair of top electrodes 9 causes an opposite discharge with the address electrode 4 in response to the scan pulse supplied in the address period, and then the adjacent top electrodes 9 in response to the sustain pulse supplied in the sustain period. ) And a scan electrode causing surface discharge. The other upper electrode 9 paired with the scan electrode is a sustain electrode to which a sustain pulse is commonly supplied.

The top dielectric layer 7 and the passivation layer 8 are stacked on the front glass substrate 1 on which the top electrodes 9 are formed. The upper dielectric layer 7 serves to limit the discharge current during plasma discharge and to accumulate wall charges during discharge. The protective film 8 is usually made of magnesium oxide (MgO), and prevents damage to the top dielectric layer 7 caused by sputtering generated during plasma discharge and improves the emission efficiency of secondary electrons.

A lower dielectric layer 6 is formed on the rear glass substrate 2 to cover the address electrodes 4. The lower dielectric layer 6 serves to protect the address electrodes 4. On the lower dielectric layer 6, partition walls 3 for dividing the discharge space are formed. On the surfaces of the lower dielectric layer 6 and the partition walls 3, phosphors 4 are excited by vacuum ultraviolet rays to generate visible light of red, green and blue (R, G, B).

The discharge mechanism of the PDP is as follows. When a voltage is applied between two electrodes of the PDP, a potential is formed in the discharge space, and a potential is generated in the pixel as the gas atoms and molecules collide with each other and ionization proceeds. The charged particles generated by the gas discharge are accumulated on the surface of the dielectric layer 7 according to the polarity of the electrode. The negative and positive charges accumulated on the surface of the dielectric layer 7 are called wall charges, and the voltage of the pixel charged by the wall charges is called a wall voltage. If the polarity of the wall charge sufficiently accumulated on the surface of the dielectric layer 7 is opposite to the polarity of the external voltage applied to the electrode, the discharge is erased while the wall voltage and the external voltage are canceled out. When the polarities of the external voltages are reversed and the polarities of the wall voltages and the external voltages are the same, the total voltage applied to the discharge space is the sum of the external voltages and the wall voltages. .

The PDP is time-divisionally driven in a so-called ADS (Address and Display Seperated) method, which is divided into an address period for selecting a pixel and a sustain period causing display discharge in the selected pixel, in order to realize the gray level of the image. That is, one frame period is divided into several subfields in which the sustain discharge number is set differently according to the luminance weight, and each subfield is divided into a reset period, an address period, and a sustain period. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 is a block diagram schematically illustrating a PDP and a driving circuit thereof.

Referring to FIG. 3, a conventional PDP apparatus includes a gamma & gain adjusting unit 31, an error diffusion & dither processing unit 32, a subfield mapping unit 33, and a data driver connected between an input line and a PDP 37. 34).

The PDP 37 includes a sustain electrode pair including a scan electrode and a sustain electrode and an address electrode intersecting the sustain electrode pair. Discharge cells are arranged in a matrix form between the sustain electrode pairs and the address electrodes.

The digital video data RGB is input to the subfield mapping unit 33 through the gamma & gain adjusting unit 31 and the error diffusion & dither processing unit 32.

The gamma & gain adjusting unit 31 performs gamma correction and gain correction on the digital video data RGB for each of the red data R, the green data G, and the blue data B. FIG.

The error diffusion & dither processing unit 32 spreads the quantization error component of the digital video data RGB input from the gamma & gain adjustment unit 31 to adjacent pixels using a Floyd-Steinberg error diffusion filter. Reduce the quantization error and refine the gradation expression. In addition, the error diffusion & dither processing unit 32 thresholds the input data with a dither mask (or dither matrix) having a threshold set corresponding to each pixel.

The subfield mapping unit 33 maps the data from the error diffusion & dither processing unit 32 to a preset subfield pattern.

The data driver 34 latches data from the subfield mapping unit 33 and supplies the latched data to the address electrodes of the PDP 37 by one line every one horizontal period.

The scan driver 35 is connected to the scan electrodes of the PDP 37 to supply the necessary signals to the scan electrodes to drive the scan electrodes.

The sustain driver 36 is connected to the sustain electrode of the PDP 37 to supply the necessary signal to the sustain electrode to drive the sustain electrode.

However, the conventional PDP has a problem in that error diffusion patterns appear because the error diffusion weights (coefficients) of neighboring pixels added to adjacent pixels are constant. In particular, the error diffusion pattern is prominent in still images and low gray levels in which the same pattern is displayed continuously. For example, using a Floyd-Steinberg error diffusion filter, the pixel of the jth column (where j is any positive integer) in the i th row, where i is any positive integer, as shown in FIG. In the case of spreading the error value at, from three pixels P (i-1, j-1), P (i-1, j) and P (i-1, j + 1) included in the i-1th line The error value multiplied by the weights of 1/16, 5/16, and 3/16 are added, and the error value multiplied by the weight of 7/16 is added from the left pixel P (i, j-1) in the i-th line. . Here, the sum of the error weights should be 1. Since the error diffusion is constantly repeated every line and every frame, as shown in FIG. 5, the first pixel every line and every frame is represented by the minimum emission value. Therefore, when the error diffusion is performed by applying the conventional error diffusion filter, the error diffusion pattern appears on the screen as shown in FIG. In order to solve this problem, a method of arbitrarily changing error diffusion weights (or coefficients) has been proposed, but this method has a problem in that the algorithm is complicated and the circuit complexity is increased.

Accordingly, an object of the present invention is to provide an error diffusion method and apparatus for a plasma display panel to prevent occurrence of error diffusion patterns.

1 is a perspective view showing a conventional three-electrode alternating surface discharge plasma display panel.

2 is a diagram illustrating a default subfield pattern obtained by dividing one frame period into eight subfields.

3 is a block diagram showing a conventional plasma display panel device.

4 is a view for explaining error diffusion of a conventional error diffusion filter.

5 is a view showing that the minimum light emitting pattern is constant when the conventional error diffusion.

6 is an image showing an error diffusion pattern.

7 is a block diagram illustrating an error diffusion device of a plasma display panel according to an exemplary embodiment of the present invention.

8 is a view for explaining the error diffusion of the present invention.

9 is a view showing that the lowest light emitting pattern is irregular when the error diffusion according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: front glass substrate 2: rear glass substrate

3: bulkhead 4: address electrode

5: phosphor 6,7: dielectric layer

8: protective film 9: top electrode

31: Gamma & Gain Adjuster 32: Error Diffusion & Dither Processing

33: subfield mapping unit 34: data driver

35 scan driver 36 sustain driver

37 plasma display panel 71 to 74 adder

76: error filter 77: line memory

78 to 80: flip-flop 81: error value sorter

In order to achieve the above object, the error diffusion method of the PDP according to an embodiment of the present invention comprises the steps of detecting the error value of the input data; Changing the position of pixels at which the error value appears.

The error value is characterized in that the lowest emission value appear in the pixels.

An error diffusion device of a PDP according to an embodiment of the present invention includes an error filter for detecting an error value of input data; An error value aligner for changing the position of the error value at regular intervals; A line memory for storing the error value from the error value aligner and outputting the stored error value; And an adder for adding the error value and the input data from the line memory.

The error value sorter is characterized in that for changing the position of the error value every frame unit.

The error value sorter is characterized in that for changing the position of the error value every line.

The error value aligner is characterized in that for changing the position of the error value every dot.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 9.

Referring to FIG. 7, an error diffusion device of a PDP according to an embodiment of the present invention includes an error filter 76 for detecting an error value and outputting the error value E (i, j). An error value sorter 81 for aligning the error values E (i, j) of the first and second flip-flops 78 and 79 connected to the error value sorter 81 dependently, and an error filter A third flip-flop 80 connected to 80, and adders 71-74 connected to the line memory 77 and the output terminals of the respective flip-flops 78-80.

The error filter 76 compares the threshold value with the pixel data input from the fourth adder 74 and calculates a quantization error value. This quantization error value is obtained by subtracting the output pixel value from the input pixel value. The error filter 76 multiplies the error quantization error value by a preset error diffusion weight, for example, the error diffusion coefficients 1/16, 5/16, 3/16, and 7/16 of Floyd-Stienberg. Occurs.

The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the pixel clock PCLK are input to the error value aligner 81. The error value aligner 81 adjusts the position of the error value E (i, j) from the error filter 76 every frame in accordance with the vertical synchronization signal Vsync, and every horizontal line in accordance with the horizontal synchronization signal Hsync. Each dot and every pixel (or pixel unit) according to the pixel clock PCLK.

The line memory 77 delays the error value input from the error value aligner 81 by one horizontal period, that is, one horizontal sync signal Hsync, and delays the delayed error value by the first adder 71 and the first flip-flop ( 78). The error value E (i, j) input to this line memory 77 is changed according to the sorting order of the error value sorter 81. Accordingly, the error value E (i, j), which is expressed as the minimum emission value, differs from the conventional line which is stored in the first cell of the line memory 77 every horizontal period, according to the position determined by the error value sorter 81 The location stored in the memory 77 will be different.

The first flip-flop 78 delays the error value E (i, j) from the line memory 77 by one dot to supply the second adder 72, and the second flip-flop 79 supplies the first flip. The error value E (i, j) from the flop 78 is delayed by one dot and supplied to the third adder 73. The third flip-flop 80 delays the error value E (i, j) from the error filter 76 by one dot and supplies it to the fourth adder 74.

The adders 71 to 74 add the error value E (i, j) input from the line memory 77 and the respective flip-flops 78 to 80 to the one pixel data S (i, j). Here, the first adder 71 adds the error value of the right pixel of the previous line Li-1 to the one pixel data S (i, j) in FIG. 9, and the second adder 72 of the previous line Li-1. The error value of the center pixel is added to the one pixel data S (i, j). The third adder 73 adds an error value of the center pixel of the current line Li to the one pixel data S (i, j).

As shown in FIG. 8, the error diffusion device changes the error values V1 and V2 stored in the first cell in the line memory 77 every frame, every horizontal line, and every dot. As a result, the pixel value of the minimum light emission value shown in the hatched pattern in FIG. 9 is changed every frame, every horizontal line, and every dot, so that the error diffusion pattern as shown in FIG. 6 does not appear.

As described above, the error diffusion method and apparatus of the PDP according to the present invention arbitrarily change the error diffusion weight (coefficient) by changing the position of the error value stored in the line memory every frame, every horizontal line, and every dot. It is possible to prevent the occurrence of error diffusion pattern without changing. In particular, the error diffusion method and apparatus of the PDP according to the present invention can prevent the error diffusion pattern from occurring in still images or low gradations in which the same pattern is continuously displayed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

Detecting an error value of the input data; And changing a position of pixels in which the error value appears. The method of claim 1, And the error value is displayed at the pixels at the lowest emission value. An error filter detecting an error value of the input data; An error value aligner for changing the position of the error value at regular intervals; A line memory for storing the error value from the error value aligner and outputting the stored error value; And an adder for adding the error value from the line memory and the input data. The method of claim 1, And the error value is displayed at the pixels at the lowest emission value. The method of claim 1, And the error value aligner changes the position of the error value every frame unit. The method of claim 1, And the error value aligner changes the position of the error value every line. The method of claim 1, And the error value aligner changes the position of the error value every dot.