KR20040082751A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a flash memory device is provided to stabilize a fabricating process by guaranteeing an overlay margin between a floating gate and an active region, and to improve a retention characteristic by rounding the upper corner of the floating gate. CONSTITUTION: A tunnel oxide layer(23) and a floating gate layer(24) are formed on a semiconductor substrate(21) having an isolation layer(22). The exposed portion of the floating gate layer is etched by a predetermined thickness through an etch process using a mask for a floating gate so that a trench is formed in the floating gate layer over the isolation layer. A conductive layer(210) is formed along the surface of the floating gate layer having the trench. An anisotropic etch process is performed until the isolation layer is exposed, and the floating gate layer is patterned. A dielectric layer(26) is formed on the patterned floating gate layer. A control gate and the floating gate are formed.

Description

Method of manufacturing flash memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of stabilizing a process by securing an overlap margin between a floating gate and an active region.

1A to 1C are cross-sectional views of devices for describing a method of manufacturing a conventional flash memory device.

Referring to FIG. 1A, an isolation region 12 is formed on a semiconductor substrate 11 to define an active region, and a tunnel oxide layer 13 is formed on a semiconductor substrate 11 in an active region. do. The floating gate layer 14 is formed on the entire structure including the tunnel oxide film 13. The photoresist pattern 15 is formed on the floating gate layer 14 by a photolithography process using a floating gate mask.

Referring to FIG. 1B, the floating gate layer 14 is patterned by an etching process using the photoresist pattern 15 as an etching mask.

Referring to FIG. 1C, the photoresist pattern 15 is removed, and the dielectric film 16 is formed along the surface of the patterned floating gate layer 14. After depositing the control gate layer 17 over the entire structure including the dielectric film 16, an etching process using a control gate mask is performed to form the control gate 17, and then a self-aligned etching process is performed. To form the floating gate 14.

The floating gate 14 is formed by an etching process using a mask for floating gates and a self-aligned etching process using a mask for control gates. In recent years, as semiconductor devices become more integrated, not only the area of the active region is narrowed, but also the space between the floating gates 14 formed adjacent to each other with the device isolation layer 12 therebetween is also narrowed. The floating gate 14 overlaps both ends of the device isolation layer 12 so as to completely cover the active region, specifically the channel region, and the neighboring floating gate to increase the coupling ratio with the control gate 17. Make the space between (14) as narrow as possible. However, there is a limit to narrow the space between the floating gates 14 as much as possible, which makes it difficult to achieve high integration of the device, and when the photo process margin is insufficient and misalignment occurs, as shown in FIG. The area may be exposed. When the control gate 17 is formed in this state, the control gate 17 and the active region directly meet, which causes the control gate 17 to not control the floating gate 14.

In addition, the floating gate 14 has its top edge portion formed in a point profile, which is not removed even after the subsequent dielectric film 16 formation process. As a result, the upper edge portion of the floating gate 14 is present in a pointed state, and when the device is operated, an electric field is concentrated on the portion, which causes charge loss of the floating gate 14. The charge loss of the floating gate 14 eventually has a problem of worsening the retention characteristics of the device, thereby lowering the reliability of the device.

Accordingly, the present invention provides a method of manufacturing a flash memory device capable of securing the overlap margin between the floating gate and the active region, thereby achieving stabilization of the process, maximizing the coupling ratio and improving retention characteristics. The purpose is.

1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional flash memory device.

2A to 2D are cross-sectional views of a device for explaining a method of manufacturing a flash memory device according to the first embodiment of the present invention.

3A to 3D are cross-sectional views of devices for explaining a method of manufacturing a flash memory device according to the second embodiment of the present invention.

4A to 4D are cross-sectional views of a device for explaining a method of manufacturing a flash memory device according to a third embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21, 31, 41: semiconductor substrate 12, 22, 32, 42: device isolation film

13, 23, 33, 43: tunnel oxide film 14, 24, 34, 44: floating gate layer

15, 25, 35, 45: photoresist pattern 16, 26, 36, 46: dielectric film

17, 27, 37, 47: control gate layer 200, 310, 410: trench

210, 320: conductive layer 300, 400: buffer insulating layer

420: SEG layer

The flash memory device manufacturing method of the present invention for achieving the above object comprises the steps of forming a tunnel oxide film and a floating gate layer on a semiconductor substrate on which the device isolation film is formed; Etching an exposed portion of the floating gate layer to a predetermined thickness by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a conductive layer along a surface of the trench in which the trench is formed; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Forming a dielectric film on the patterned floating gate layer; And forming a control gate and a floating gate.

Another method of manufacturing a flash memory device of the present invention comprises the steps of forming a tunnel oxide film, a floating gate layer and a buffer insulating layer on a semiconductor substrate on which the device isolation film is formed; Etching a portion of the buffer insulating layer and the exposed portion of the floating gate layer by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a conductive layer along surfaces of the trenched floating gate layer and the patterned buffer insulating layer; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Removing a buffer insulating layer over the patterned floating gate layer; Forming a dielectric film on the patterned floating gate layer; And forming a control gate and a floating gate.

Another method of manufacturing a flash memory device of the present invention comprises the steps of: forming a tunnel oxide film, a floating gate layer and a buffer insulating layer on a semiconductor substrate on which the device isolation film is formed; Etching a portion of the buffer insulating layer and the exposed portion of the floating gate layer by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a selective epitaxial silicon growth layer in the floating gate layer of the trench portion; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Removing the buffer insulating layer over the patterned floating gate layer; Forming a dielectric film on the patterned floating gate layer; And forming a control gate and a floating gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

2A to 2D are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to a first embodiment of the present invention.

Referring to FIG. 2A, an isolation region 22 is formed in the semiconductor substrate 21 to define an active region, and a tunnel oxide layer 23 is formed on the semiconductor substrate 21 in the active region. do. The floating gate layer 24 is formed on the entire structure including the tunnel oxide film 23. The photoresist pattern 25 is formed on the floating gate layer 24 by a photolithography process using a mask for floating gates.

Referring to FIG. 2B, an exposed portion of the floating gate layer 24 is etched to a predetermined thickness by an etching process using the photoresist pattern 25 as an etching mask, and thus, the floating gate layer is formed along the upper portion of the device isolation layer 22. The trench 200 is formed at 24. After removing the photoresist pattern 25, the conductive layer 210 is formed along the surface of the floating gate layer 24 on which the trench 200 is formed.

In the above, the conductive layer 210 may be a floating gate such as doped poly crystal silicon, undoped poly crystal silicon, implanted poly crystal silicon, or the like. It is formed of a material that can be used.

Referring to FIG. 2C, the floating gate layer 24 is patterned by performing an anisotropic etching process until the device isolation layer 22 is exposed while the conductive layer 210 is formed. The patterned floating gate layer 24 has a conductive layer 210 on both sides in the form of a spacer, which means that the patterned floating gate layer 24 of the present invention is conventionally patterned floating gate layer (FIG. 1B). It can be seen that it is formed in a pattern larger by twice the deposition thickness of the conductive layer 210 compared to the reference numeral 14 of. Therefore, even if the photo process margin is insufficient and misalignment occurs, the process can be stabilized by additionally securing an overlap margin than the existing process. In addition, since the floating gate layer 24 is patterned by an anisotropic etching process without using an etching mask, the upper edge portion to be etched is rounded.

Referring to FIG. 2D, a dielectric film 26 is formed along the surface of the patterned floating gate layer 24 having the conductive layer 210 in the form of a spacer. After depositing the control gate layer 27 over the entire structure including the dielectric film 26, an etching process using a mask for the control gate is performed to form the control gate 27, followed by a self-aligned etching process. To form the floating gate 24.

3A to 3D are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to a second embodiment of the present invention.

Referring to FIG. 3A, the device isolation layer 32 is formed on the semiconductor substrate 31 to define an active region, and the tunnel oxide layer 33 is formed on the semiconductor substrate 31 in the active region. do. The floating gate layer 34 and the buffer insulating layer 300 are formed on the entire structure including the tunnel oxide film 33. The photoresist pattern 35 is formed on the buffer insulating layer 300 by a photolithography process using a floating gate mask.

Referring to FIG. 3B, an exposed portion of the buffer insulating layer 300 and the floating gate layer 34 is etched to a predetermined thickness by an etching process using the photoresist pattern 35 as an etching mask, and thus the device isolation layer 32 is etched. A trench 310 is formed in the floating gate layer 34 along the upper side. After removing the photoresist pattern 35, the conductive layer 320 is formed along the surfaces of the floating gate layer 34 on which the trench 310 is formed and the patterned buffer insulating layer 300.

In the above, the buffer insulating layer 300 is formed of an oxide-based or nitride-based. The conductive layer 320 may be used as a floating gate, such as doped poly crystal silicon, undoped poly crystal silicon, implanted poly crystal silicon, or the like. Form into material.

Referring to FIG. 3C, the floating gate layer 34 is patterned by performing an anisotropic etching process until the device isolation layer 32 is exposed while the conductive layer 320 is formed. The patterned buffer insulating layer 300 serves as an etch protective layer of the floating gate layer 34 as an underlying layer during the anisotropic etching process. The patterned floating gate layer 34 has a conductive layer 320 on both sides in the form of a spacer, which means that the patterned floating gate layer 34 of the present invention is conventionally patterned floating gate layer (FIG. 1B). It can be seen that the pattern is formed by twice as large as the deposition thickness of the conductive layer 320 compared to the reference numeral 14). Therefore, even if the photo process margin is insufficient and misalignment occurs, the process can be stabilized by additionally securing an overlap margin than the existing process. In addition, since the floating gate layer 34 is patterned by an anisotropic etching process without using an etching mask, the upper edge portion to be etched is rounded.

Referring to FIG. 3D, after removing the buffer insulating layer 300, a dielectric layer 36 is formed along the surface of the patterned floating gate layer 34 having the conductive layer 320 in the form of a spacer. After depositing the control gate layer 37 over the entire structure including the dielectric film 36, an etching process using a control gate mask is performed to form the control gate 37, followed by a self-aligned etching process. To form the floating gate 34.

4A to 4D are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to a third embodiment of the present invention.

Referring to FIG. 4A, an isolation region 42 is formed in the semiconductor substrate 41 to define an active region, and a tunnel oxide layer 43 is formed on the semiconductor substrate 41 in the active region. do. The floating gate layer 44 and the buffer insulating layer 400 are formed on the entire structure including the tunnel oxide layer 43. A photoresist pattern 45 is formed on the buffer insulating layer 400 by a photolithography process using a floating gate mask.

Referring to FIG. 4B, an exposed portion of the buffer insulating layer 400 and the floating gate layer 44 is etched to a predetermined thickness by an etching process using the photoresist pattern 45 as an etching mask, and thus, the device isolation layer 42 is etched. A trench 410 is formed in the floating gate layer 44 along the top of the. After removing the photoresist pattern 45, a selective epitaxial silicon growth (SEG) process is performed to form the SEG layer 420 only in the trench 410 portion of the floating gate layer 44.

In the above, the buffer insulating layer 400 is formed of oxide or nitride.

Referring to FIG. 4C, the floating gate layer 44 is patterned by performing an anisotropic etching process until the device isolation layer 42 is exposed while the SEG layer 420 is formed. The patterned buffer insulating layer 400 serves as an etch protective layer of the floating gate layer 44 as an underlying layer during the anisotropic etching process. The patterned floating gate layer 44 has a SEG layer 420 on both sides in the form of a spacer, which means that the patterned floating gate layer 44 of the present invention is conventionally patterned floating gate layer (FIG. 1B). It can be seen that the pattern is formed by twice as large as the deposition thickness of the SEG layer 420 compared to the reference numeral 14 of. Therefore, even if the photo process margin is insufficient and misalignment occurs, the process can be stabilized by additionally securing an overlap margin than the existing process. In addition, since the floating gate layer 44 is patterned by an anisotropic etching process without using an etching mask, the upper edge portion to be etched is rounded.

Referring to FIG. 4D, after removing the buffer insulating layer 400, a dielectric film 46 is formed along the surface of the patterned floating gate layer 44 having the SEG layer 420 in the form of a spacer. After depositing the control gate layer 47 over the entire structure including the dielectric film 46, an etching process using a mask for the control gate is performed to form the control gate 47, followed by a self-aligned etching process. To form the floating gate 44.

As described above, the present invention can secure the overlap margin larger than the overlap margin that can be secured by the photoresist pattern, thereby achieving stabilization of the process, and the upper edge portion of the floating gate is rounded to retain the device's retention characteristics. Can be improved, and the pattern size of the floating gate can be made as large as possible, thereby achieving high integration of the device.

Claims (13)

Forming a tunnel oxide film and a floating gate layer on the semiconductor substrate on which the device isolation film is formed; Etching an exposed portion of the floating gate layer to a predetermined thickness by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a conductive layer along a surface of the trench in which the trench is formed; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Forming a dielectric film on the patterned floating gate layer; And And forming a control gate and a floating gate. The method of claim 1, And the conductive layer is formed of any one of doped polycrystalline silicon, undoped polycrystalline silicon, and implanted polycrystalline silicon. The method of claim 1, The patterned floating gate layer is a method of manufacturing a flash memory device, characterized in that the conductive layer in the form of a spacer on both sides. The method of claim 1, The patterned floating gate layer is a manufacturing method of a flash memory device, characterized in that the upper edge portion is formed rounded. Forming a tunnel oxide film, a floating gate layer, and a buffer insulating layer on the semiconductor substrate on which the device isolation film is formed; Etching a portion of the buffer insulating layer and the exposed portion of the floating gate layer by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a conductive layer along surfaces of the trenched floating gate layer and the patterned buffer insulating layer; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Removing a buffer insulating layer over the patterned floating gate layer; Forming a dielectric film on the patterned floating gate layer; And And forming a control gate and a floating gate. The method of claim 5, wherein The buffer insulating layer is a method of manufacturing a flash memory device, characterized in that formed in the oxide-based or nitride-based. The method of claim 5, wherein And the conductive layer is formed of any one of doped polycrystalline silicon, undoped polycrystalline silicon, and implanted polycrystalline silicon. The method of claim 5, wherein The patterned floating gate layer is a method of manufacturing a flash memory device, characterized in that the conductive layer in the form of a spacer on both sides. The method of claim 5, wherein The patterned floating gate layer is a manufacturing method of a flash memory device, characterized in that the upper edge portion is formed rounded. Forming a tunnel oxide film, a floating gate layer, and a buffer insulating layer on the semiconductor substrate on which the device isolation film is formed; Etching a portion of the buffer insulating layer and the exposed portion of the floating gate layer by an etching process using a mask for floating gate, thereby forming a trench in the floating gate layer above the device isolation layer; Forming a selective epitaxial silicon growth layer in the floating gate layer of the trench portion; Patterning the floating gate layer by performing an anisotropic etching process until the device isolation layer is exposed; Removing a buffer insulating layer over the patterned floating gate layer; Forming a dielectric film on the patterned floating gate layer; And And forming a control gate and a floating gate. The method of claim 10, The buffer insulating layer is a method of manufacturing a flash memory device, characterized in that formed in the oxide-based or nitride-based. The method of claim 10, The patterned floating gate layer is a method of manufacturing a flash memory device, characterized in that the selective epitaxial silicon growth layer on both sides is in the form of a spacer. The method of claim 10, The patterned floating gate layer is a manufacturing method of a flash memory device, characterized in that the upper edge portion is formed rounded.