KR20040070615A - A semiconductor memory device having internal voltage measuring circuits and the internal voltage measuring method - Google Patents

Abstract

PURPOSE: A semiconductor memory device provided with an internal voltage measuring circuits and a method for measuring the internal voltage for the same are provided to measure the change of the transient inner voltage when the semiconductor memory device in the form of package operates at a high frequency. CONSTITUTION: A semiconductor memory device(100) provided with an internal voltage measuring circuits includes an inner voltage generator(101) and an inner voltage measuring circuit(102). The inner voltage generator(101) receives the external voltage and generates the inner voltage. The inner voltage measuring circuit(102) converts the inner voltage into a first digital data in response to a predetermined control signal to output the converted first digital data to the first output pad. And, the inner voltage measuring circuit(102) converts the direct voltage inputted to the first input pad into a second digital data to output the converted second digital data to the first output pad.

Description

A semiconductor memory device having internal voltage measuring circuits and the internal voltage measuring method

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an internal voltage measuring circuit and an internal voltage measuring method thereof.

In general, an internal voltage generated by an internal voltage generator is supplied to a semiconductor memory device as an operating power source. The internal voltage generator generates an internal voltage by stepping down a relatively high external power supply voltage supplied from the outside. The internal voltage is preferably low in voltage level variation for stable operation of the semiconductor chip. The level variation of the internal voltage serves as an important factor in determining the operating characteristics of the semiconductor memory device.

However, due to the memory cell array structure composed of a plurality of word lines and a plurality of bit lines, the level of the internal voltage is changed instantaneously when the semiconductor memory device operates or the semiconductor memory device is tested. In more detail, when a plurality of word lines are activated at the same time, the level of the internal voltage is instantaneously lowered because the same internal voltage is dividedly supplied to the plurality of word lines. In addition, when a plurality of word lines are precharged at the same time, the level of the internal voltage is momentarily high.

This internal voltage must be maintained within a predetermined voltage level range for stable operation of the semiconductor chip. Therefore, the measurement data for the internal voltage whose voltage level changes as the semiconductor memory device operates is utilized as data for designing a semiconductor circuit having more stable operation characteristics.

Conventionally, an oscilloscope is used to measure the internal voltage of a semiconductor memory device. The semiconductor memory device also includes an internal voltage generator circuit for generating an internal voltage to be measured by the oscilloscope in a test mode. The internal voltage generator generates an internal voltage according to a predetermined reference voltage in a test mode and outputs the internal voltage to the pad. The oscilloscope measures the internal voltage output to the pad.

An example of a semiconductor memory device having such an internal voltage generator circuit is described in US Patent No. 6,339,357.

An internal voltage measurement process of a semiconductor memory device having an internal voltage generation circuit as described in US Patent No. 6,339,357 will be described in more detail with reference to FIGS. 1 and 2 as follows.

1 is an enlarged view schematically illustrating a semiconductor chip on a wafer in order to explain an internal voltage measuring method according to the related art.

As shown in FIG. 1, a plurality of semiconductor chips 11 are designed on the wafer 10. In addition, pads 12, 13, 14, and 15 for internal voltage monitors are formed on each of the plurality of semiconductor chips 11 to measure the level change of the internal voltage.

Conventionally, the internal voltage of a semiconductor chip is measured by an oscilloscope in a wafer state when the semiconductor chip is produced. That is, the output waveforms of the pads 12, 13, 14, and 15 are measured by contacting probes of the oscilloscope with the pads 12, 13, 14, and 15 for the internal voltage monitor. An example of the output waveform is shown in FIG.

2 is a view illustrating an internal voltage measurement waveform according to the related art, and illustrates a measurement waveform of a boosted voltage VPP among internal voltages.

As shown in FIG. 2, the boosted voltage VPP is measured for a predetermined measurement period. The measurement period is preferably from the time when the word line is activated to the precharge by the ras bar signal RASB.

As shown in FIG. 2, actually, undershooting occurs momentarily when the word line is active, and overshooting occurs momentarily when the word line is precharged.

However, in the conventional internal voltage measurement, when the semiconductor chip is operated in the test mode, only the average value of the internal voltage is measured. Thus, as shown in FIG. Not measured

In addition, since the conventional internal voltage measuring method measures the internal voltage of the semiconductor chip on the wafer, the internal voltage characteristic of the semiconductor memory device in the package state is inferred based on the data measured in the wafer state. Therefore, there is a problem in that the difference between the internal voltages of the semiconductor chips in the package state and the wafer state is unknown.

On the other hand, conventionally, since the internal voltage is measured when the semiconductor chip is in the test mode, there is a problem in that the characteristics of the internal voltage when the semiconductor chip is actually operated at a high frequency cannot be confirmed.

An object of the present invention is to provide a semiconductor memory device having an internal voltage measuring circuit for measuring a change in the instantaneous internal voltage when the semiconductor memory device in a package state is operated at a high frequency and an internal voltage measuring method thereof. .

1 is an enlarged view schematically illustrating a semiconductor chip on a wafer in order to explain an internal voltage measuring method according to the related art.

2 is a view showing an internal voltage measurement waveform according to the prior art.

3 is a block diagram schematically illustrating a semiconductor memory device having an internal voltage measurement circuit according to the present invention.

4 is a block diagram illustrating an internal voltage measuring circuit according to a first exemplary embodiment of the present invention.

FIG. 5 is a detailed block diagram of the delay circuit shown in FIG. 4.

FIG. 6 is a detailed circuit diagram of the sample and hold circuit shown in FIG. 4.

FIG. 7 is a detailed circuit diagram of the A / D converter shown in FIG. 4.

FIG. 8 is a timing diagram illustrating main input / output signals of the internal voltage measuring circuit shown in FIG. 4.

9 is a block diagram illustrating an internal voltage measuring circuit according to a second exemplary embodiment of the present invention.

10 is a flowchart illustrating a process of measuring an internal voltage of a semiconductor memory device according to the present invention.

FIG. 11 is a flowchart illustrating a table generation process of FIG. 10 in detail.

FIG. 12 is a flowchart illustrating a digital data extraction process for the internal voltage shown in FIG. 10 in detail.

According to another aspect of the present invention, there is provided a semiconductor memory device having an internal voltage measuring circuit including a plurality of data input pads including a first input pad and a second input pad, and a first output pad. A semiconductor memory device having a plurality of data output pads included therein, the semiconductor memory device comprising an internal voltage generator and an internal voltage measuring circuit. The internal voltage generator receives an external voltage and generates an internal voltage. The internal voltage measuring circuit converts the internal voltage into first digital data and outputs the first voltage to the first output pad in response to a predetermined control signal, and converts the DC voltage received by the first input pad into second digital data and outputs the first output. Output to the pad.

In order to achieve the above technical problem, an internal voltage measuring method of a semiconductor memory device having an internal voltage measuring circuit according to an embodiment of the present invention may convert a predetermined internal voltage into first digital data and output the predetermined DC voltage. An internal voltage measuring method of a semiconductor memory device comprising an internal voltage measuring circuit for converting a second data into second digital data and outputting the second digital data;

(a) extracting the second digital data from the DC voltage having a predetermined voltage level range to generate a reference table;

(b) extracting the first digital data from the internal voltage in response to a predetermined control signal;

(c) confirming the DC voltage level for the first digital data from the reference table;

(d) repeating steps (b) and (c) when there is the internal voltage to be further measured; And

(e) further stopping the measuring operation of the internal voltage when there is no internal voltage to be measured.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram schematically illustrating a semiconductor memory device having an internal voltage measurement circuit according to the present invention.

As shown in FIG. 3, the semiconductor memory device 100 having the internal voltage measuring circuit according to the present invention includes an internal voltage generator 101, an internal voltage measuring circuit 102, a memory cell array 103, a peripheral circuit 104, and the like. A plurality of input and output pads 105 to 110 are provided.

The memory cell array 103 and the peripheral circuit 104 may be understood by those of ordinary skill in the art, and thus a detailed description thereof will be omitted.

The internal voltage generator 101 generates an internal voltage VINT from an external voltage Vcc input to the power pin 111. The internal voltage VINT may preferably include a boosted voltage VPP, a substrate voltage VBB, a memory cell array voltage Vcca, a bit line voltage VBL, and the like.

The internal voltage measuring circuit 102 receives the control signal CTL through the control pin 112 and inputs the delay data RD1 to RDM (the input / output pin 113 through the input pad 105). M is a natural number of 2 or more).

The internal voltage measuring circuit 102 extracts digital data DIN for the internal voltage VINT at a predetermined operation time of the semiconductor memory device in response to the control signal CTL. Here, the measurement time point for the internal voltage VINT, that is, the extraction time point of the digital data DIN may be set by the delay data RD1 to RDM.

The internal voltage measuring circuit 102 outputs the extracted digital data DIN to the data input / output pin 115 through the output pad 107.

Meanwhile, the internal voltage measuring circuit 102 receives a table DC voltage VTB input to the data input / output pin 114 through the input pad 106.

The range of the table DC voltage VTB level is set based on the internal voltage VINT to be measured. In more detail, the range of the table DC voltage VTB level is the internal voltage VINT level ± ΔV.

The internal voltage measuring circuit 102 extracts the digital data DTB of the table DC voltage VTB and outputs the digital data DTB to the data input / output pin 115 through the output pad 107. The digital data DTB for the table DC voltage VTB may be stored in a separate memory (not shown) outside the semiconductor memory device.

Here, the digital data DTB for the table DC voltage VTB is used as a reference value for checking the actual DC voltage level of the internal voltage VINT.

The digital data DTB table for the DC voltage VTB for the table may be generated before the measuring operation of the internal voltage VINT. The digital data DTB table may be generated after the measurement operation of the internal voltage VINT. However, in this case, the digital data DIN for the internal voltage VINT needs to be stored in an external separate memory (not shown).

The reason why the same internal voltage measuring circuit 102 is used for both the generation of the table and the measurement of the internal voltage is that the operating characteristics of the semiconductor memory device change according to process, voltage, and temperature changes. .

In other words, the digital data of the table generated by the internal voltage measuring circuit of any semiconductor memory device may be different from the digital data of the table generated by the internal voltage measuring circuit of another semiconductor memory device.

Therefore, for a more accurate measurement of the internal voltage, it is desirable that the table be generated by the same internal voltage measurement circuit.

4 is a block diagram illustrating an internal voltage measuring circuit according to a first exemplary embodiment of the present invention.

In FIG. 4, the internal voltage measurement circuit 102 includes a first resistor 210, a delay circuit 220, a sample and hold circuit 230, a mux 240, an A / D converter 250, and a second resistor ( 260.

The first register 210 receives and stores serially input delay data RD1 to RDM from an input pad 105 (see FIG. 3). The first register 210 converts the delay data RD1 to RDM into parallel data in response to a predetermined first enable signal ENR1 and outputs the parallel data.

The delay circuit 220 has a delay time set by the delay data RD1 to RDM. The delay circuit 220 outputs a plurality of control pulse signals S1 to S3 by delaying the control signal CTL input from the outside for a predetermined time.

Here, the control signal CTL may preferably include a ras bar signal / RAS or a cas bar signal / CAS.

In response to the plurality of control pulse signals S1 to S3, the sample and hold circuit 230 receives and samples the internal voltage VINT to be measured, and amplifies and outputs the sampled voltage VS. . The sample and hold circuit 230 receives a predetermined first reference voltage VREF1.

The mux 240 outputs any one of the sampling voltage VS and the table DC voltage VTB in response to a predetermined selection signal SEL.

The A / D converter 250 receives one of the sampling voltage VS and the table DC voltage VTB and a predetermined second reference voltage VREF2.

Here, the first and second reference voltages VREF1 and VREF2 are output from separate reference voltage generation circuits (not shown) and have a constant voltage level.

The A / D converter 250 generates and outputs digital data DIN from the sampling voltage VS. The A / D converter 250 generates and outputs digital data DTB from the table DC voltage VTB.

The second register 260 stores the digital data DIN or DTB output from the A / D converter 250 and, in response to the second enable signal ENR2, as shown in FIG. 8. The digital data DIN or DTB is converted into parallel data and output to the output pad 107 (see FIG. 3).

FIG. 5 is a detailed block diagram of the delay circuit shown in FIG. 4.

In FIG. 5, the delay circuit 220 includes a delay chain 221 and a pulse signal generator 222. The delay chain 221 includes a plurality of switching circuits N1 to NM (M is a natural number of two or more) and a plurality of delay cells 41 to 4M.

The plurality of switching circuits N1 to NM are turned on or off in response to the delay data RD1 to RDM, and each of the plurality of delay cells 41 to 4M drives the inverters 61 to 6M. Include. Each of the plurality of switching circuits N1 to NM may be preferably implemented as an NMOS transistor. The delay data RD1 to RDM are input to gates of the NMOS transistors N1 to NM. In addition, the source and the drain of the NMOS transistors N1 to NM are connected to the input and the output of the delay cells 41 to 4M, respectively. The delay cells 41 to 4M are connected in series between an input node NIN and an output node NOUT. The delay cells 41 to 4M output a delayed input signal by a predetermined time.

The control signal CTL is input to the input node NIN, and the control signal DCTL delayed from the output node NOUT is output.

Here, the operation of the delay chain 221 will be described in more detail as follows.

First, assume that the delay data RD1 and RD2 are "HIGH" and the remaining delay data RD2 to RDM are "LOW". Only the NMOS transistors N1 and N2 are turned on by the delay data RD1 and RD2, and the remaining NMOS transistors N3 to NM are turned off.

As the NMOS transistors N1 and N2 are turned on, the control signal CTL is transmitted through the NMOS transistors N1 and N2 without passing through the delay cells 41 and 42.

In addition, as the remaining NMOS transistors N3 to NM are turned off, the control signal CTL output from the NMOS transistor N2 is delayed by a predetermined time while passing through the delay cells N3 to NM. As a result, the control signal CTL is output as the control signal DCTL delayed by the delay chain 221 at the output node NOUT.

The pulse signal generator 222 outputs predetermined pulse control signals S1 to S3 in response to the delayed control signal DCTL.

FIG. 6 is a detailed circuit diagram of the sample and hold circuit shown in FIG. 4.

As illustrated in FIG. 6, the sample and hold circuit 230 includes first to third switching circuits 231 to 233, a capacitor C, and an OP amplifier 234. The first to third switching circuits 231 may be preferably implemented as NMOS transistors. A gate of the first NMOS transistor 231 receives the pulse control signal S1, a drain is connected to an internal voltage VINT, and a source is connected to a first node NODE1. The anode of the capacitor C is connected to the first node NODE1 and the cathode is connected to the second node NODE2.

A gate of the second NMOS transistor 232 receives the pulse control signal S2, a drain is connected to the second node NODE2, and a source is connected to the third node NODE3. A gate of the third NMOS transistor 233 receives the pulse control signal S3, a drain is connected to the first node NODE1, and a source is connected to the third node NODE3.

The non-inverting terminal (+) of the OP amplifier 234 is connected to the second node (NODE2), the inverting terminal (-) receives a predetermined first reference voltage (VREF1).

The sample and hold circuit 230 samples the internal voltage VINT in response to the pulse control signals S1 to S3, holds the sampling value for a predetermined time, and then stores the sampled voltage VS. Amplified and output to the third node (NODE3). This will be described in more detail as follows. First, referring to FIG. 8, in response to the delayed control signal DCTL, the pulse control signals S1 and S2 are enabled for a predetermined period, and then disabled. The first and second NMOS transistors 231 and 232 are turned on for the predetermined time in response to the pulse control signals S1 and S2. The first NMOS transistor 231 outputs the internal voltage VINT to the first node NODE1. The capacitor C receives the internal voltage VINT and is charged to the internal voltage VINT level.

When the pulse control signals S1 and S2 are disabled, the pulse control signal S3 is enabled. In addition, when the pulse control signal S3 is enabled, the capacitor C discharges the sampled voltage VS to the second node NODE2.

The OP amplifier 234 amplifies the sampled voltage VS and outputs the amplified voltage to the third node NODE3.

FIG. 7 is a detailed circuit diagram of the A / D converter shown in FIG. 4. As shown in FIG. 7, the A / D converter 250 includes a plurality of comparators 51 to 5N. Predetermined reference voltages V1 to VN are input to the non-inverting terminals + of the plurality of comparators 51 to 5N, and the sampling voltage VS or the table DC voltage to the inverting terminal −. VTB) is input.

The reference voltages V1 to VN are voltages in which a predetermined second reference voltage VREF2 is dropped by the plurality of resistors R1 to RN, respectively.

The plurality of comparators 51 to 5N compare the sampling voltage VS or the table DC voltage VTB with the reference voltages V1 to VN, as shown in FIG. (1) "or" LOW (0) "digital data D1 to DN are output. This will be described in more detail as follows.

First, the A / D converter 250 includes four comparators 51 to 54, and the sampling voltage VS of 1.2 V is input to the inverting terminal (−) of the comparators 51 to 54. Assume that Also, assume that the reference voltages V1 to V4 are 1.4V, 1.3V, 1.1V, and 1.0V, respectively.

The comparators 51 and 52 output digital data D1 and D2 of "0" because the sampling voltage VS is lower than the reference voltages V1 and V2. The comparators 53 and 54 output digital data D3 and D4 of "1" because the sampling voltage VS is higher than the reference voltages V3 and V4.

As a result, the A / D converter 250 outputs digital data DIN of “0011” when the sampling voltage VS is 1.2V.

In addition, the A / D converter 250 operates in the same manner as when the sampling voltage VS is input even when the table DC voltage VTB is input to output the digital data DTB.

In FIG. 7, for example, the A / D converter 250 includes four comparators 51 to 54, but the number of the comparators included in the A / D converter 250 is the digital data. It can be set variously according to the bit of (DIN). The bits of the digital data DIN are preferably at least two bits.

9 is a block diagram illustrating an internal voltage measuring circuit according to a second exemplary embodiment of the present invention.

As shown in FIG. 9, the internal voltage measuring circuit 300 according to the second embodiment of the present invention may include a first resistor 310, a delay circuit 320, a first mux 330, a sample and hold circuit 340, A second mux 350, an A / D converter 360, and a second register 370 are provided.

Since the configuration and specific operation of the internal voltage measurement circuit 300 are the same as the internal voltage measurement circuit 102 described above, a detailed description thereof will be omitted.

However, the internal voltage measuring circuit 300 is different from the internal voltage measuring circuit 102 in that it further includes the first mux 330.

The first mux 330 outputs any one of a plurality of internal voltages VINT1 to VINT3 in response to a predetermined first selection signal SEL1. The internal voltage measuring circuit 300 may select and measure a desired internal voltage among the plurality of internal voltages VINT1 to VINT3 by the first mux 330.

Next, a detailed operation of the internal voltage measuring circuit 102 configured as described above will be described with reference to FIGS. 10 to 12.

10 is a flowchart 1000 illustrating a process of measuring an internal voltage of a semiconductor memory device according to the present invention.

As shown in FIG. 10, first, a table of digital data DTB for a table DC voltage VTB having a predetermined voltage level range is generated (1100). Here, the step 1100 will be described later in more detail with reference to FIG.

Next, the digital data DIN for the internal voltage VINT to be measured is extracted (1200). Here, the step 1200 will be described in more detail with reference to FIG. Thereafter, the DC voltage level of the digital data DIN with respect to the internal voltage VINT is checked from the digital data DTB table (1300).

It is determined whether there is an additional internal voltage VINT to be measured (1400). When there is an additional internal voltage VINT to be measured in step 1400, the process returns to step 1200 and the processes are repeated. Further, when there is no additional internal voltage VINT to be measured, the internal voltage measurement operation is stopped and terminated (1500).

FIG. 11 is a flowchart 1100 illustrating the table generation process of FIG. 10 in detail.

As shown in FIG. 11, first, a range of a table DC voltage VTB level is set based on an internal voltage VINT level to be measured (1101). For example, when the internal voltage VINT to be measured is 3V, the table DC voltage VTB may be set to 3V ± 0.5V. As a result, the digital data DTB for the table DC voltage VTB of 2.5 V to 3.5 V is extracted by the internal voltage measuring circuit 102. Here, the table DC voltage VTB should be set to include both the minimum voltage and the maximum voltage according to the level change of the internal voltage VINT to be measured.

Thereafter, the test DC voltage VTB within the set range is input to the mux 240 of the internal voltage measuring circuit 102 (1102). The mux 240 outputs the test DC voltage VTB to the A / D converter 250 in response to a predetermined selection signal SEL. The A / D converter 250 obtains digital data DTB having a predetermined number of bits for the test DC voltage VTB (1103).

Here, the A / D converter 250 outputs the digital data DTB by comparing the test DC voltage VTB to predetermined reference voltages V1 to VN.

In addition, the digital data DTB is stored in the second register 260 of the internal voltage measuring circuit 102. The second register 260 converts the digital data DTB into serial data and outputs the serial data in response to the second enable signal ENR2.

The second register 260 outputs the digital data DTB to the outside of the semiconductor memory device through the output pad 107, and the digital data DTB is stored in a separate memory (not shown) (1104). ).

As such, the reason why the digital data DTB is stored in the second register 260 and output at a specific time point is to prevent the other data output through the output pad 107 from being affected.

Thereafter, it is determined whether the test DC voltage VTB is at the maximum voltage level (1105). When the test DC voltage VTB is not at the maximum voltage level in step 1105, after the level of the test DC voltage VTB is increased, the process returns to step 1102 to repeat the processes. Perform.

When the test DC voltage VTB is at the maximum voltage level in step 1105, the table generating operation is stopped and terminated (1107).

FIG. 12 is a flowchart 1200 illustrating a digital data extraction process for the internal voltage illustrated in FIG. 10 in detail.

As shown in FIG. 12, first, delay data RD1 to RDM are input to the first register 210 of the internal voltage measuring circuit 102 through the input pad 105. The first register 210 stores the delay data RD1 to RDM and converts the delay data RD1 to RDM into parallel data in response to a predetermined first enable signal ENR1. To 220).

The delay circuit 220 has a delay time set by the delay data RD1 to RDM (1201). Next, a control signal CTL is input to the delay circuit 220 (1202). The delay circuit 220 delays the control signal CTL for a set delay time and outputs a plurality of control pulse signals S1 to S3 (1203).

Thereafter, the sample and hold circuit 230 samples the internal voltage VINT according to the control pulse signals S1 to S3 to obtain a sampling voltage VS, and amplifies and outputs the sampling voltage VS. (1204). At this time, the mux 240 outputs the sampling voltage VS to the A / D converter 250 in response to the selection signal SEL.

The A / D converter 250 obtains digital data DIN having a predetermined number of bits for the sampling voltage VS (1205).

The A / D converter 250 outputs the digital data DIB by comparing the sampling voltage VS to predetermined reference voltages V1 to VN.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the semiconductor memory device having the internal voltage measuring circuit of the present invention and the internal voltage measuring method thereof, it is possible to measure the instantaneous change in the internal voltage when the semiconductor memory device in a package state is operated at a high frequency. It works.

Claims (14)

A semiconductor memory device comprising a plurality of data input pads including a first input pad and a second input pad, and a plurality of data output pads including a first output pad. An internal voltage generator for receiving an external voltage and generating an internal voltage; And In response to a predetermined control signal, the internal voltage is converted into first digital data and output to the first output pad, and the direct current voltage received by the first input pad is converted into second digital data to output the first output pad. A semiconductor memory device having an internal voltage measuring circuit, characterized in that it comprises an internal voltage measuring circuit for outputting the signal. The method of claim 1, wherein the control signal, 12. A semiconductor memory device having an internal voltage measurement circuit comprising any one of a ras bar signal and a cas bar signal. The circuit of claim 1, wherein the internal voltage measuring circuit comprises: A first register configured to store delay data input to the second input pad and to output the delay data in response to a first enable signal; A delay circuit having a delay time set by the delay data and delaying the control signal during the delay time to output a plurality of pulse control signals; A sample and hold circuit for sampling the internal voltage in response to the plurality of pulse control signals and amplifying and outputting the sampling voltage; A first mux circuit outputting any one of the sampling voltage and the DC voltage in response to a first predetermined selection signal; An A / D converter to A / D convert the sampling voltage to output the first digital data, and to convert the DC voltage to A / D to output the second digital data; And A second register outputting the first digital data to the first output pad in response to a second enable signal, and outputting the second digital data to the first output pad in response to the second enable signal; A semiconductor memory device having an internal voltage measurement circuit comprising: The method of claim 3, The first register converts the delay data into parallel data and outputs the parallel data; And the second register converts the first digital data into first serial data and outputs the converted second digital data into second serial data and outputs the converted second digital data. The method of claim 4, wherein the delay circuit, A delay chain having a delay time set by the delay data and delaying and outputting the control signal during the delay time; And And a pulse signal generator configured to output the plurality of pulse control signals including first to third pulse control signals in response to the delayed control signal. The method of claim 5, wherein the delay chain, A plurality of switching circuits switched on / off by the delay data; And And a plurality of delay cells connected in parallel to each of the plurality of switching circuits, and having a plurality of delay cells outputting the control signal by a predetermined time when the switching circuit is turned off. Semiconductor memory device. The method of claim 3, wherein the A / D converter, And a plurality of comparators for outputting any one of a high signal and a low signal by comparing an input voltage to a plurality of reference voltages. The method of claim 7, wherein the plurality of reference voltages, A semiconductor memory device having an internal voltage measuring circuit, characterized in that the predetermined reference control voltage is voltages stepped down by a plurality of resistors having different resistances. The method of claim 3, The internal voltage generator generates a plurality of internal voltages from the external voltage, The internal voltage measuring circuit further includes a second mux circuit outputting any one of a plurality of internal voltages to the sample and hold circuit in response to a second predetermined selection signal. Semiconductor memory device. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And a reference table for confirming the level of the DC voltage with respect to the first digital data, further comprising an external memory storing the second digital data. An internal voltage measuring method of a semiconductor memory device comprising an internal voltage measuring circuit converting a predetermined internal voltage into first digital data and outputting the converted digital voltage to second digital data and outputting the converted digital voltage. To (a) extracting the second digital data from the DC voltage having a predetermined voltage level range to generate a reference table; (b) extracting the first digital data from the internal voltage in response to a predetermined control signal; (c) confirming the DC voltage level for the first digital data from the reference table; (d) repeating steps (b) and (c) when there is the internal voltage to be further measured; And (e) when the internal voltage to be measured is not present, stopping the measuring operation of the internal voltage. The method of claim 11, wherein step (a) comprises: (a) setting the voltage level range of the direct current voltage; (b) inputting the DC voltage into the internal voltage measuring circuit through a predetermined first data input pad; (c) A / D converting the DC voltage to obtain the first digital data; (d) reading the first digital data and storing the first digital data in the memory; (e) increasing the level of the DC voltage at predetermined voltage level intervals, and then repeating steps (b) to (d); And (f) repeating step (e) until the DC voltage reaches a maximum voltage level in the voltage level range. The method of claim 12, wherein the voltage level range of the DC voltage is set based on the level of the internal voltage. The method of claim 11, wherein step (b) comprises: (a) setting a delay time based on delay data input through a predetermined second data input pad; (b) delaying the control signal during the delay time to output a plurality of pulse control signals; (c) sampling the internal voltage in response to the plurality of pulse control signals, and amplifying and outputting the sampled voltage; And (d) A / D converting the sampled voltage to obtain the second digital data.