KR20040068774A - Liquid crystal display of line-on-glass type - Google Patents

Abstract

PURPOSE: A line-one-glass LCD(Liquid Crystal Display) is provided to minimize resistance of a gate current path including resistance of a line-on-glass signal line. CONSTITUTION: A line-on-glass LCD includes an LCD module, the first and second tape carrier packages(62,58), the first and second printed circuit boards(66,78), a line-on-glass type signal lines, and a conductive bottom cover(102). The LCD module includes a liquid crystal cell matrix. The first tape carrier packages include data driving circuits(64) for driving data lines of the liquid crystal cell matrix and are connected to the LCD module. The second tape carrier packages include gate driving circuits(60) for driving gate lines of the liquid crystal cell matrix and are connected to the LCD module. The first printed circuit board supplies the first driving signals to be provided to the data driving circuits and the second driving signals to be provided to the gate driving circuits to the first tape carrier packages. The second printed circuit board supplies the second driving signals to the second tape carrier packages. The line-on-glass type signal lines supply the second driving signals from the first printed circuit board to the second printed circuit board. The conductive bottom cover protects the LCD module and is connected in parallel with one of the line-on-glass type signal lines through the first and second printed circuit boards.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY OF LINE-ON-GLASS TYPE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing signal distortion caused by a line-on-glass signal line.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on a tape carrier package (TCP) and electrically connected to the liquid crystal display panel by a tape automated bonding (TAB) method. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing controller and power supply of the main PCB through a flexible printed circuit (FPC) and a sub-PCB. Specifically, the data drive ICs are supplied with data control signals and pixel data from the timing controller and power signals from the power supply via the main PCB-> first FPC-> data PCB-> data TCP. Gate drive ICs receive gate control signals from the timing controller and power signals from the power supply via the main PCB-> first FPC-> data PCB-> second FPC-> gate PCB-> gate TCP. .

The drive ICs mounted on the liquid crystal display panel in the COG method are controlled from a timing controller mounted on the main PCB through line-on-glass type signal lines formed on the FPC and the liquid crystal display panel. Signals and pixel data and power signals from the power supply unit.

On the other hand, in order to further reduce the thickness of the liquid crystal display device, even when the drive ICs are connected to the liquid crystal display panel through TCP, LOG type signal lines are adopted to eliminate the FPC and / or the PCB.

For example, the FPC connecting the data PCB and the gate PCB is removed, and signal lines for supplying gate control signals and power signals to the gate PCB are formed on the liquid crystal display panel in a LOG type. Accordingly, the gate drive ICs mounted on the gate TCP are separated from the timing controller via the main PCB-> FPC-> data PCB-> data TCP-> LOG type signal line-> gate TCP-> gate PCB-> gate TCP. The gate control signals and power signals from the power supply unit are supplied.

In addition, the FPC and gate PCB connected to the data PCB are removed, and signal lines for supplying gate control signals and power signals to the gate drive ICs are formed on the liquid crystal display panel. Accordingly, the gate drive ICs mounted on the gate TCP are connected to the gate control signals from the timing controller and the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG type signal line-> gate TCP. Power signals are supplied.

However, the LOG signal lines have a relatively large line resistance as they are formed in a fine pattern in a limited area of the outer portion of the liquid crystal display panel. Accordingly, the gate control signals and the power signals supplied through the LOG signal lines are distorted.

Specifically, the LOG type liquid crystal display device in which the FPC between the data PCB and the gate PCB is removed includes the main PCB 20 including the timing controller 22 and the power supply unit 24 and the FPC 28 as shown in FIG. 1. A data PCB 16 connected to the main PCB 20 through the main circuit 20, a data driver IC 14 mounted thereon, and a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6; The gate driver IC 10 is mounted to include a gate TCP 8 connected to the liquid crystal display panel 6 and a gate PCB 18 connected to the gate TCP 8.

The liquid crystal display panel 6 is formed by bonding the thin film transistor array substrate 2 and the color filter array substrate 4 to each other with a liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL. The liquid crystal cell implements gradation by adjusting the light transmittance according to the supplied pixel signal.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 28. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

The gate control signals and the power signals supplied to the gate drive IC 10 are first received from the timing controller 22 and the power supply 24 on the main PCB 20 via the FPC 18 and the data PCB 16. Data is supplied to the TCP 12. The gate control signals and the power signals supplied through the first data TCP 12 are transmitted to the first gate TCP 8 via the LOG signal line group 26 formed in the edge region of the thin film transistor array substrate 2. Supplied. Gate control signals and power signals supplied to the first gate TCP 8 are supplied to each of the gate TCPs 8 via the gate PCB 18 and gate control signals supplied to each of the gate TCPs 8. And power signals are supplied to and used by the gate drive IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 together with the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. Power signals; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG signal line group 26 is formed in a fine pattern using the same gate metal layer as the gate lines in the limited pad region of the thin film transistor array substrate 2. Accordingly, the LOG signal line group 26 has a larger line resistance than the conventional FPC. As a result, the gate control signals GSP, GSC, and GOE transmitted through the LOG signal line group 26 and the power signals VGH, VGL, VCC, GND, and VCOM are distorted, thereby causing crosstalk, Image degradation such as Greenish and Flicker will occur. In particular, the waveform distortion of the gate low voltage VGL among the power signals and the gate control signals supplied through the LOG signal line group 26 is a main cause of the above-described deterioration of image quality. The waveform distortion of the gate low voltage VGL is coupled to the ground line forming a current path together with the gate low voltage VGL.

For example, when a column line pattern in which black gray and 31 gray alternate in units of pixels (including R, G, and B sub-pixels) is displayed on a liquid crystal display panel driven by a dot inversion method as illustrated in FIG. 2. A greenish phenomenon in which the G sub-pixels appear bright occurs.

Specifically, as shown in FIG. 2, when a column line pattern in which black gray and 31 gray are alternately displayed, sub-pixels adjacent to left and right display different grays, and thus, pixel signal transition sizes between the sub-pixels are different. Accordingly, the coupling values of adjacent pixels through the parasitic capacitors do not cancel each other. As a result, the common voltage VCOM and the gate low voltage VGL of the direct current type supplied to the liquid crystal display panel are shown in FIGS. 3A and 3B. As shown in the figure, swing along the data signal.

3A and 3B show a common voltage VCOM and gate low voltage VGL waveforms swinged by parasitic capacitors when a black gray signal and a 31 gray signal are supplied in a dot inversion manner to a specific data line. . Here, it can be seen that the common voltage VCOM and the gate low voltage VGL swing with the same phase as the black gray signal having a relatively large voltage.

As a result, when the black pixel signal is supplied to each of R1, G1, and B1 shown in FIG. 2 and the pixel signal of 31 gray is supplied to each of R2, G2, and B2, as shown in FIG. 4, the swing is performed along the black pixel signal. Due to the common voltage VCOM, the pixel signal charge values VG1, VR2, and VB2 of the pixel signals charge values VR1, VG1, and VB2 of R1, B1, and G2 become smaller than the pixel voltage charge values VG1, VR2, and VB2. Accordingly, the G1, R2, and B2 pixels appear relatively bright. R1 and B1 to which the black pixel signal is supplied cannot be visually detected, so only the G2 pixel to which 31 gray is supplied appears to be bright, resulting in a greenish phenomenon.

In addition, as shown in FIG. 5, when a pattern in which 31 gray and black gray are alternately displayed in units of sub-pixels is displayed on a liquid crystal panel, and a window W displaying the same gray is displayed in a specific area, the window area W is displayed. Since the same gray is displayed, the pixel signal transition size between adjacent pixels cancels out. Accordingly, as shown in FIG. 6, the swing widths of the gate low voltage VGL and the common voltage VCOM in the T2 section including the window region W may include T1 not including the window region W. It becomes smaller than the interval. Therefore, the driving value of the pixels in the T2 section including the window area W and the T1 section not included in the window area W are changed. Specifically, as shown in FIG. 7, when the lines R1, G1, and B1 are examined, the lines R1 and B1 are charged in the T1 section except for the G1 line (not visually sensed) to which the black pixel signal is supplied (VR1, VB1). It can be seen that the charge amounts VR2 and VB2 in the T2 section are smaller. As a result, horizontal crosstalk may be generated in which pixels driven in the T2 section including the window region W appear relatively brighter than pixels driven in the T1 section including the window region W. FIG.

The swing voltages of the common voltage VCOM and the gate low voltage VGL, which cause greenish and crosstalk, are thus induced to the ground voltage which forms a gate current path with them. Accordingly, when the resistance of the ground line to which the ground voltage is supplied is large, the resistance of the gate current path increases, thereby increasing the swing width of the common voltage VCOM and the gate low voltage VGL. However, in the conventional liquid crystal display, the ground line includes a LOG type ground line including a resistance component of about several tens of Ω, and thus includes a relatively large resistance component. As a result, the resistance of the gate current path increases to increase the swing widths of the common voltage VCOM and the gate low voltage VGL, thereby causing the problem of the above-described greenish and horizontal crosstalk phenomena becoming clear.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device capable of minimizing the resistance of a gate current path including a resistance of a LOG type signal line.

1 is a plan view showing a line-on glass liquid crystal display device with a conventional FPC removed.

2 is a view showing a specific pattern causing greenish in the conventional liquid crystal display.

3A and 3B show a comparison of a swing width between a common voltage and a gate low voltage due to the specific pattern shown in FIG.

4 is a view for explaining a greenish phenomenon caused by the swing of the common voltage shown in FIGS. 3A and 3B.

FIG. 5 illustrates a specific pattern including a window causing horizontal crosstalk in a conventional liquid crystal display. FIG.

FIG. 6 is a diagram illustrating a comparison of a swing width between a common voltage and a gate low voltage in a section including the window region illustrated in FIG. 5 and a section not including the window region.

FIG. 7 is a view for explaining a horizontal crosstalk phenomenon caused by the swing of the common voltage shown in FIG.

FIG. 8 is a plan view illustrating a liquid crystal display module including a line on glass type liquid crystal display without FPC according to an exemplary embodiment of the present invention. FIG.

FIG. 9 is a plan view partially showing a rear portion of the liquid crystal display module shown in FIG. 8; FIG.

FIG. 10 is a cross-sectional view of the liquid crystal display module cut along the line Ι-Ι 'shown in FIG. 9. FIG.

11 is a waveform diagram showing a comparison between the gate low voltage of the prior art and the present invention.

<Description of main parts of drawing>

2, 52: thin film transistor array substrate 4, 54: color filter array substrate

6, 56: liquid crystal display panel 8, 58: gate TCP

10, 60: gate drive IC 12, 62: data TCP

14, 64: data drive IC 16, 66: data PCB

18, 88: FPC 20, 80: main PCB

22, 82: timing control unit 24, 84: power supply unit

26, 86: LOG signal line group 18, 78: gate PCB

100: backlight unit 102: bottom cover

106: screw

In order to achieve the above object, the LOG liquid crystal display device according to the present invention comprises a liquid crystal display module having a liquid crystal cell matrix; First tape carrier packages mounted with a data driving circuit for driving data lines of the liquid crystal cell matrix and connected to the liquid crystal display module; Second tape carrier packages mounted to the liquid crystal display module by mounting a gate driving circuit to drive the gate lines of the liquid crystal cell matrix; A first printed circuit board configured to supply first driving signals to be supplied to the data driving circuit and second driving signals to be supplied to the gate driving circuit to the first tape carrier package; A second printed circuit board supplying the second drive signals to the second tape carrier package; A line-on-glass type signal line group formed in the liquid crystal display module to supply second driving signals from the first printed circuit board to the second printed circuit board; And a conductive bottom cover that is connected in parallel with at least one signal line of the line-on-glass type signal line group through the first and second printed circuit boards while protecting the liquid crystal display module. .

The line-on-glass type signal line group receives the second driving signals supplied from the first printed circuit board via any one of the first tape carrier packages and receives any one of the second tape carrier packages. The second printed circuit board is supplied via the second printed circuit board.

The bottom cover is connected in parallel with a ground line for supplying a ground voltage among the line-on-glass type signal line group via the first and second printed circuit boards.

And a screw for electrically connecting the ground signal lines formed on the first and second printed circuit boards to the bottom cover.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 13.

FIG. 8 is a plan view schematically illustrating a LOG type liquid crystal display according to an exemplary embodiment of the present invention. In the LOG type liquid crystal display shown in FIG. 8, the FPC between the data PCB 66 and the gate PCB 78 is removed. Has a structure.

The LOG type liquid crystal display shown in FIG. 8 includes a main PCB 80 including a timing controller 82 and a power supply 84, and a data PCB 66 connected to the main PCB 80 through an FPC 88. And a data TCP 62 mounted between the data PCB 66 and the liquid crystal display panel 56 and a gate driver IC 60 mounted on the liquid crystal display panel 56. A connected gate TCP 58 and a gate PCB 78 connected to the gate TCP 58 are provided.

The liquid crystal display panel 56 is formed by bonding the thin film transistor array substrate 52 and the color filter array substrate 54 with the liquid crystal interposed therebetween. The liquid crystal display panel 56 is provided with liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL. The liquid crystal cell implements gradation by adjusting the light transmittance according to the supplied pixel signal.

The data drive ICs 64 are connected to the data lines DL via the data TCP 62 and the data pad portion of the liquid crystal display panel 56. The data drive ICs 64 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 64 may receive data control signals, pixel data, and power signals from the timing controller 82 and the power supply 84 on the main PCB 80 via the data PCB 66 and the FPC 88. Will be supplied.

The gate drive ICs 60 are connected to the gate lines GL via the gate TCP 58 and the gate pad portion of the liquid crystal display panel 56. The gate drive ICs 60 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 60 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

The gate control signals and the power signals supplied to the gate drive IC 60 are first received from the timing controller 82 and the power supply 84 on the main PCB 80 via the FPC 88 and the data PCB 66. Data is supplied to TCP 62. The gate control signals and the power signals supplied through the first data TCP 62 are transmitted to the first gate TCP 58 via the LOG signal line group 86 formed in the edge region of the thin film transistor array substrate 52. Supplied. Gate control signals and power signals supplied to the first gate TCP 58 are supplied to each of the gate TCPs 58 via the gate PCB 78, and gate control signals supplied to each of the gate TCPs 58. And power signals are supplied to and used by the gate drive IC 60.

The LOG signal line group 86 is normally supplied from the power supply unit 24 such as the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. Power signals; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

In particular, in order to minimize signal distortion caused by the resistance of the LOG type ground line LGND supplying the ground voltage GND among the LOG signal line group 86, the data PCB 66 and the gate PCB 78 are interposed between the data PCB 66 and the gate PCB 78. The conductive path of the ground voltage GND connected in parallel with the LOG type ground line LGND is further formed.

For example, as illustrated in FIG. 9, a ground path connected in parallel with a LOG type ground line LGND using a bottom cover 102 overlapping the data PCB 66 and the gate PCB 78. (TGND).

FIG. 9 is a rear view illustrating a portion of a rear part of a liquid crystal display module according to an exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view of the liquid crystal display module illustrated in FIG. 9 taken along line II ′.

9 and 10, the backlight unit 100 positioned below the liquid crystal panel 56 is mounted on the main supporter 104. The data TCP 62 mounted with the data drive IC 64 and connected to the thin film transistor substrate of the liquid crystal panel 56 surrounds the side portion of the main supporter 104 together with the data PCB 66. It is seated on the back part of). Similarly, the gate TCP 58 mounted with the gate drive IC 60 and connected to the thin film transistor substrate of the liquid crystal panel 56 also surrounds the side portion of the main supporter 104 together with the gate PCB 78. It rests on the back part of 100. In addition, the bottom cover 102 is fastened to cover the side surface of the main supporter 104 while overlapping the rear portion of the data PCB 66, the gate PCB 78, the data TCP 62, and the gate TCP 58. . In general, the bottom cover 102 is formed of a metal material, and thus has conductivity. The bottom cover 102 has a ground line PGND1 formed on the data PCB 66 through a screw 106 as shown in FIG. 10. And a ground line PGND2 formed on the gate PCB 78.

Accordingly, the path of the ground voltage formed between the data PCB 66 and the gate PCB 78 is the ground line PGND1 of the data PCB 66-> first data TCP 62-> LOG type ground line LGN. A first path leading to the ground line PGND2 of the first gate TCP 58-> gate PCB 78; The second path leading to the ground line PGND1 of the data PCB 66-> screw 106-> bottom cover 102-> screw 106-> ground line PGND2 of the gate PCB 78 is parallel It consists of.

The parallel configuration of the ground paths reduces the resistance of the ground lines below about 1Ω. Therefore, the resistance of the gate current path of the power signal (gate high voltage VGH, gate low voltage VGL, common voltage VCOM, etc.) including the ground path is reduced. As a result, as shown in FIG. 11, the gate low voltage VGL1, which was unstable in the past with a large swing width, is supplied to the gate low voltage VGL2 stabilized according to the decrease in the current path resistance in the liquid crystal display according to the present invention. It becomes possible.

The bottom cover 102 is connected in parallel via at least one signal line of the LOG signal line group 86 and the screw 106, the data PCB 66, and the gate PCB 78. Even in this case, since the resistance of the gate current path decreases, the common voltage VCOM and the gate low voltage VGL can be stabilized.

As described above, the LOG type liquid crystal display according to the present invention can reduce the resistance of the gate current path by connecting one of the LOG signal line groups for supplying the gate driving signals and the conductive bottom cover in parallel. For example, the LOG type liquid crystal display according to the present invention can reduce the resistance of the gate current path by connecting the LOG type ground line and the bottom cover in parallel.

Accordingly, in the LOG type liquid crystal display according to the present invention, the resistance of the gate current path is reduced to stabilize the common voltage and the gate low voltage, thereby minimizing the greenish and horizontal crosstalk due to the unstable common voltage and the gate low voltage. Will be.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A liquid crystal display module having a liquid crystal cell matrix; First tape carrier packages mounted with a data driving circuit for driving data lines of the liquid crystal cell matrix and connected to the liquid crystal display module; Second tape carrier packages mounted to the liquid crystal display module by mounting a gate driving circuit to drive the gate lines of the liquid crystal cell matrix; A first printed circuit board configured to supply first driving signals to be supplied to the data driving circuit and second driving signals to be supplied to the gate driving circuit to the first tape carrier package; A second printed circuit board supplying the second drive signals to the second tape carrier package; A line-on-glass type signal line group formed in the liquid crystal display module to supply second driving signals from the first printed circuit board to the second printed circuit board; And a conductive bottom cover connected in parallel with at least one signal line of the line-on-glass type signal line group through the first and second printed circuit boards while protecting the liquid crystal display module. The method of claim 1, The line-on-glass type signal line group Supplying the second driving signals supplied from the first printed circuit board via any one of the first tape carrier packages to the second printed circuit board via any one of the second tape carrier packages. A liquid crystal display device, characterized in that. The method of claim 1, The bottom cover is And a parallel connection with a ground line for supplying a ground voltage among the line-on-glass type signal line group via the first and second printed circuit boards. The method of claim 3, wherein And a screw electrically connecting the ground signal lines formed on the first and second printed circuit boards to the bottom cover.