KR20040062751A - Liquid crystal display and thin film transistor panel - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) and a TFT(Thin Film Transistor) panel are provided to improve side visibility by differently setting charge rates of two sub-pixels. CONSTITUTION: Sub-pixels(P1(i,j),P2(i,j)) are connected to a gate line(G1) and data lines(Dj-1,Dj). The sub-pixels(P1(i,j),P2(i,j)) have control terminals connected to the gate line(G1). The sub-pixels(P1(i,j),P2(i,j)) include the first and second switching elements(Q1,Q2) and the first and second liquid crystal capacitors(CCL1,CCL2) connected in series to the data lines(Dj-1,Dj). The first liquid crystal capacitor(CCL1) is connected to the first switching element(Q1), and the second liquid crystal capacitor(CCL2) is connected to the second switching element(Q2).

Description

Liquid Crystal Display and Thin Film Transistor Display {LIQUID CRYSTAL DISPLAY AND THIN FILM TRANSISTOR PANEL}

The present invention relates to a liquid crystal display device having a subpixel and a thin film transistor array panel.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. A voltage is applied to both electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage.

Among these liquid crystal displays, TN (twisted nematic) liquid crystal displays have various advantages, but they have limitations in extending their range to monitors or TVs due to viewing angle problems. For this reason, in order to improve the viewing angle of the TN liquid crystal display, a series of achievements have been shown through many studies such as the development of a multi-domain method or the development of a new compensation film.

In particular, in the case of a multi-domain liquid crystal display device, the gamma curve on the front side and the gamma curve on the side surface do not coincide with each other, thus showing inferior visibility on the left and right sides as compared with a conventional TN liquid crystal display device. For example, in the case of PVA (patterned vertically aligned) method, which cuts out by domain dividing means, the screen is brighter and the color tends to move toward the white side toward the side, and in severe cases, there is no difference in luminance between high grays. It also occurs when the image looks clumped.

The technical problem to be achieved by the present invention is to implement a liquid crystal display device having excellent visibility by improving the image quality of the liquid crystal display device.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are equivalent circuit diagrams of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

4, 5A, and 5B are cross-sectional views of the liquid crystal panel assembly of FIG. 3 taken along lines IVa-IVa ', Va-Va', and Vb-Vb ', respectively.

6, 9, 12, and 15 are layout views illustrating a thin film transistor array panel at an intermediate stage in a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

7, 8A, and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 6 taken along the lines VII-VII ', VIIIa-VIIIa', and VIIIb-VIIIb ', respectively.

10, 11A, and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 9 taken along lines X-X ', XIa-XIa', and XIb-XIb ', respectively.

13, 14A, and 14B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 13 taken along lines XIII-XIII ', XIVa-XIVa', and XIVb-XIVb ', respectively.

16, 17A, and 17B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 15 taken along lines XVI-XVI ', XVIIa-XVIIa', and XVIIb-XVIIb ', respectively.

18 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 19 illustrates two subpixels of the liquid crystal display shown in FIG. , Is a graph showing the pixel voltage as a function of time.

20 is a graph of a gamma curve in a conventional liquid crystal display and a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display device according to the present invention for achieving the object of the present invention is

A first signal line and a second signal line, and

A pixel connected to the first signal line and the second signal line

Including;

The pixel includes first and second switching elements and first and second liquid crystal capacitors having control terminals connected to the first signal line and connected in series to the second signal line.

Preferably, the first liquid crystal capacitor is connected to the first switching element, and the second liquid crystal capacitor is connected to the second switching element.

The pixel may further include a third switching element connected to the first signal line and the second signal line.

In addition, the first liquid crystal capacitor is preferably connected to the second switching element and the second liquid crystal capacitor is connected to the third capacitor.

In addition, the pixel may further include first and second storage capacitors connected in parallel with the first and second liquid crystal capacitors, respectively.

The liquid crystal display device according to the present invention

A first signal line and a second signal line, and

A pixel connected to the first signal line and the second signal line

Including;

The pixel includes first and second subpixels each including at least one transistor connected to the first signal line and the second signal line, and a liquid crystal capacitor connected to the transistor.

The filling rate of the first subpixel is different from that of the second subpixel.

In the present invention, it is preferable that the aspect ratios of the transistors of the first subpixel and the second subpixel are different from each other.

In addition, the transistor is a MOS transistor, the parasitic capacitance between the gate and the drain of the transistor of the first sub-pixel and the second sub-pixel is preferably different.

The first and second subpixels may further include sustain capacitors connected in parallel with the liquid crystal capacitors, respectively, and kickback voltages of the first and second subpixels are the same.

The thin film transistor substrate according to the present invention

Insulation board,

A gate line and a data line formed on the substrate and insulated from each other;

A first thin film transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode separated from the first source electrode;

A second thin film transistor including a second gate electrode connected to the gate line, a second source electrode connected to the first drain electrode, and a second drain electrode separated from the second source electrode;

A first pixel electrode connected to the first drain electrode,

A second pixel electrode connected to the second drain electrode

It includes.

Here, the first and second pixel electrodes preferably have cutouts, and any one of the first and second pixel electrodes has a first portion and a second portion respectively positioned above and below the other. It is preferable to include.

In this case, the boundary between the first and second portions and the second pixel electrode and the cutout portion may not be parallel to or perpendicular to the gate line and the data line.

In addition, the thin film transistor substrate according to the present invention may further include a storage electrode overlapping the first and second pixel electrodes through an insulator.

In this case, it is preferable that the sustain electrode overlaps the cutout or the boundary between the first pixel electrode and the second pixel electrode.

The gate line may overlap the first and second pixel electrodes through an insulator.

In addition, the thin film transistor substrate according to the present invention

Insulation board,

A gate line and a data line formed on the substrate and insulated from each other;

A first thin film transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode separated from the first source electrode;

A second thin film transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode separated from the second source electrode;

A third thin film transistor including a third gate electrode connected to the gate line, a third source electrode connected to the second drain electrode, and a third drain electrode separated from the third source electrode;

A first pixel electrode connected to the first drain electrode,

A second pixel electrode connected to the third drain electrode

It includes.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A to 2C are equivalent circuit diagrams of a liquid crystal panel assembly in a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention is connected to a liquid crystal panel assembly 300 and a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 and a signal controller 600 for controlling the gray voltage generator 800 are included.

Referring to FIGS. 1 and 2A, the liquid crystal panel assembly 300 is connected to a plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and SL in an equivalent circuit, and is in a substantially matrix form. It includes a plurality of pixels arranged.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

The display signal lines G ₁ -G _n , D ₁ -D _m , SL also include a plurality of sustain electrode lines SL to which a predetermined voltage such as a common voltage is applied. Each storage electrode line SL is positioned between the gate lines G ₁ -G _n and substantially extends in the row direction, and is substantially parallel to each other. This storage electrode line SL may be omitted.

One pixel is defined by one gate line G ₁ -G _n and one data line D ₁ -D _m , for example, (i, j) (i = 1, 2, ..., n, j = 1, 2, ..., m) means a pixel connected to the i-th gate line G _i and the j-th data line D _j .

As shown in Figs. 2A to 2C, each pixel ( ) Are the two subpixels ( , ), And each subpixel ( , ) Includes at least one switching element (Q ₁ , Q ₂ , Q ₃ ), liquid crystal capacitors (C _LC1 , C _LC2 ) and storage capacitors (C _ST1 , C _ST2 ) connected thereto. do. As shown, the switching elements Q ₁ , Q ₂ and Q ₃ are three-terminal elements having a control terminal, an input terminal and an output terminal. The storage capacitors C _ST1 and C _ST2 can be omitted as necessary, and the storage electrode line SL is also unnecessary in that case.

Each liquid crystal capacitor C _LC1, C _LC2 is between the switching elements Q ₁ , Q ₂ , Q ₃ and the common voltage V _com , while the storage capacitors C _ST1, C _ST2 are switching elements Q ₁ , Q. ₂ , Q ₃ ) and the storage electrode line SL. When the storage electrode line SL is not present, the storage capacitors C _{ST1 and} C _ST2 may be connected to adjacent gate lines G _{1 to} G _n .

The control terminals of the switching elements Q ₁ , Q ₂ , Q ₃ are commonly connected to the corresponding gate lines G ₁ -G _n , and the output terminals are the corresponding liquid crystal capacitors C _LC1, C _LC2 and the storage capacitor C _ST1, C _ST2 ).

In FIG. 2A, each subpixel ( , ) Includes one switching element Q ₁ , Q ₂ . Subpixel Switching element Q ₁ and subpixel The switching element Q _{2 of} ) is connected in series to the data lines D ₁ -D _m . That is, the input terminal of the switching device (Q ₁₎ is coupled to the data lines (D ₁ -D _m), the switching input terminals of the element (Q ₂₎ is connected to the output terminal of the switching device (Q ₁₎ . Therefore, two subpixels ( , One of the subpixels ( ) Is directly connected to the corresponding data line (D _j ) and the other subpixel ( ) Is the subpixel ( The data signal from the data line D _j is supplied through the switching element Q ₁ .

In FIG. 2B, one subpixel ( ) Includes one switching element Q ₁ , but the other subpixel ( ) Includes two switching elements Q ₂ , Q ₃ . Subpixel The input terminal of the switching element Q ₁ of) is connected to the corresponding data line D ₁ -D _m , and the subpixel ( The two switching elements Q ₂ and Q ₃ are connected in series to the data lines D ₁ -D _m . Therefore, two subpixels ( , One of the subpixels ( ) Is connected to the corresponding data line D _j through one switching element Q ₁ , but the other subpixel ( ) Receives a data signal from the data line D _j through two switching elements Q ₂ and Q ₃ .

In FIG. 2C, each subpixel ( , ) Includes one switching element Q ₁ , Q ₂ . Input terminals of the respective switching elements Q ₁ and Q ₂ are connected to the corresponding data lines D ₁ -D _m .

Next, a detailed structure of the liquid crystal panel assembly 300 of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to the drawings.

3 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of the liquid crystal panel assembly illustrated in FIG. 3 taken along line IVa-IVa '. 5A is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line Va-Va ', and FIG. 5B is a cross-sectional view of the liquid crystal panel assembly of FIG. 3 taken along the line Vb-Vb'.

As shown in FIG. 3, the liquid crystal panel assembly 300 according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 therebetween.

First, the lower panel 100, that is, the thin film transistor array panel will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending mainly in the horizontal direction are formed on the transparent insulating substrate 110 such as glass.

Each gate line 121 mainly extends in a row direction, and a plurality of portions thereof extend up and down to form gate electrodes 124a and 124b of the thin film transistor.

The storage electrode line 131 is applied with a given voltage such as the common voltage V _com , and includes a plurality of sets of storage electrodes 133-136 and a connection part 137. Each pair of sustain electrodes 133-136 includes a pair of column direction sustain electrodes 133, 134, one row direction sustain electrode 135, and a plurality of diagonal direction sustain electrodes 136. The column direction sustain electrodes 133 and 134 extend from the sustain electrode line 131 in the column direction and face each other. The row direction sustain electrode 135 extends in the horizontal direction at one end of the column direction sustain electrode 133. The diagonal sustain electrode 136 extends diagonally from the column sustain electrode 133, and part of the diagonal sustain electrode 136 is also connected to the main body of the sustain electrode line 131 or the row sustain electrode 135. The connection part 137 connects neighboring column direction sustain electrodes 133 and 134. The branching points of the column sustain electrodes 133 and the row direction sustain electrodes 135 are wider than other portions.

The gate line 121 and the storage electrode line 131 are made of a metal or a conductor such as Al, Al alloy, Ag, Ag alloy, Mo, Mo alloy, Cr, Ti, Ta, or the like.

As shown in Figs. 5A and 5B, the gate line 121 and the sustain electrode line 131 of the present embodiment are formed of a single layer, but have a low specific resistance to metal layers such as Cr, Mo, Ti, and Ta, which are excellent in physicochemical properties. It may be made of a double layer including a metal layer of the series or Ag series. Side surfaces of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle with respect to the horizontal plane is preferably 30 ° to 80 °.

A gate insulating layer 140 made of silicon nitride (SiN _X ) is formed on the gate line 121 and the storage electrode line 131.

A plurality of semiconductor layers 151 and 152 made of hydrogenated amorphous silicon are formed on the gate insulating layer 140. Each set of semiconductors 151 and 152 includes one linear semiconductor 151 and a plurality of island-like semiconductors 152 extending mainly in the column direction. Each branch extending from the linear semiconductor 151 and each island-like semiconductor 152 form a pair to overlap the gate electrodes 124a and 124b to form a channel portion of the thin film transistor.

On the semiconductors 151 and 152, a plurality of linear and island resistive contact members 161, 163a, 163b, 165a, and 165b made of amorphous silicon doped with a high concentration of N-type impurities such as silicide or phosphorus are formed.

Side surfaces of the semiconductors 151 and 152 and the ohmic contacts 161, 163a, 163b, 165a, and 165b have a tapered structure and have an inclination angle in a range of 30 ° to 80 °.

A plurality of data lines 171 and a plurality of pairs of drain electrodes 175a and 175b are formed on the contact members 161, 163a, 163b, 165a, and 165b.

Each data line 171 mainly extends in the column direction along the linear semiconductor 151 and its branches extend over the ohmic contact member 163a to form a plurality of source electrodes 173a for the thin film transistor. The drain electrode 175a is located on the island-like ohmic contact 163b and also on the other island-like ohmic contact 165a, serving as a source electrode 173b of another transistor, and extending upwardly. The drain electrode 175b extends across the row direction sustain electrode 135.

Like the gate line 121, the data line 171 and the drain electrodes 175a and 175b are made of a material such as Cr and Al, and may be formed of a single layer or multiple layers, and the side of the data line 171 and the drain electrodes 175a and 175b may have a 30 ° to 80 ° It may have an inclination angle.

Here, the ohmic contacts 161, 163a, 163b, 165a, and 165b are disposed only at portions where the semiconductors 151, 152, the data lines 171, and the drain electrodes 175a, 175b overlap each other, thereby providing contact resistance therebetween. Lowers.

According to another embodiment of the present invention, the data line 171 and the drain electrodes 175a and 175b may have substantially the same planar shape as the ohmic contacts 161, 163a, 163b, 165a and 165b and the semiconductor 151. , 152 may have substantially the same planar shape except for the channel portion of the thin film transistor.

According to another embodiment of the present invention, the linear semiconductor 151 is island-shaped only in the branch including the channel portion, and the linear portion extending along the data line 171 is omitted. In this case, the semiconductor 151 may be present at a portion that intersects the gate line 121 and the data line 171 to effectively insulate them.

A passivation layer 180 made of an inorganic insulator such as silicon nitride or an organic insulator such as resin is formed on the data line 171, the drain electrodes 175a and 175b, and the channel portion of the semiconductors 151 and 152. The passivation layer 180 has a plurality of contact holes 183a and 183b exposing portions of the drain electrodes 175a and 175b, and contact holes 184 and 185 exposing branch points of the sustain electrodes 133 and 136, respectively. The passivation layer 180 also has a contact hole 182 exposing a part of the data line 171, and has a contact hole 181 exposing a part of the gate line 121 together with the gate insulating layer 140. .

A plurality of pairs of pixel electrodes 190a and 190b, a plurality of gate contact assistants 91, a plurality of data contact assistants 92, and a plurality of connection members 95 are formed on the passivation layer 180. The pixel electrodes 190a and 190b, the contact auxiliary members 91 and 92, and the connection member 95 are made of a transparent conductive material or a reflective conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Each pair of pixel electrodes 190a and 190b is connected to the corresponding drain electrodes 175a and 175b through corresponding contact holes 183a and 183b, respectively. One 190a of each pair of pixel electrodes 190a and 190b is located near the center (hereinafter referred to as a "central pixel electrode") and the other 190b is located above and below the center pixel electrode 190a (hereinafter referred to as "a central pixel electrode"). "Top and bottom pixel electrodes").

The center pixel electrode 190a is an isosceles trapezoidal, and is substantially parallel to the row direction cutouts 81 and 82 and the hypotenuses which are dug in the row direction at the centers of the top and bottom sides, respectively, and symmetrically with respect to the row direction cutouts 81 and 82. An oblique incision 83 arranged. The diagonal cutout 83 is connected to the row cutout 81.

The upper and lower pixel electrodes 190b are vertically symmetrical with respect to the center pixel electrode 190a, and are substantially rectangular with the center pixel electrode 190a. The upper and lower pixel electrodes 190b have a constant distance 85 from the center pixel electrode 190a and have a constant parallel edge with the upper and hypotenuse sides of the central pixel electrode 190a. The upper and lower pixel electrodes 190b include an upper half portion 190b1 positioned above the center pixel electrode 190a, a lower half portion 190b2 positioned below, and an elongated connection portion 196 extending in the vertical direction. The upper half 190b1 and the lower half 190b2 each have one cutout parallel to the hypotenuse of the central pixel electrode 190a, and they are arranged symmetrically.

The pixel electrodes 190a and 190b overlap with the storage electrode line 131 to form a storage capacitor.

The gate contact assisting member 91 and the data contact assisting member 92 are connected to the gate line 121 and the data line 171 through contact holes 181 and 182, respectively. The contact assistants 91 and 92 are not essential to protect exposed portions of the gate line 121 and the data line 171 and to increase physical and electrical contact with external devices.

The connecting member 95 connects the upper and lower sustain electrode lines 131 across the gate line 121 through the contact holes 184 and 185.

The alignment layer 11 is formed on the entire surface of the thin film transistor array panel 100 except for the vicinity of the contact auxiliary members 91 and 92.

Next, the color filter display panel will be described with reference to FIGS. 3 and 4.

The black matrix 220 is formed on a transparent insulating substrate 210 such as glass, and the black matrix 220 has an opening located in a region corresponding to the pixel electrodes 190a and 190b. Green and blue color filters 230 are formed. On the color filter 230, a common electrode 270 made of a transparent conductive material such as ITO or IZO is formed over the entire surface of the display panel 200. The common voltage is applied to the common electrode 270.

The common electrode 270 includes a plurality of cutouts, and each bee includes a plurality of central cutouts 271, a plurality of diagonal cutouts 272, and a plurality of most magnetic cutouts 273. In each bee, the central cutout 271 extends substantially in the row direction and is positioned between the row cutouts 81 and 82 of the pixel electrodes 190a and 190b. The diagonal cutout 272 is located between the diagonal cutouts 83 and 84 of the pixel electrodes 190a and 190b and the gap 85 between the two pixel electrodes 190a and 190b, with a distance between them. same. The edge cutout 273 is parallel to the gate line 121 or the data line 171, meets an obtuse angle with the diagonal cutout 272 of the common electrode 270, and obliquely meets the pixel electrodes 190a and 190b. The incision 84 meets at an acute angle. The edge cutout 273 overlaps and covers the sustain electrode line 131 main body, the row direction and column direction sustain electrodes 133-135, and is disposed between the diagonal cutouts 83 and 84 and the pixel electrodes 190a and 190b. The gap 85 of the gap overlaps with the diagonal sustain electrode 136 to prevent light leakage. However, some of the diagonal cutouts 272 of the common electrode 270 may not be covered by the sustain electrode.

An alignment layer 21 is formed on the entire surface of the common electrode 270.

Polarizers 12 and 22 are attached to the outer sides of the two substrates 110 and 210, respectively. At this time, the polarization axes of these polarizing plates 12 and 22 are arranged to be substantially parallel to the gate line 121 or the data line 171 and orthogonal to each other.

The liquid crystal molecules of the liquid crystal layer 3 may be homogeneous alignment or homeotropic alignment or vertical alignment, but it is preferable in terms of the viewing angle.

At least one of the cutouts 81-84 and 271-273 illustrated in FIGS. 3 to 5B may be replaced with protrusions formed separately on the passivation layer 180.

The liquid crystal panel assembly 300 illustrated in FIGS. 3 to 5b is a specific embodiment of the liquid crystal panel assembly illustrated in FIG. 2a, and the liquid crystal capacitor C _LC of FIG. 2a is the pixel electrode 190 of the lower panel 100. And the common electrode 270 of the upper panel 200 as two terminals, and the liquid crystal layer 3 between the two electrodes 190 and 270 functions as a dielectric. FIG. 2A shows a MOS transistor as an example of the switching elements Q _{1 and} Q ₂ , which have the gate electrodes 124a and 124b, the source electrodes 173a and 173b and the drain electrode as described above. A thin film transistor having three terminals 175a and 175b and having an amorphous silicon layer as a channel layer is implemented.

Unlike in FIGS. 3 to 5B, the common electrode 270 may be provided on the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

In the liquid crystal display, the liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode 190 and the common electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIG. 3 to FIG. 5B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 to 17B and 3 to 5B.

6, 9, 12, and 15 are layout views illustrating a thin film transistor array panel at an intermediate stage in a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention. 7, 8A, and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 6 taken along the lines VII-VII ', VIIIa-VIIIa', and VIIIb-VIIIb ', respectively. FIG. 11B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 9 taken along a line XX ', XIa-XIa', and XIb-XIb ', respectively, and FIGS. 13, 14A, and 14B are shown in FIG. A cross-sectional view of the thin film transistor array panel taken along the XIII-XIII 'line, the XIVa-XIVa' line, and the XIVb-XIVb 'line, respectively, and FIGS. 16, 17A, and 17B illustrate XVI of the thin film transistor array panel shown in FIG. 15, respectively. Sectional drawing cut along the -XVI 'line, the XVIIa-XVIIa' line, and the XVIIb-XVIIb 'line.

First, as illustrated in FIGS. 6 to 8B, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 by a photolithography process.

Next, the gate insulating layer 140, the amorphous silicon layer, and the doped amorphous silicon layer are sequentially stacked, and the above two layers, that is, the doped amorphous silicon layer and the amorphous silicon layer are sequentially patterned in one photo process, and FIGS. 9 to 9. As shown in FIG. 11B, a plurality of linear and islands doped amorphous silicon layers and a plurality of linear and island semiconductors 151 and 152 are formed.

Subsequently, as shown in Figs. 12 to 14B, after forming the plurality of data lines 171 and the plurality of drain electrodes 175a and 175b by a photographic process, the exposed doped amorphous silicon layer portions are removed to remove the plurality of linear lines. And island-like resistive contact members 161, 163a, 163b, 165a, and 165b.

After the passivation layer 180 is laminated, the passivation layer 180 and the gate insulating layer 140 are patterned in one photo process, and the plurality of contact holes 181, 182, 183a, and 183b are illustrated in FIGS. 15 to 17B. 184, 185).

Finally, as shown in FIGS. 3 to 5B, the plurality of pixel electrodes 190a and 190b, the plurality of gate contact assistants 91, and the plurality of data contact assistants 92 are formed on the passivation layer 180 by a photographic process. After the plurality of connection members 95 are formed, the alignment layer 11 is formed on the entire surface of the thin film transistor array panel 100.

According to another embodiment of the present invention, the steps of FIGS. 9 to 11B and the steps of FIGS. 12 to 14B may be formed by one photolithography process. In this case, a photoresist pattern having a different thickness is used according to a position, for example, the thickest at the portion where the data line 171 and the drain electrodes 175a and 175b are to be formed, and the thinnest at the portion where the gate insulating layer 140 is exposed. There is no thickness, and a photoresist pattern having an intermediate thickness may be used at a portion where the semiconductors 151 and 152 are to be formed. The photomask for forming the photoresist layer pattern preferably includes a blocking region where most of the light is blocked, a transmission region where most of the light is transmitted, and a semi-transmissive region where only part of the light is transmitted. The semi-transmissive region has a plurality of slit patterns or lattice patterns or includes a transflective film.

The data line 171 and the drain electrodes 175a and 175b thus formed have substantially the same planar shape as the ohmic contacts 161, 163a, 163b, 165a and 165b, and the semiconductors 151 and 152 are formed of the thin film transistor. Except for the channel portion, they have substantially the same planar shape.

FIG. 18 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment, which is a specific embodiment of FIG. 2B but differs from FIG. 2B in that it is a shear gate method.

A plurality of gate lines 121 extending mainly in the horizontal direction are formed on the transparent insulating substrate 110 such as glass.

Each gate line 121 mainly extends in a row direction, and the plurality of portions thereof extend up and down to form gate electrodes 124a, 124b1, and 124b2 of the thin film transistor. Each gate line 121 also includes a plurality of sets of branch electrodes 122, 123, 125, and 126, which are branches, and a connection portion 127. Each set of branch electrodes 122, 123, 125, 126 includes a pair of columnar branch electrodes 122, 123 and two row branch electrodes 135, 136. The branch electrodes 122 and 123 extend in the column direction from the gate line 121 and face each other. The row branch electrodes 125 extend in the horizontal direction at one end of the column branch branches 122, and the row branch electrodes 126 connect the centers of the two column branch electrodes 122 and 123 in the horizontal direction. do. The connection part 127 connects adjacent columnar branch electrodes 122 and 123.

The gate insulating layer 140 is formed on the gate line 121.

A plurality of sets of semiconductors 151 and 152 are formed on the gate insulating layer 140, and each set of semiconductors 151 and 152 includes one linear semiconductor 151 and a plurality of island-type semiconductors 152 extending mainly in a column direction. It includes. Each pair of branches extending from the linear semiconductor 151 and each island-like semiconductor 152 form a pair to overlap the gate electrodes 124a, 124b1, and 124b2 to form a channel portion of the thin film transistor.

A plurality of linear and island resistive contact members (not shown) are formed on the semiconductors 151 and 152.

A plurality of data lines 171 and a plurality of drain electrode drain electrodes 175a, 175b1, and 175b2 are formed on the contact member.

Each data line 171 mainly extends in the column direction along the linear semiconductor 151, and its branches extend to form a plurality of source electrodes 173a for the thin film transistor. The drain electrode 175a extends vertically, and the drain electrode 175b1 is positioned on the linear semiconductor 151 and on the island-type semiconductor 152 to serve as a source electrode of another transistor. The drain electrode 175b2 extends across the row direction branch electrode 125.

Here, the ohmic contacts 161, 163a, 163b, 165a, and 165b are disposed only at portions where the semiconductors 151, 152, the data lines 171, and the drain electrodes 175a, 175b overlap each other, thereby providing contact resistance therebetween. Lowers.

The passivation layer 180 is formed on the data line 171, the drain electrodes 175a, 175b1, and 175b2, and the channel portion of the semiconductors 151 and 152. The passivation layer 180 has a plurality of contact holes 183a and 183b exposing portions of the drain electrodes 175a and 175b2, respectively. The passivation layer 180 also has a contact hole 182 exposing a part of the data line 171, and has a contact hole 181 exposing a part of the gate line 121 together with the gate insulating layer 140. .

A plurality of pairs of pixel electrodes 190a and 190b, a plurality of gate contact assistants 91, and a plurality of data contact assistants 92 are formed on the passivation layer 180.

The pair of pixel electrodes 190a and 190b are sequentially arranged in the column direction, and are connected to the corresponding drain electrodes 175a and 175b2 through corresponding contact holes 183a and 183b, respectively.

Each pixel electrode 190a, 190b overlaps the gate line 121 and the branch electrodes 122, 123, 125, and 126 of the front end to form a storage capacitor, and the branch electrode 126 is between the two pixel electrodes 190a and 190b. Is positioned at to cover the light leakage between the two pixel electrodes (190a, 190b).

The gate contact assisting member 91 and the data contact assisting member 92 are connected to the gate line 121 and the data line 171 through contact holes 181 and 182, respectively.

According to another exemplary embodiment of the present invention, in the thin film transistor array panel illustrated in FIG. 18, the pixel electrodes 190a and 190b have a shape as shown in FIG. 3.

According to another exemplary embodiment of the present invention, the thin film transistor array panel illustrated in FIG. 18 may have the sustain electrode line 131 as shown in FIG. 3, and the shape of the gate line 121 may also be as shown in FIG. 3.

1 again, the liquid crystal display according to the exemplary embodiment of the present invention will be described.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display.

The gate driver 400 may also be referred to as a scan driver. The gate driver 400 may be connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to provide a gate-on voltage V _on from the driving voltage generator 700. And a gate signal composed of a combination of the gate off voltage V _off are applied to the gate lines G ₁ -G _n .

The data driver 500, also referred to as a source driver, is connected to the data lines D ₁ -D _m of the assembly 300 to select a gray voltage from the gray voltage generator 800 to select data as a data signal. Applies to lines D ₁ -D _m .

The signal controller 600 generates a control signal for controlling operations of the gate driver 400, the data driver 500, the driving voltage generator 700, and the like, so that each gate driver 400, the data driver 500, and The driving voltage generator 700 is supplied.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display and applies them to the data driver 500.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching elements Q ₁ , Q ₂ connected to.

While a gate-on voltage V _on is applied to one gate line G ₁ -G _n , and a row of switching elements Q ₁ and Q ₂ connected thereto is turned on (this period is referred to as "1H" or " 1 horizontal period "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 400 assigns each data voltage to the corresponding data. Supply to line (D ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the liquid crystal capacitors C _LC1 and C _LC2 of each subpixel of the corresponding pixel through the turned-on switching elements Q ₁ and Q ₂ .

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

However, in the example of FIG. 2A, the data voltage is a subpixel ( ) Is passed through only one transistor Q ₁ , and the subpixel ( ) Is passed through two transistors (Q ₁ , Q ₂ ), so that two subpixels ( , The charging rate of the liquid crystal capacitors C _LC1 and C _LC2 of the C1 is different. Specifically, two subpixels ( , By varying the aspect ratio of transistors Q ₁ and Q ₂ or the magnitude of parasitic capacitance present between the control terminals and switching terminals (source / drain) of switching elements Q ₁ and Q ₂ . Subpixel , ) Can be different voltage charging rate. Given enough charge time, both subpixels ( , ) Is charged almost the same voltage, but not because the reaction rate of the liquid crystal is slow, the charging speed of the liquid crystal capacitor (C _LC1 , C _LC2 ) is also slow. For example, when the aspect ratio of the transistor Q ₁ is greater than the aspect ratio of the transistor Q ₂ , the subpixel ( ) Is charged to a subpixel ( ) Is greater than the voltage charged in

Also in the example of FIG. 2B, the data voltage is sub-pixel ( ) Is passed through only one transistor Q ₁ , and the subpixel ( ) Is passed through two transistors Q ₂ and Q ₃ . As a result, the two subpixels ( , ), And the voltage charged in is different.

In the case of FIG. 2C, the data voltage is a subpixel ( ) Is passed through the transistor Q ₁ , and the subpixel ( ) Is transferred via transistor Q ₂ . If the aspect ratios of the two transistors Q ₁ and Q ₂ are different, the two subpixels ( , ), And the voltage charged in is different.

In addition, according to another embodiment of the present invention, two subpixels ( , Two sub-pixels (C) by _varying the capacitance of the liquid crystal capacitors C _LC1 and C _LC2 or the capacitances of the holding capacitors C _ST1 and C _ST2 . , ), The voltage charged to The liquid crystal capacitors C _LC1 and C _LC2 have different capacities. , It may be considered that the area of the pixel electrodes 190a and 190b of the () is different, and the area ratio is about 10: 1 to 1:10.

Like this, one pixel is divided into two subpixels ( , ) And divide it into two subpixels ( , Differentiating the voltage charged in the) improves the visibility on the side. This will be described in detail later with reference to FIGS. 19 and 20.

However, briefly described above, but, for example, in the case of Figure 2a, the switching elements (Q _1, Q _2), there is a parasitic capacitor (Cgs1, Cgd1, Cgd2) between the control terminal and the input-output terminal (source / drain) of the. The kickback voltage due to the parasitic capacitances Cgs1, Cgd1, and Cgd2 acts to lower the charging voltage of each liquid crystal capacitor C _LC1 , C _LC2 . That is, the charging voltage of each of the liquid crystal capacitors C _LC1 and C _LC2 , that is, the pixel voltage is a value obtained by subtracting the kickback voltage from the data voltage (assuming that the common voltage is 0 for convenience).

However, in the case of inverting driving alternately applying positive and negative data voltages, the kickback voltage always acts in a direction of lowering the voltage. Therefore, if the common voltage is not properly corrected, the pixel voltage and the negative voltage of the positive voltage are the same The pixel voltage at the time becomes asymmetrical. Specifically, two subpixels ( , Different kickback voltages may cause the voltage to reverse. For example, the subpixel ( ) Kickback voltage Is significantly greater than the kickback voltage of If the pixel voltage of the pixel is positive, the subpixel ( Smaller than) but larger when negative.

Therefore, in the embodiment of the present invention, the parasitic capacitances Cgs1, Cgd1, and Cgd2, the liquid crystal capacitors C _LC1 and C _LC2 , and the holding capacitors C _ST1 and C _ST2 are adjusted to have the same kickback voltage. For example, the parasitic capacitances Cgd1 and Cgd2 of the two transistors Q ₁ and Q ₂ have the same size, and the two holding capacitors C _ST1 and C _ST2 and the liquid crystal capacitors C _LC1 and C _{The case of making LC2} ) the same also is mentioned.

FIG. 19 illustrates two subpixels of the liquid crystal display shown in FIG. , Is a graph showing the pixel voltage as a function of time.

19 shows that the aspect ratio W / L of the transistor Q ₁ , that is, the value obtained by dividing the channel width W by the channel length L is 20 / 4.5 and the W / L of the transistor Q2 is 15. /4.5, and the two subpixels ( , The storage capacitances C _ST1 and C _ST2 are 0.3pF, the liquid crystal capacitors C _CL1 and C _CL2 are 0.1pF, and the gate-source parasitic capacitance Cgs1 of transistor Q ₁ is 7.83fF, two. The gate-drain parasitic capacitances Cgd1 and Cgd2 of the transistors Q ₁ and Q ₂ are 13.67 fF, and the applied data voltages are measured at 0 V and 10 V, respectively.

As can be seen in FIG. 19, two subpixels ( , There is no reversal phenomenon in the pixel voltage.

20 is a graph of a gamma curve (transmission as a function of gray scale) in a conventional liquid crystal display without a subpixel and a liquid crystal display according to an embodiment of the present invention, viewed from the front and at a side of 60 ° Each is shown for viewing.

The liquid crystal display device used for the measurement used the biaxial compensation film as a liquid crystal display device which averaged four domains of the R-ECB type to 1: 1: 1: 1.

The maximum voltage applied to the conventional liquid crystal display device used for the measurement is 4.9V, and the maximum voltage applied to the liquid crystal display device of this embodiment is 5.9V. Two sub-pixels of the liquid crystal display of this embodiment ( , ) Is 85% and 75% respectively compared to the conventional liquid crystal display, and the two subpixels ( , Area of the pixel electrodes 190a and 190b is the same.

In FIG. 20, the front gamma curve of the conventional liquid crystal display and the front gamma curve of the present embodiment are set to be the same. As can be seen in Figure 20, it can be seen that the side gamma curve of the present embodiment is closer to the front gamma curve than the conventional side gamma curve, which means that the side visibility is improved.

As described above, in the pixel composed of two subpixels, the side visibility is improved by changing the filling rates of the two subpixels.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (18)

A first signal line and a second signal line, and A pixel connected to the first signal line and the second signal line Including; The pixel includes first and second switching elements and first and second liquid crystal capacitors having control terminals connected to the first signal line and connected in series to the second signal line. Liquid crystal display. In claim 1, And the first liquid crystal capacitor is connected to the first switching element, and the second liquid crystal capacitor is connected to the second switching element. In claim 1, The pixel further includes a third switching element connected to the first signal line and the second signal line. In claim 3, And the first liquid crystal capacitor is connected to the second switching element and the second liquid crystal capacitor is connected to the third capacitor. The method according to any one of claims 1 to 4, The pixel further includes first and second storage capacitors connected in parallel with the first and second liquid crystal capacitors, respectively. A first signal line and a second signal line, and A pixel connected to the first signal line and the second signal line Including; The pixel includes first and second subpixels each including at least one transistor connected to the first signal line and the second signal line, and a liquid crystal capacitor connected to the transistor. The filling rate of the first subpixel and the filling rate of the second subpixel are different from each other. Liquid crystal display. In claim 6, The aspect ratio of the transistors of the first subpixel and the second subpixel are different from each other. In claim 6, The transistor is a MOS transistor, and the parasitic capacitance between the gate and the drain of the transistor of the first subpixel and the second subpixel is different. The method according to any one of claims 6 to 8, The first and second subpixels each further include a storage capacitor connected in parallel with the liquid crystal capacitor. In claim 9, The kickback voltages of the first and second subpixels are the same. Insulation board, A gate line and a data line formed on the substrate and insulated from each other; A first thin film transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode separated from the first source electrode; A second thin film transistor including a second gate electrode connected to the gate line, a second source electrode connected to the first drain electrode, and a second drain electrode separated from the second source electrode; A first pixel electrode connected to the first drain electrode, A second pixel electrode connected to the second drain electrode Thin film transistor substrate comprising a. In claim 11, The thin film transistor substrate of which the first and second pixel electrodes each have a cutout. In claim 12, One of the first and second pixel electrodes includes a first portion and a second portion respectively positioned above and below the other one of the first and second pixel electrodes. In claim 13, A boundary between the first and second portions and the second pixel electrode and the cutout portion are neither parallel nor perpendicular to the gate line and the data line. The method according to any one of claims 11 to 14, The thin film transistor substrate further comprising a storage electrode overlapping the first and second pixel electrodes via an insulator. The method of claim 15, The sustain electrode overlaps the cutout or a boundary between the first pixel electrode and the second pixel electrode. The method according to any one of claims 11 to 14, The gate line overlaps the first and second pixel electrodes through an insulator. Insulation board, A gate line and a data line formed on the substrate and insulated from each other; A first thin film transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode separated from the first source electrode; A second thin film transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode separated from the second source electrode; A third thin film transistor including a third gate electrode connected to the gate line, a third source electrode connected to the second drain electrode, and a third drain electrode separated from the third source electrode; A first pixel electrode connected to the first drain electrode, A second pixel electrode connected to the third drain electrode Thin film transistor substrate comprising a.