KR20040060438A - Network synchronous reference clock automatic replacement device - Google Patents

Abstract

PURPOSE: An apparatus for switching automatically a network synchronization reference clock is provided to stabilize a reference clock by switching selectively a reference signal according to states of plural line boards. CONSTITUTION: An apparatus for switching automatically a network synchronization reference clock includes a plurality of line boards and a control board. The line boards(1A-1N) are used for extracting a reference clock signal from a data stream signal of an external network system and detecting and outputting a reference clock error signal therefrom. The control board(4) is used for monitoring the line boards, deciding the detected reference clock error signals, and providing the reference clock signal to control a switching state of the particular line board.

Description

Network synchronous reference clock automatic replacement device

The present invention relates to an automatic switching device of a reference synchronizer of a network system, and in particular, each of the line boards includes a monitoring selection means for detecting / blocking an error of the reference clock signal, and any other line through the control board when an error occurs. The present invention relates to a network reference reference automatic automatic switching device of a network system which selectively switches to a reference signal provided from a board.

In general, the transmission method that transfers traffic between two points is separated by wire transmission by copper cable or coaxial cable, wireless transmission by terrestrial microwave link, satellite transmission by satellite relay, optical transmission by optical fiber, etc. Are classified. The transmission system is composed of a transmission facility and a transmission terminal device, where the transmission medium and the repeater correspond to the transmission facility, and the transmission terminal device and the reception terminal device correspond to the transmission terminal device. In this case, the transmitting station apparatus converts the transmission information into a signal form suitable for a transmission medium when the transmission information is given, and the transmitted signal is received by the receiving terminal apparatus through the multi-stage relay apparatus and restored as the original transmission information. . However, such a transmission system is generally configured in the form of a network in which a plurality of transmission equipments, for example, equipment such as an ATM exchanger and a plurality of subscriber equipments are connected. In addition, between the network equipment of the transmission system as described above, a network synchronizer circuit is usually provided for the network synchronizer of the system.

Then, referring to FIG. 1 of the network synchronizer of the conventional transmission system as described above, a plurality of line boards 70A-N connected to an external network device (not shown) and matching data stream signals transmitted and received, A back board 71 for supplying bias power to the plurality of line boards 70A-N and connecting signals to the corresponding boards; and a reference clock signal provided from any line board via the back board 71. It consists of a network synchronizer board 72 for synchronizing the transmission system.

Each of the line boards 70A-N has a LIU (line interface unit) / framer unit 73A-N for converting a data stream signal input from an external network device into frame data and routing the same to the corresponding board. And a line matching circuit unit 75A-N including a reference clock extraction circuit unit 74A-N for extracting and outputting a reference clock signal from the frame data of the LIU / framer unit 73A-N;

A level converting circuit section 76A-N for converting a TTL level reference clock signal output from the line matching circuit section 75A-N into a PECL (Pseudo Emitter coupled logic) signal and outputting the level converting circuit section 76A-N. And a line control circuit section 78A-N including a clock drive section 77A-N for outputting the reference clock signal of the PECL level converted by the < RTI ID = 0.0 >) < / RTI > do.

Here, the manipulator board 72 may include any one of a plurality of line boards 70A-N.

A reference clock selector 79 selects an input reference clock signal.

Meanwhile, referring to the operation of the network synchronizer device of the conventional transmission system as described above, the LIU / framer unit 73A of the line matching circuit unit 75A of the line board 70A previously designated to provide a reference clock signal for the network synchronizer is Data stream signal input from external network equipment (not shown) is converted into frame data and routed to the board. In this case, the reference clock extracting circuit portion 74A of the line matching circuit portion 75A extracts and restores the reference clock signal from the frame data of the LIU / framer portion 73A, and then the level conversion circuit portion of the line control circuit portion 78A. 76A). The level converting circuit section 76A converts the TTL level reference clock signal output from the reference clock extracting circuit section 74A of the line matching circuit section 75A into a PECL signal and outputs it to the clock driver 77A. Then, the clock drive unit 77A of the line control circuit unit 78A receives the reference clock signal of the PECL level converted by the level converting circuit unit 76A via the back board 71 and the reference of the master synchronizer board 72. Output to clock selector 79.

Accordingly, the reference clock selector 79 of the manipulator board 72 determines the final reference clock signal among the reference clock signals input via the back board 71. Then, the network synchronizer board 71 adjusts the network synchronizer of the transmission system based on the final reference clock signal determined by the reference clock selector 79.

However, the network synchronizer of the conventional transmission system as described above is limited to a specific line board during system setting because the line board for extracting the reference clock signal from the external network equipment is fixed to the specific line board during operation of the transmission system. In case of abnormality, the system clock signal could not be supplied stably. Also, in order to replace a specific line board that has failed, the operator has to replace the board. There was a problem.

Therefore, the present invention has been invented to solve the conventional problems as described above, even if a problem occurs in a specific line board for supplying a reference clock automatically switch to another normal line board to continue the system with a stable reference clock signal Therefore, the object of the present invention is to provide an automatic switching device for the reference clock of the network system, which significantly improves the system clock stability of the network board.

Another object of the present invention is to supply a stable reference clock signal to the manipulator board, which is not limited to a specific slot or board for supplying the reference clock, so that the network system can be stably operated, thereby significantly improving the operation reliability of the network system. It is to provide an automatic switching device of the reference clock of the system.

The present invention for achieving the above object is a network system having a network board using a reference clock of the external network equipment, in addition to extracting the reference clock signal from the data stream signal of the external network equipment and the reference clock error signal A plurality of line boards for detecting and outputting a plurality of line boards, and a control board for continuously monitoring each of the plurality of line boards and determining whether a specific reference board error signal is detected to control whether a specific line board is transferred. It provides an automatic network reference clock switching device of the network system.

1 is an explanatory diagram illustrating a network synchronizer of a conventional network system.

2 is an explanatory diagram illustrating a network synchronizer reference clock automatic switching device of the network system of the present invention.

<Detailed Description of Codes>

1A-N: Line Board 2: Back Board

3: Manipulator board 4: Control board

5A-N: LIU / Framer section 6A-N: Reference clock extraction circuit section

7A-N: Line matching circuit section 8A-N: Supervisory circuit section

9A-N: level conversion circuit section 10A-N: clock drive section

11A-N: Line control circuit section 12: Alarm analysis / clock selection circuit section

13: reference clock selector

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The apparatus of the present invention is connected to an external network device (not shown) as shown in FIG. 2 to match data stream signals transmitted and received, extract a reference clock signal from the data stream signal, and detect and output a reference clock error signal. A plurality of line boards 1A-N, a back board 2 for supplying bias power to the plurality of line boards 1A-N, and connecting signals to a corresponding board as necessary, and via the back board 2 By using a reference clock signal provided from an arbitrary line board to continuously monitor each of the plurality of line boards 1A-N and the detected reference clock error. It is composed of a control board (4) for controlling the switching of the specific line board to provide a reference clock by determining the signal.

Each of the line boards 1A-N has a LIU (line interface unit) / framer unit 5A-N for converting a data stream signal input from an external network device into frame data and routing the same to the corresponding board. And a line matching circuit section 7A-N including a reference clock extraction circuit section 6A-N for extracting and outputting a reference clock signal from the frame data of the LIU / framer section 5A-N;

A supervisory circuit unit 8A-N for detecting an error occurrence of a reference clock signal output from the line matching circuit unit 7A-N and outputting it to the control board 4 through the back board 2; and the supervisory circuit unit 8A. A level converting circuit section 9A-N for converting the TTL level reference clock signal output from -N) into a PECL (Pseudo Emitter coupled logic) signal and outputting the PECL converted by the level converting circuit section 9A-N. Outputs the reference clock signal of the level to the manipulator board 3 via the back board 2, and determines whether to output the reference clock signal according to whether or not the reference clock output control signal (enable) of the control board 4 is received. Each of the line control circuit units 11A-N including the clock drive units 10A-N is included.

Here, the control board 4 monitors the reference clock error signal detected from the monitoring circuit section 8A-N of each line board 1A-N, and analyzes an alarm for selecting a specific line board to be switched according to the result. And a clock select circuit section 12. In addition, the network synchronizer board 3 is provided with a reference clock selector 13 for selecting a reference clock signal input to any one of the plurality of line boards 1A-N.

Next, the operation and effects of the present invention having the above configuration will be described.

When the system is first set up, the apparatus of the present invention controls the control board 4 to provide a reference clock signal by selecting any one of the plurality of line boards 1A-N according to a set procedure. When (4) selects the line board 1A, the alarm analysis / clock selection circuit unit 12 of the control board 4 transmits an enable signal through the back board 2 to control the line of the line board 1A. Only the clock drive section 10A of the circuit section 11A is applied, and all of the clock drive sections 10B-N of the line control circuit section 11B-N of the remaining line boards 1B-N are disabled.

Therefore, only the selected line board 1A provides the reference clock signal to the manipulator board 3, and the remaining line boards 1B-N execute only the set function but do not provide the reference clock signal.

Meanwhile, the LIU / framer unit 5A of the line matching circuit unit 7A of the selected line board 1A converts a data stream signal input from an external network device (not shown) into frame data and routes it to the corresponding board. At this time, the reference clock extraction circuit portion 6A of the line matching circuit portion 7A extracts and restores the reference clock signal from the frame data of the LIU / framer portion 5A, and then monitors the circuit portion 8A of the line control circuit portion 11A. ) The monitoring circuit section 8A detects an error of the reference clock signal input from the line matching circuit section 7A and outputs it to the level conversion circuit section 9A. The level conversion circuit section 9A converts the reference clock signal of the TTL level output from the reference clock extraction circuit section 6A of the line matching circuit section 7A into a PECL signal and outputs it to the clock driver 10A. Then, the clock drive unit 10A of the line control circuit unit 11A is already receiving the reference clock output control signal (enable) of the control board 4, so that the level of the PECL level converted by the level converting circuit unit 9A is changed. The reference clock signal is output to the reference clock selector 13 of the network synchronizer board 3 via the back board 2.

Accordingly, the reference clock selector 13 of the manipulator board 3 determines the final reference clock signal among the reference clock signals input via the back board 2. Then, the synchronizer board 3 adjusts the synchronizer of the transmission system based on the final reference clock signal determined by the reference clock selector 13.

Here, the supervisory circuit section 8B-N of the remaining line boards 1B-N including the line board 1A selected during the above process is taken from the reference clock extraction circuit section 6A-N of the line matching circuit section 7A-N. The controller continuously monitors whether there is an error in the output reference clock and then outputs the result signal to the alarm analysis / clock selection circuit unit 12 of the control board 4 through the back board 2.

At this time, if the current enable signal is applied to the clock drive unit 10A and an error occurs in the reference clock signal of the line board 1A providing the reference clock, the monitoring circuit unit 8A detects this. By outputting through the back board 2 to the alarm analysis / clock selection circuit unit 12 of the control board (4). Then, the alarm analysis / clock selection circuit unit 12 of the control board 4 analyzes it and immediately transfers it to another normal line board 1N to continue supplying the reference clock to the network synchronizer board 3.

That is, when an error occurs in the line board 1A, the alarm analysis / clock selection circuit unit 12 of the control board 4 is disabled by the clock drive unit 10A of the line board 1A. Is applied to block the reference clock supply, while an enable signal is applied to another normal line board 1N, for example, the clock drive unit 10N of the line board 1N, through the switched line board 1N. The reference clock signal continues to be supplied to the synchronizer board 3.

As described above, the present invention includes a monitoring selection means for detecting / blocking an error of the reference clock signal on each of the line boards, and in the event of an error, the present invention selectively switches to a reference signal provided from any other line board through the control board. Therefore, even if an error occurs in a specific line board supplying the reference clock, it automatically switches to another normal line board and continues to operate the system with a stable reference clock signal, thereby significantly improving the system clock stability of the synchronizer board. Have.

In addition, according to the present invention, the network system is stably operated by supplying a stable reference clock signal to the manipulator board without being limited to a specific slot or board for supplying the reference clock, thereby significantly improving the operation reliability of the network system. It also works.

Claims (3)

In a network system having a network synchronizer board using a reference clock of external network equipment, A plurality of line boards extracting a reference clock signal from the data stream signal of the external network device and detecting and outputting a reference clock error signal, and continuously monitoring each of the plurality of line boards and detecting the reference clock error signal. Automated reference clock automatic switching device of the network system, characterized in that it comprises a control board for controlling whether or not the transfer of a particular line board to provide a reference clock. The apparatus of claim 1, wherein each of the line boards includes a monitoring circuit unit for detecting whether an error occurs in the reference clock signal and outputting the error to the control board through a white board, and a reference clock signal having a TTL level output from the monitoring circuit unit as a PECL signal. A level converting circuit unit for converting and outputting a reference clock signal of the PECL level converted by the level converting circuit unit to a network synchronizer board via a back board, and receiving a reference clock output control signal of a control board according to whether a reference clock signal is received; And a line control circuit unit including a clock drive unit to determine whether the output of the network system. 2. The control board of claim 1, wherein the control board includes an alarm analysis / clock selection circuit section for monitoring a reference clock error signal detected from the monitoring / selection circuit section of each line board and selecting a specific line board to be switched according to the result. Automated reference clock automatic switching device of the network system, characterized in that.