KR20040060290A - Gate Electrode of Semi- conductor Device and Method for Gate Electrode of Fabricating Semiconductor Device - Google Patents
Gate Electrode of Semi- conductor Device and Method for Gate Electrode of Fabricating Semiconductor Device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000002243 precursor Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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Abstract
Description
본 발명은 반도체 소자 제조방법에 관한것으로, 보다 상세하게는 고집적 고속 로직 소자 및 메모리 소자의 1 G DRAM 또는 4 G DRAM 이상의 초고집적 소자의 게이트 전극 제조방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate electrode of a highly integrated high-speed logic device and a memory device of 1 G DRAM or 4 G DRAM or more.
반도체소자에서 양산중인 DRAM 및 로직의 게이트 전극 유전막으로는 실리콘 절연막이 사용되고 있다. 디자인 룰이 감소함에 따라 절연막의 두께는 터널링 한계가 되는 25 - 30 옹스트롱 이하로 줄어드는 추세에 있으며, 0.1 ㎛ 테크롤로지의 게이트 유전막으로 DRAM의 경우 30 -35 옹스트롱의 두께가, 로직 소자의 경우 13 - 15 옹스트롱 정도의 두께가 예상된다. 그러나 현재까지 사용되고 있는 폴리실리콘 게이트 전극을 계속 사용하는 경우 폴리실리콘의 공핍현상에 의하여 전기적으로 증가되는 게이트 유전막의 두께 성분이 3 - 8 옹스트롱 정도까지 되어 15 - 30 옹스트롱 정도까지로 유효 게이트 절연막 두께를 감소시키는데 큰 걸림돌이 되고 있다.Silicon insulating films are used as gate electrode dielectric films of DRAM and logic in mass production in semiconductor devices. As the design rule decreases, the thickness of the insulating film is decreasing to 25-30 angstroms or less, which is the tunneling limit. The gate dielectric film of 0.1 탆 technology is used. A thickness of about 13-15 Angstroms is expected. However, when the polysilicon gate electrode used up to now is used, the thickness of the gate dielectric film electrically increased by the depletion of polysilicon is about 3-8 angstroms, and the effective gate insulating film is about 15-30 angstroms. It is a big obstacle to reducing the thickness.
따라서 최근 이를 극복하기 위한 노력의 일환으로 하이-k 유전 재료를 게이트 절연막으로 채용하는 연구가 진행되고 있으며, 한편으로는 지금까지 연구되어 오던 폴리 실리콘 게이트 대신에 메탈 게이트를 적용함으로써 폴리 게이트 공핍을 최소화하는 방향으로 연구가 진행되고 있다.Therefore, as part of efforts to overcome this problem, researches on adopting high-k dielectric materials as gate insulating films have recently been conducted. Meanwhile, poly gate depletion is minimized by applying metal gates instead of poly silicon gates, which have been studied so far. Research is underway in the direction.
뿐만아니라 P+ 폴리 게이트의 경우 보론 침투와 같은 문제, 또한 메탈 게이트를 사용함으로서 막을 수 있어 최근 많은 연구가 집중되고 있는 분야이기도 하다.In addition, the P + poly gate can be prevented by the use of metal gates, such as boron penetration, and is a field in which a lot of research has recently been concentrated.
메탈 게이트 전극의 경우 많은 연구가 TiN 또는 WN을 중심으로 진행되어 왔으나, 일함수(Work function) 값이 4.75 - 4.85 eV 정도인 관계로 미드갭(midgap) 일함수에서 발렌스 밴드 쪽으로 가깝게 일함수를 형성하게 된다.In the case of metal gate electrodes, many studies have been conducted around TiN or WN, but since the work function is about 4.75-4.85 eV, the work function is formed close to the balance band in the midgap work function. Done.
표면 채널 PMOSFET를 위한 경우 상기의 일함수는 어느정도 적합한 수준이라고 할수 있으나, nMOSFET의 경우 채널 도핑을 2 - 5 *1017/㎝을 정도로 할때 문턱전압 값이 거의 0.8 - 1.2 V 정도가 됨을 의미한다.For the surface channel PMOSFET, the above work function is somewhat suitable, but for the nMOSFET, when the channel doping is about 2-5 * 1017 / cm, it means that the threshold voltage value is almost 0.8-1.2V.
즉, 이러한 경우 저 전압 또는 저 전력의 특성을 갖는 하이 퍼포먼스 소자에서 요구되는 문턱전압 (0.3 - 0.6) 타켓을 만족시킬 수 가 없게 된다. 따라서, nMOS와 pMOS에서 동시에 0.3 - 0.6 V 정도의 낮은 문턱전압 값을 얻기 위해서는 nMOS의 경우 일함수 값이 4.2 eV, pMOS의 경우 일함수 값이 약 4.8 - 5.1 eV 정도의 값을 가지는 이중 금속전극을 사용하는 것이 바람직하다.That is, in this case, the threshold voltage (0.3-0.6) target required by the high performance device having the characteristics of low voltage or low power cannot be satisfied. Therefore, in order to obtain a low threshold voltage of 0.3-0.6 V in both nMOS and pMOS, a double metal electrode having a work function of 4.2 eV for nMOS and a work function of about 4.8-5.1 eV for pMOS Preference is given to using.
이러한, 이중 금속 전극에서 요구되는 특성으로서 일함수가 nMOS용과 pMOS용으로 가능한 동종의 물질을 적용하는 것이 에칭 단계나 공정의 단순화 측면에서 유리하다고 볼 수 있으나, 동종의 물질로서 구성성분이나 박막의 배향성의 조절로 일함수가 0.7 - 1.0 eV이상으로 차이가 나는 경우는 현재까지 극히 더문 실정이다. 따라서, 일함수가 다름 이종의 물질을 이중 금속 전극에 적용하고자 하는 방법을 고려해 볼 수 있는데 전혀 다른 이종의 금속 전극을 nMOS 및 pMOS 전극에 적용하고자 할 경우에는 무엇보다도 게이트 적층의 높이가 달라지고 전극을 구성하는 물질이 달라져서 전극을 에칭하는데 어려움이 있을 수 있다. 결론적으로 이종 합금 전극 자체에 포함하고 있는 금속의 성분비(농도)를 조절함으로써 nMOS, pMOS 전극을 형성한다면 보다 이상적인 이중 금속 전극이 되리라 사료된다.It is advantageous to apply the same kind of material whose work function is possible for nMOS and pMOS as characteristics required for the double metal electrode in terms of the simplification of the etching step or the process. If the work function differs by more than 0.7-1.0 eV, the current situation is extremely slow. Therefore, the work function may be considered to apply heterogeneous materials to the double metal electrode. When the heterogeneous metal electrode is applied to the nMOS and pMOS electrodes, the height of the gate stack is changed and the electrode is different. It may be difficult to etch the electrode because the material constituting the different. In conclusion, if the nMOS and pMOS electrodes are formed by controlling the component ratio (concentration) of the metals contained in the dissimilar alloy electrode itself, it would be more ideal double metal electrode.
본 발명은 상기한 문제점을 개선하기 위하여 nMOS에서는 낮은 일함수의 값을 가지는 Ti-rich Ru1-xTix를 pMOS에서는 높은 일함수 값을 가지는 Ru-rich Ru1-xTix를 금속 게이트 전극에 적용하여 제조하는 방법 및 그 방법을 이용하여 제조된 게이트 전극을 제공하는데 그 목적이 있다.The present invention provides a method of manufacturing Ti-rich Ru1-xTix having a low work function in nMOS and Ru-rich Ru1-xTix having a high work function in pMOS by applying a metal gate electrode to solve the above problems. And a gate electrode fabricated using the method.
Ru 자체는 헥사고날 물질로서 CVD 또는 PVD 방법으로 성장시켜 주로 캐패시터 하부 전극으로 적용하기 위해서 주로 연구되어 온 물질이다. Ru는 그 일함수가 5.0eV 이상으로 pMOS의 게이트 전극으로 적용하기에 용이한 물질로 알려져 있다. 이런 높른 일함수를 가지고 있는 Ru에 상대적으로 매우 낮은 일함수 (~ 4.1 eV)를 가지고 있는 Ti의 농도를 높임으로써 전체적인 합금의 일함수를 낮추어 궁긍적으로 nMOS 전극 물질에 Ti-rich Ru1-xTix 를 적용하려는데 있다. Ti 대신에 일함수가 낮은 Ta를 이용하여 Ru-rich Ru1-xTax 은 pMOS 전극으로 Ta-rich Ru1-xTax를 nMOS 전극으로 이용하는 것도 좋은 대안이다.Ru itself is a hexagonal material that has been studied mainly for growth by CVD or PVD and mainly applied as a capacitor lower electrode. Ru has a work function of 5.0 eV or more and is known to be easy to apply as a gate electrode of a pMOS. By increasing the concentration of Ti with a very low work function (~ 4.1 eV) relative to Ru with this high work function, the overall work function of the alloy is lowered and ultimately Ti-rich Ru1-xTix is applied to the nMOS electrode material. It is intended to apply. Using Ta, which has a low work function, instead of Ti, Ru-rich Ru1-xTax is a pMOS electrode, and Ta-rich Ru1-xTax is an nMOS electrode.
도1는 본 발명에 의해 제조된 반도체 소자를 도시한 단면도.1 is a cross-sectional view showing a semiconductor device manufactured by the present invention.
도2a 내지 도2g는 본 발명의 실시예에 의해 일반적인 게이트 구조에 이중 금속 게이트를 제조하는 방법을 도시한 단면도.2A-2G are cross-sectional views illustrating a method of fabricating a double metal gate in a general gate structure in accordance with an embodiment of the present invention.
도3a 내지 도3f는 본 발명의 실시예에 의해 다마신 게이트 구조의 이중 금속 게이트를 제조하는 방법을 도시한 단면도.3A to 3F are cross-sectional views illustrating a method of manufacturing a double metal gate having a damascene gate structure according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>
100 : 반도체 기판 110 : p-well100 semiconductor substrate 110 p-well
120 : n-well 130 : 소자분리막120: n-well 130: device isolation film
11 : 게이트 절연막 12 : Ti-rich Ru1-xTix 막11 gate insulating film 12 Ti-rich Ru1-xTix film
13 : Ru-rich Ru1-xTix 막 14 : 확산 방지막13: Ru-rich Ru1-xTix film 14: diffusion barrier film
15 : 금속막 17 : 측벽 절연막15 metal film 17 sidewall insulating film
18 : 소오스, 드레인 영역18: source, drain region
상기한 목적을 달성하기 위하여 반도체 소자에 있어서, nMOS와 pMOS 지역의 기판 상에 형성된 게이트 절연막과, 상기 nMOS 지역의 게이트 절연막 상에 형성된 Ti-rich Ru1-xTix막과, 상기 pMOS 지역의 게이트 절연막 상에 형성된 Ru-rich Ru1-xTix막과, 상기 Ti-rich Ru1-xTix막과, 상기 Ru-rich Ru1-xTix막 상에 각각 형성된 확산방지막과, 상기 확산 방지막 상에 형성된 저항이 낮은 금속막으로 이루어지는 게이트 전극을 특징으로 한다..In order to achieve the above object, in a semiconductor device, a gate insulating film formed on a substrate of nMOS and pMOS regions, a Ti-rich Ru1-xTix film formed on a gate insulating film of the nMOS region, and a gate insulating film of the pMOS region A Ru-rich Ru1-xTix film formed on the film, the Ti-rich Ru1-xTix film, a diffusion barrier film formed on the Ru-rich Ru1-xTix film, and a metal film having a low resistance formed on the diffusion barrier film, respectively. It features a gate electrode.
상기 nMOS 지역의 일함수 값이 4.0 - 4.4 eV 이고, 상기 pMOS 지역의 일함수 값이 4.7-5.2 eV 이다.The work function value of the nMOS region is 4.0-4.4 eV, and the work function value of the pMOS region is 4.7-5.2 eV.
상기 Ti-rich Ru1-xTix막의 x는 0.51 - 1.0 이고, 상기 Ru-rich Ru1-xTix막의 x는 00.00 - 0.50 이다.The x of the Ti-rich Ru1-xTix film is 0.51-1.0, and the x of the Ru-rich Ru1-xTix film is 00.00-0.50.
상기 Ti-rich Ru1-xTix막의 Ti 대신에 탄탈륨을 사용하고, 상기 Ru-rich Ru1-xTix막에서 Ru 대신에 Pt를 사용하는 것도 가능하다.Tantalum may be used instead of Ti of the Ti-rich Ru1-xTix film, and Pt may be used instead of Ru in the Ru-rich Ru1-xTix film.
상기한 목적을 달성하기 위한 본 발명은 반도체소자의 제조방법에 있어서,In the present invention for achieving the above object in the method of manufacturing a semiconductor device,
반nMOS와 pMOS 지역의 기판 상에 게이트 절연막을 형성하는 단계와,Forming a gate insulating film on the substrate in the anti-nMOS and pMOS regions,
상기 nMOS 지역에 Ti-rich Ru1-xTix막을 형성하는 단계와,Forming a Ti-rich Ru1-xTix film in the nMOS region;
상기 pMOS 지역에는 Ru-rich Ru1-xTix막을 형성하는 단계와,Forming a Ru-rich Ru1-xTix film in the pMOS region;
그 상부에 확산방지막을 형성하는 단계와,Forming a diffusion barrier thereon;
상기 확산방지막 상부에 저항이 낮은 금속막을 형성하는 단계를 포함하는 게이트 전극 형성하는 것을 특징으로 한다.Forming a gate electrode comprising the step of forming a metal film with a low resistance on the diffusion barrier.
상기 Ru-rich Ru1-xTix막을 형성할 때 Ru1-xTix 타켓의 스퍼터링시 질소의 양을 5-100 sccm 으로 흘리고, Ar양은 5 - 50 sccm, RF 파우어는 025 - 15 KW를 사용한다.When forming the Ru-rich Ru1-xTix film, the amount of nitrogen is flowed at 5-100 sccm during sputtering of the Ru1-xTix target, the amount of Ar is 5-50 sccm, and the RF power is 025-15 KW.
상기Ti-rich Ru1-xTix막과 Ru-rich Ru1-xTix막을 형성할 때 단원자 증착법(Atomic Layer Deposion)을 이용한다.When forming the Ti-rich Ru1-xTix film and Ru-rich Ru1-xTix film, an atomic layer deposition method is used.
상기 단원자 증착법에서 Ru 전구체는 Ru(EtCp)2, Ru(od)3 중 하나를 사용하고, 50-650℃의 온도 범위, 0.05 - 5 torr 기압에서 증착한다.In the monoatomic deposition method, Ru precursor is deposited using one of Ru (EtCp) 2 and Ru (od) 3, and is deposited at a temperature range of 50-650 ° C. and a pressure of 0.05-5 torr.
상기 단원자 증착법에서 Ti 전구체는 TiCl4, TDMAT, TDEAT 중 하나를 사용한다.In the monoatomic deposition method, the Ti precursor uses one of TiCl 4, TDMAT, and TDEAT.
이하 첨부된 도면을 참고하여 본원 발명의 실시예를 설명하기로 한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도1은 본 발명에 의해 제조되는 반도체소자를 도시한 도면으로서, 반도체 기판(100)에 p-well(110)과 n-well(120)이 각각 형성되고, 그 상부에 게이트 전극이 형성된다.1 is a diagram illustrating a semiconductor device manufactured according to the present invention, in which a p-well 110 and an n-well 120 are formed on a semiconductor substrate 100, and a gate electrode is formed thereon.
그리고, 상기 게이트 절연막(11) 상에는 p-well(110)상부에는 Ti-rich Ru1-xTix 막(12) (여기서 x는 0.51 - 1.0)을, 상기 n-well(120) 상부에는 Ru-rich Ru1-xTix 막(13) (여기서 x는 0.00 - 0.50)으로 형성된다.The Ti-rich Ru1-xTix film 12 (where x is 0.51-1.0) is formed on the p-well 110 and the Ru-rich Ru1 is disposed on the n-well 120. -xTix film 13, where x is 0.00-0.50.
또한, 상기 막(12,13) 상부에 확산방지막(14)으로 TiN, TaN 또는 WN으로 형성된다. 그리고, 확산방지막(14) 상부에 저항이 낮은 금속막(15)으로 예를들어 텅스텐이 적층된다. 상기 금속막(15) 상에 하드마스크용 질화막(16)이 형성되고, 이와같이 적층 구조를 갖는 게이트 전극 측벽에 측벽절연막(17)이 형성되고, 게이트 전극양측 하부의 기판에 소오스, 드레인 영역(18)이 형성된다.In addition, the diffusion barrier 14 is formed of TiN, TaN or WN on the films 12 and 13. Then, for example, tungsten is laminated on the diffusion barrier 14 with a low resistance metal film 15. A hard mask nitride film 16 is formed on the metal film 15, and a sidewall insulating film 17 is formed on the sidewalls of the gate electrodes having a stacked structure, and the source and drain regions 18 are formed on the substrates below the gate electrodes. ) Is formed.
상기 nMOS 지역의 일함수 값이 4.0 - 4.4 eV 이고, 상기 pMOS 지역의 일함수 값이 4.7-5.2 eV 디도록 하기위해 상기 Ti-rich Ru1-xTix막의 x는 0.51 - 1.0 이고, 상기 Ru-rich Ru1-xTix막의 x는 00.00 - 0.50 이다.The x-value of the Ti-rich Ru1-xTix film is 0.51-1.0, and the Ru-rich Ru1 so that the work function value of the nMOS region is 4.0-4.4 eV, and the work function value of the pMOS region is 4.7-5.2 eV. The x of the -xTix film is 00.00-0.50.
상기 Ti-rich Ru1-xTix막의 Ti 대신에 탄탈륨을 사용하고, 상기 Ru-rich Ru1-xTix막에서 Ru 대신에 Pt를 사용하는 것도 가능하다.Tantalum may be used instead of Ti of the Ti-rich Ru1-xTix film, and Pt may be used instead of Ru in the Ru-rich Ru1-xTix film.
도2a 내지 도2g 는 일반적인 게이트 구조에 본 발명의 실시예에 의해 이중금속 게이트 구조를 갖는 반도체 소자의 형성방법을 도시한 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a semiconductor device having a double metal gate structure in accordance with an embodiment of the present invention in a general gate structure.
도2a는 p-well(110), n-well(120) 및 소자분리막(130)이 각각 구비된 반도체 기판 상부에 게이트 절연막(11)을 형성한 다음, 그 상부에 Ru-rich Ru1-xTix막(12)을 증착하고, 예정된 n-well(120) 지역을 식각하기 위해 마스크(24)을 형성한 것이다.FIG. 2A shows a gate insulating film 11 formed on a semiconductor substrate having p-well 110, n-well 120, and device isolation layer 130, respectively, and then a Ru-rich Ru1-xTix film formed thereon. (12) is deposited and a mask 24 is formed to etch a predetermined n-well 120 region.
도2b는 노출된 Ru-rich Ru1-xTix막(12)을 식각하고 그 하부의 게이트 절언막(11)을 제거한 것을 도시한다.FIG. 2B shows that the exposed Ru-rich Ru1-xTix film 12 is etched and the gate interfacial film 11 below is removed.
도2c는 상기 마스크(24)를 제거한 다음, 노출된 n-well(12) 상에 다시 게이트 절연막(11)을 형성하고, 전체적으로 Ru-rich Ru1-xTix막(13)을 증착한 것이다.In FIG. 2C, after the mask 24 is removed, the gate insulating film 11 is formed again on the exposed n-well 12, and the Ru-rich Ru1-xTix film 13 is entirely deposited.
도2d는 전체적으로 확산방지막(14)과 저항이 낮은 금속막(15)을 적층한 것이다.FIG. 2D is a laminate of the diffusion barrier 14 and the metal film 15 with low resistance as a whole.
도2e는 상기 금속막(15) 상부에 하드 마스크용 질화막(16)을 형성하고, 그 상부에 게이트 전극용 감광막 패턴(26)을 형성한 것이다.2E shows a hard mask nitride film 16 formed on the metal film 15, and a photoresist film pattern 26 for a gate electrode formed thereon.
도2f는 식각 공정으로 상기 질화막(16)에서 게이트 절연막(11)까지 식각하여 게이트 패턴(30)을 형성한 것이다.FIG. 2F shows a gate pattern 30 formed by etching from the nitride film 16 to the gate insulating film 11 by an etching process.
도2g는 게이트 패턴(30)의 상부에 있는 감광막 패턴(26)을 제거한 다음, 게이트 패턴(30) 측벽에 측벽절연막(17)을 형성한 것이다.2G shows that the photoresist layer pattern 26 on the gate pattern 30 is removed, and then the sidewall insulating layer 17 is formed on the sidewalls of the gate pattern 30.
즉, 상기한 본발명의 실시예에 의하면 게이트 전극 구조에서 게이트 절연막과 확산 방지막 사이에 nMOS 트랜지스터는 Ti-rich Ru1-xTix막을 형성하는 것이고, p MOS 트랜 지스터에는 Ru-rich Ru1-xTix막을 형성하는 것이다.That is, according to the embodiment of the present invention, in the gate electrode structure, the nMOS transistor forms a Ti-rich Ru1-xTix film between the gate insulating film and the diffusion barrier, and the Ru-rich Ru1-xTix film is formed in the p MOS transistor. will be.
상기 Ru-rich Ru1-xTix막을 형성할 때 Ru1-xTix 타켓의 스퍼터링시 질소의 양을 5-100 sccm 으로 흘리고, Ar양은 5 - 50 sccm, RF 파우어는 0.25 - 15 KW를 사용한다.When forming the Ru-rich Ru1-xTix film, the amount of nitrogen is flowed at 5-100 sccm during sputtering of the Ru1-xTix target, and the amount of Ar is 5-50 sccm and the RF power is 0.25-15 KW.
상기Ti-rich Ru1-xTix막과 Ru-rich Ru1-xTix막을 형성할 때 단원자 증착법(Atomic Layer Deposion)을 이용한다.When forming the Ti-rich Ru1-xTix film and Ru-rich Ru1-xTix film, an atomic layer deposition method is used.
상기 단원자 증착법에서 Ru 전구체는 Ru(EtCp)2, Ru(od)3 중 하나를 사용하고, 50-650℃의 온도 범위, 0.05 - 5 torr 기압에서 증착한다.In the monoatomic deposition method, Ru precursor is deposited using one of Ru (EtCp) 2 and Ru (od) 3, and is deposited at a temperature range of 50-650 ° C. and a pressure of 0.05-5 torr.
상기 단원자 증착법에서 Ti 전구체는 TiCl4, TDMAT, TDEAT 중 하나를 사용한다.In the monoatomic deposition method, the Ti precursor uses one of TiCl 4, TDMAT, and TDEAT.
도3a 내지 도3f는 본 발명의 또다른 실시예에 의해 다마신(damascene) 게이트 구조의 이중 금속 게이트를 형성하는 단계를 도시한 것이다.3A through 3F illustrate forming a double metal gate having a damascene gate structure according to another embodiment of the present invention.
도3a는 p-well(110), n-well(120) 및 소자분리막(130)이 각각 구비된 반도체 기판 상부에 더미 게이트 절연막(41)을 형성한 다음, 그 상부에 폴리실리콘층을 증착하고, 게이트 패터닝 공정으로 더미 게이트 전극(42)을 형성한 다음, 더미 게이트 전극(42) 측벽에 측벽절연막(43)을 형성한다. 그리고, 불순물을 이온주입하여 소오스, 드레인 영역을 형성하고, 절연막을 두껍게 증착한 다음, 평탄화공정으로 상기 게이트 전극 상부면에서 평탄하게 된 절연막(44)을 형성한 것이다.FIG. 3A illustrates a dummy gate insulating layer 41 formed on a semiconductor substrate having a p-well 110, an n-well 120, and an isolation layer 130, respectively, followed by depositing a polysilicon layer thereon. After the dummy gate electrode 42 is formed by the gate patterning process, the sidewall insulating layer 43 is formed on the sidewalls of the dummy gate electrode 42. An ion is implanted to form a source and a drain region, a thick insulating film is deposited, and a planarization insulating film 44 is formed on the upper surface of the gate electrode by a planarization process.
도3b는 마스크(45)를 이용하여 p-well(110)상부에 있는 더미 게이트 전극(42)으로 사용된 폴리실리콘을 식각하고, 하부에 있는 더미 게이트 절연막(41)을 제거하고, 다시 게이트 산화막(도시안됨)을 형성한 것을 도시한 것이다.3B etches the polysilicon used as the dummy gate electrode 42 on the p-well 110 using the mask 45, removes the dummy gate insulating film 41 at the bottom, and again the gate oxide film. (Not shown) is shown.
도3c는 상기 더미 게이트 전극이 제거된 부분을 포함한 전영역에 전체적으로 Ti-rich Ru1-xTix막(46)을 형성한 것이다.FIG. 3C shows the Ti-rich Ru1-xTix film 46 formed in the entire region including the portion where the dummy gate electrode is removed.
도3d는 상기 Ti-rich Ru1-xTix막(46) 상부에 전체적으로 텅스텐(47)을 형성하여 더미 게이트 전극이 제거된 부분을 채운다음, CMP 공정으로 평탄작업을 시행하여 상기 n-well(120) 상부에 있는 더미 게이트 전극이 노출되도록 한 것이다.FIG. 3D illustrates that tungsten 47 is formed on the Ti-rich Ru1-xTix layer 46 as a whole to fill the portion where the dummy gate electrode is removed, and then the n-well 120 is flattened by a CMP process. The dummy gate electrode on the upper side is exposed.
도3e는 n-well(120) 상부에 있는 더미 게이트 전극(42)으로 사용된 폴리실리콘과 더미 게이트 절연막(41)을 식각하여 n-well(120)이 노출되도록 한 다음, 얇은 게이트 절연막(도시안됨)을 형성하고 그 상부에 전체적으로 Ru-rich Ru1-xTix막(48)을 증착한 것이다.3E etches the polysilicon and the dummy gate insulating film 41 used as the dummy gate electrode 42 on the n-well 120 so that the n-well 120 is exposed, and then a thin gate insulating film (not shown). No)), and a Ru-rich Ru1-xTix film 48 is deposited on the whole.
도3f는 전체적으로 텅스텐(49)을 형성하여 더미 게이트 전극이 제거된 부분을 채운다음, CMP 공정으로 평탄작업을 시행하여 더미 게이트 전극이 제거된 부분에 채운 것이다.FIG. 3F is a tungsten 49 formed as a whole to fill the portion where the dummy gate electrode is removed, and then a flat operation is performed by the CMP process to fill the portion where the dummy gate electrode is removed.
상기한 본 발명은 반도체 소자 제조시 nMOS 영역에는 Ti-rich Ru1-xTix막을 이용하여 일함수 값을 4.0-4.4 eV로, pMOS에는 Ru-rich Ru1-xTix막을 이용하여 일함수 값을 4.9-5.1 eV로 조절함으로써 nMOS와 pMOS 모두에서 표면 채널 CMOS 소자를 구현해서 문턱전압을 낮출 수 가 있다.In the present invention, the work function is 4.0-4.4 eV using a Ti-rich Ru1-xTix film in the nMOS region and the work function value is 4.9-5.1 eV using a Ru-rich Ru1-xTix film in the pMOS. The threshold voltage can be reduced by implementing surface channel CMOS devices in both nMOS and pMOS.
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