KR20040057133A - Frequency up converter for mobile communication system - Google Patents

Abstract

PURPOSE: A frequency upconverter in a mobile communication system is provided to apply a post clipping method in order to lower the PAR(Peak to Average Ratio) of a baseband signal and to increase the efficiency of an HPA(High Power Amplifier) by filtering and cancelling a distorted spectrum generated when the post clipping method is applied. CONSTITUTION: A baseband signal processing part in a frequency upconverter is comprised of a demultiplexer(100), PSFs(Pulse Shaping Filters)(101,102), clippers(103,104), CUFs(Clean Up Filters)(105,106), a plurality of interpolation filters(107-112), and a modulator. The demultiplexer(100) splits modem output into I/Q signals. The PSFs(101,102) execute band limiting for the split signals respectively. The clippers(103,104) clip signals of more than an appointed level from the filtered signals. The CUFs(Clean Up Filters)(105,106) remove a distorted spectrum component generated by the clipping. The interpolation filters(107-112) interpolate the filtered and omitted signals. The modulator, composed of numerical control oscillators(113,114), multipliers(MUL1,MUL2), and a summer(SUM1), modulates the interpolated signals.

Description

FREQUENCY UP CONVERTER FOR MOBILE COMMUNICATION SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency uplinker in a mobile communication system. In particular, in order to lower the peak to average power ratio (PAR) of a baseband signal in a frequency uplinker of a base station system, a post clipping scheme is applied. The present invention relates to a frequency uplink device of a mobile communication system that filters and removes a distortion spectrum, thereby increasing efficiency of a high power amplifier (HPA).

In general, since a mobile communication system (CDMA) has a high PAR characteristic due to the characteristics of a signal, a power amplifier applied to a base station system should have a much larger peak power capacity than the rated output to ensure linearity. That is, the higher the PAR, the higher the power amplifier (HPA) behind the frequency uplinker should have a specification high enough to cover the peak power (Peak Power).

For example, if a base station system needs to have a power amplifier that can cover more than 10dB of PAR, the power amplifier should be able to cover 200W when the average power is 20W. This increasing problem arises.

Therefore, the PAR of the signal is typically adjusted to lower the specification of the power amplifier. In the conventional case, as shown in FIG. 1, a baseband clipper (BB Clipper) in front of a pulse shaping filter (PSF) is shown. In order to position the signal, a large number of methods have been used to prevent the signal from being output more than a certain level.

1 is a block diagram showing the configuration of a baseband signal processing unit in a conventional frequency uplink device. The demultiplexer 10 which separates the modem output into I, Q signals and a predetermined level or more in each of the separated signals I and Q are shown in FIG. The clipper (11, 12) for clipping the signal, the pulse shaping filter (13, 14) for band-limiting the clipped signal, and the phase characteristics in the corresponding passband of the shaping filtered signal Phase equalizer (15, 16) to satisfy, a plurality of interpolation filters (17 to 22) for interpolating the signal filtered and omitted at the front end and the cosine / sine wave respectively to the interpolated filtered signal A modulator comprising a numerically controlled oscillator (23, 24) and multipliers (MUL1, MUL2) to generate and multiply, and an adder (SUM1) to add to the digital / analog converter by adding the recovered I, Q signal by multiplying the cosine / sine waveIt is configured to hereinafter.

Here, the clippers 11 and 12 positioned at the front end of the pulse shaping filters 13 and 14 are for clipping the baseband signal of a predetermined level or more to lower the PAR in the output signal. The pre clipping method in which 11 and 12 are positioned at the front end of the pulse shaping filters 13 and 14 is a conventional method, and as shown in FIG. 2, there is a problem in the spectrum of the final output. There is no.

However, compared to the post clipping method in which the clippers 11 and 12 are positioned at the rear ends of the pulse shaping filters 13 and 14, the improvement of the PAR is reduced by about 1 dB as shown in FIG. As shown in FIG. 4, an error vector magnitude (EVM) or a code domain characteristic is degraded as compared to the post clipping method.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and in order to lower the instantaneous power-to-average power ratio (PAR) of the baseband signal in the frequency uplink of the base station system, a post clipping scheme is applied and then generated. It is an object of the present invention to provide a frequency upgrader of a mobile communication system that can filter out a distortion spectrum to improve efficiency of a high power amplifier (HPA) at a later stage.

In order to achieve the above object, the present invention provides a demultiplexer for dividing a modem output into I and Q signals, a pulse shaping filter for band-limiting the I and Q signals, and clipping the output signal of the pulse shaping filter to a predetermined level or more. A clipper, a clean up filter (CUF) for removing spectral distortion components caused by the clipping, a plurality of interpolation filters for interpolating an output signal of the cleanup filter, and modulating the interpolated signal. It is characterized by including a modulator.

1 is a block diagram showing the configuration of a baseband signal processor in a conventional frequency uplinker.

2 is a graph for comparing output spectral characteristics by pre clipping and post clipping.

3 is a graph for comparing the degree of improvement of PAR by pre clipping and post clipping.

4 is an exemplary diagram for comparing the degree of noise inclusion by pre clipping and post clipping.

Figure 5 is a block diagram showing the configuration of the baseband signal processing unit of the frequency uplink according to the present invention.

6 is a graph showing the characteristics of the filter combined with the phase equalizer and the cleanup filter function according to the present invention.

FIG. 7 is a block diagram showing a detailed configuration of a cleanup filter in FIG.

8 is a graph for comparing the output spectrum before and after applying the cleanup filter according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: demultiplexer 101,102: pulse shaping filter

103,104: Clipper 105,106: Clean Up Filter

107 ~ 112: Interpolation filter 113,114: Numerically controlled oscillator

MUL1, MUL2,201,204: Multiplier SUM1,202: Adder

203: buffer part

The present invention applies a post clipping method of positioning the clipper at the rear end of the pulse shaping filter, thereby lowering the PAR value as compared with the conventional pre clipping method, and deteriorating the spectrum of the output signal, which is a problem of the post clipping method. In order to solve this problem, a clean up filter (CUF) is provided at the rear end of the clipper to remove distorted spectral components, thereby lowering the PAR as much as possible without degrading the spectrum performance due to clipping. There is a characteristic to make.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described.

5 is a block diagram showing the configuration of the baseband signal processing unit of the frequency uplink according to the present invention. Unlike the conventional baseband signal processing unit, FIG. 5 applies a post clipping method in which a clipper is positioned at a rear end of a pulse shaping filter. There is a difference in configuration having a rear end of the clipper having a cleanup filter for removing the distortion spectrum generated by the phase equalizer and post clipping.

That is, the demultiplexer 100 for separating the modem output into I, Q signals, the pulse shaping filter (PSF) 101 and 102 for band-limiting the separated signals I and Q, and the shaping filtered signal. A clipper 103 and 104 for clipping a signal of a predetermined level or more, a cleanup filter 105 and 106 for removing a distorted spectral component caused by the clipping, and an interpolated signal A plurality of interpolation filters (107 to 112) for interpolation, and a numerically controlled oscillator (113, 114), a multiplier (MUL1, MUL2) and the cosine / sine wave to generate and multiply the cosine / sine wave by the interpolated filtered signal, respectively. And a modulator composed of an adder (SUM1) for multiplying and reconstructing the I and Q signals and outputting them to the digital-to-analog converter.

In this case, the cleanup filters 105 and 106 constitute a phase equalizer at the rear end of the pulse shaping filters 101 and 102 in the case of the CDMA 1X system, and the cleanup filter may also function as the phase equalizer in the cleanup filter. To reduce the PAR. In addition, in the case of the W-CDMA system, only a separate cleanup filter module is additionally configured to remove distortion spectrum components.

6 is a graph showing the characteristics of a clean-up filter (CUF) combined with a phase equalizer (PE) function according to the present invention, (a) is a filter in which a phase equalizer (PE) and a clean-up filter (CUF) function are mixed. (B) shows the performance test result (Phase Magnitude) for the gain and phase, it can be seen that it shows the characteristics of both functions.

7 is a block diagram showing a configuration of a clean-up filter according to the present invention. The multiplier 201 multiplies the input data INPUT and the filter coefficient COEF stored in a separate memory and outputs the multiplier through the multiplier 201. An adder 202 for accumulating the output data and a buffer unit 203 for buffering the data accumulated and output from the adder 202 and then returning the result to the adder 202 to accumulate the next data together. ), And a multiplier 204 for multiplying and outputting the final data accumulated by the adder 202 by a predetermined gain GAIN.

For reference, the maximum number of taps (TAP) of the clean-up filter is defined as a data rate of the input signal and a maximum system clock operating in a field-programmable gate array (FPGA). Since there is no difference, it is possible to simultaneously implement the functions of the phase equalizer PE and the cleanup filter CUF.

As a result of applying the clean-up filter configured as described above to test the frequency upr, the distortion spectral component can be removed as shown in FIG. 8, and the spectrum performance according to clipping while lowering the PAR value as much as possible is shown. Is not degraded.

As described above, in order to reduce the instantaneous power-to-average power ratio (PAR) of the baseband signal, the frequency uplinker of the mobile communication system of the present invention applies a post clipping scheme and applies the distortion spectrum generated at that time. By filtering and removing, there is an effect to increase the efficiency of the high-power amplifier (HPA) of the rear stage.

Claims (2)

A demultiplexer that separates the modem output into I, Q signals, A pulse shaping filter for band-limiting the I and Q signals; A clipper for clipping the output signal of the pulse shaping filter to a predetermined level or more; A clean up filter (CUF) for removing spectral distortion components generated by the clipping; A plurality of interpolation filters for interpolating the output signal of the clean-up filter; And a modulator for modulating the interpolated signal. The multiplier of claim 1, wherein the cleanup filter comprises: a multiplier configured to multiply and output the input data INPUT and the filter coefficient COEF stored in a separate memory; An adder for accumulating data output through the multiplier; A buffer unit for buffering the data accumulated and output from the adder and returning the accumulator to the adder to accumulate the data together with the next data; And a multiplier configured to multiply and output a final gain accumulated by the adder to a predetermined gain (GAIN).