KR20040054935A - Apparatus for repairing in semiconductor memory device - Google Patents

Abstract

PURPOSE: A repair device of a semiconductor memory device is provided to replace a specific timing with a different timing when repairing the semiconductor memory device. CONSTITUTION: A judgement unit(2) determines whether to repair according to a test result of a semiconductor memory device. And a control unit controls an operation timing according to the decision of the judgement unit. The judgement unit includes at least one fuse(1) determining whether to repair, and additionally includes a discrimination unit discriminating the blowing of the fuse.

Description

Repair device in semiconductor memory device {Apparatus for repairing in semiconductor memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair apparatus for a semiconductor memory device, and more particularly, to a repair apparatus for a semiconductor memory device capable of repairing by replacing a specific timing with another timing for a semiconductor memory device in which a fail has occurred.

The repairing method at the package level according to the related art is a rescue method in which a defective cell is replaced with a repair cell by one cell unit by using an anti fuse.

In this manner, one cell fails to fail and two or more cells fail, or a remedy for a column fail or a row fail is impossible.

In recent years, there is a higher possibility that the failure at the package level is a software failure due to a margin for design timing or a lack of margin for the DC level, rather than a hardware failure for one cell.

Since such software failure is more severe in a worst condition, it has been determined to be a semiconductor memory device that cannot be used because it cannot be replaced by a hardware repair, that is, a cell repair by an anti-fuse.

In addition, although the product was produced by designing a high frequency product, a problem arises in that the product is shipped as a low frequency product by a software patch as described above.

In addition, the repair method according to the related art requires that the address information for the cell is input by blowing a fuse in order to relieve a single failed cell. Fuses must be used, and when programming, the fuses may not be blown out completely, or they may be reconnected and blown to operate with resistors with very large resistance values, causing the worst-case replacement of a cell other than the fail cell. .

An object of the present invention for solving the above problems is to repair by using a method of replacing a specific timing with another timing when repairing a semiconductor memory device.

1 is a block diagram illustrating a repair apparatus of a semiconductor memory device according to the present invention.

The repair apparatus of the semiconductor memory device at the package level of the present invention for achieving the above object,

Determination means for determining whether to repair according to a result of a test on the semiconductor memory device; And

And adjusting means for adjusting the operation timing according to the determination of the determining means.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a repair apparatus of a semiconductor memory device according to the present invention.

The repair apparatus includes a fuse unit 1 composed of one fuse, a determination unit 2 for determining whether a fuse is blown, and an operation delay signal SIG according to the output signal FRD of the determination unit 2. (4) or the repair determination unit 3 that selectively transmits to the repair delay unit 5.

At the package level, the fuse unit 1 cuts off when a repair result of a specific timing is required, and outputs a signal RES indicating that repair is necessary.

Here, only one fuse (not shown) may be included in the fuse unit 1. This is because a plurality of fuses are required because the address is decoded in order to repair a failed cell in which a hardware failure has occurred. Because only three fuses are needed.

The determination unit 2 determines whether or not the fuse of the fuse unit 1 is to be repaired according to whether or not the fuse of the fuse unit 1 is blown, and outputs a determination result REP. Therefore, when the REP is enabled as a result of the determination, the operation timing repair is performed.

The repair determination unit 3 selectively transmits the operation timing signal SIG input according to the repair determination result REP to the normal delay unit 4 or the repair delay unit 5.

When the repair determination result indicates that REP is enabled and repair is required, the input operation timing signal SIG is delayed by the repair delay unit 5 to output the repair operation timing signal RSIG, so that a specific timing is adjusted.

On the other hand, when the repair determination result REP is disabled, that is, when the package test result is normal operation, the input operation timing signal SIG is delayed by the normal delay unit 4 and outputs the normal operation timing signal NSIG. Normal operation is performed without adjusting.

Here, the operation timing signal SIG are signals controlled by an internal delay circuit, and particularly, signals that may affect package characteristics. For example, the timing tRAS of the row address strobe signal, the precharge timing tRP of the row address strobe signal / RAS, the delay timing of the column select signal Yi, the delay timing of the sense amplifier enable signal SAEN, and the like.

For example, when a write timing tWR fails, delaying the timing of the sense amplifier enable signal SAEN is greatly improved. However, if the timing of the sense amplifier enable signal SAEN is delayed, there may be a problem in the delay time tRCD characteristic until the row address strobe signal / RAS is enabled and the column address strobe signal / CAS is enabled.

Therefore, the design delays the timing of the sense amplifier enable signal SAEN, performs the manufacturing process, and performs tests in the package state until the row address strobe signal / RAS is enabled and the column address strobe signal / CAS is enabled. If the timing of the sense amplifier enable signal SAEN is set faster by applying the repair apparatus of the present invention to a package having a problem with a delay time tRCD characteristic, the delay of the repair delay unit 5 rather than the normal delay unit 4 is delayed. By setting the time short, it is possible to mass-produce a product having the timing of the optimum sense amplifier enable signal SAEN.

On the other hand, in the case of other operation timing signals, when the delay time is too short, that is, enabled so fast that a failure occurs, if the delay time of the repair delay unit 5 is set longer than the normal delay unit 4, the optimum operation is performed. Mass-produced products can be produced.

Here, the repair apparatus of the present invention may be applied to the operation timing signals, respectively, to optimize the operation timing signals.

Also, after the repair of the operation timing signals, the test may be performed again to perform hardware repair on the fail cell. In this case, the number of replacement cells may be reduced.

On the other hand, it is also possible to replace specific timing using the repair apparatus of the present invention at the wafer level. That is, by replacing the corresponding timing using an optional fuse for a weak wafer in a specific test item in a wafer state and performing a repair by performing a proof test, the yield may be improved.

In addition, wafer-level repair can be performed more reliably than anti-fuse because it uses an optional fuse rather than an anti-fuse.

As described above, the repair apparatus according to the present invention can optimize the operation timing characteristics by replacing specific timings with other timings instead of replacing failed cells, thereby improving product yield.

In addition, since the number of fuses can be reduced since the fuse used only sets whether or not the repair is to be performed, there is an effect of reducing the error due to the fuse cutting.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

Determination means for determining whether to repair according to a result of a test on the semiconductor memory device; And adjusting means for adjusting the operation timing in accordance with the determination of the determining means. The method of claim 1, The determining unit includes at least one fuse for determining whether to repair. The method of claim 2, And the determining means further comprises determining means for determining whether the fuse is blown or not. The method of claim 1, The adjusting means, Normal adjustment means for adjusting the operation timing in the normal mode; Repair adjusting means for adjusting an operation timing in a repair mode; And And selecting means for transmitting the operation timing signals input according to the output signal of the determining means to one of the normal adjusting means and the repair adjusting means. The method of claim 4, wherein Wherein said normal adjustment means and said repair adjustment means are each composed of delay means having different delay times. The method of claim 5, wherein And said normal adjusting means and said repair adjusting means are each composed of an inverter chain. The method of claim 1, Wherein the test is a test performed at a wafer level. The method of claim 7, wherein The determining unit includes at least one fuse for determining whether to repair. The method of claim 8, The fuse is a repair device of a semiconductor memory device, characterized in that consisting of an optional fuse. The method of claim 8, And the determining means further comprises determining means for determining whether the fuse is blown or not.