KR20040049177A - A register bank circuit for elevating operation speed of a microprocessor - Google Patents

Abstract

PURPOSE: A register bank circuit for improving an operation speed of a microprocessor is provided to improve the operation speed of the microprocessor by shortening a data read delay of the register bank circuit. CONSTITUTION: A register file(110) stores the inputted data by responding to a write control signal, and outputs the read data to one from the output terminals by responding to a read control signal. Keeper circuits(120,130,140) are connected to the output terminals through each data bus and keep a voltage level of the read data loaded to the data bus for a predetermined time. Precharge circuits(150,160,170) are connected to the keeper circuits through each data bus and keep the voltage of the data bus to a predetermined internal voltage level by responding to a precharge control signal.

Description

A register bank circuit for elevating operation speed of a microprocessor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to microprocessors and, more particularly, to register bank circuitry that improves the operating speed of a microprocessor.

In general, the microprocessor includes a register bank circuit that temporarily stores data requested by the microprocessor, such as operation result data of each functional block or data read from the external memory, in addition to an external memory.

Since the register bank circuit has a very fast operation speed compared to the data write and read operations of the external memory, the register bank circuit is very efficient in executing a program requiring real time work.

1 is a block diagram illustrating a register bank circuit and functional blocks according to the prior art.

As shown in FIG. 1, the register bank circuit according to the related art includes a register file 10, a precharge circuit 20, a keeper circuit 30, a latch circuit 40, and a mux. ) Circuit 50.

The register file 10 stores data DATA_W input in response to a predetermined write control signal, and outputs the stored data DATA_W as internal output data DATA_R1 in response to a predetermined read control signal.

The precharge circuit 20 precharges the output terminal of the register file 10 to maintain a predetermined voltage level in response to a predetermined precharge control signal, and when the internal output data DATA_R1 is outputted, the precharge circuit 20 Stop the charge operation.

The keeper circuit 30 maintains the value of the internal output data DATA_R1 for a predetermined time, and the latch circuit 40 reads the internal output data DATA_R1 in response to a latch enable signal input from the outside. Output as DATA_R2).

The mux circuit 50 includes a plurality of muxes, and any one of the plurality of muxes outputs the read data DATA_R2 in response to a selection signal input from the outside.

Here, the read data DATA_R2 may include data required by a plurality of functional blocks. In FIG. 1, a prefetch unit (hereinafter referred to as PU) 60, an arithmetic and logic unit (hereinafter referred to as ALU) 70, and a load / store unit among the plurality of functional blocks. Only 80 (Load and Store Unit, hereinafter LSU) is shown.

FIG. 2 is a detailed circuit diagram of the register bank circuit shown in FIG. 1.

As shown in FIG. 2, the register file 10 includes a plurality of transfer gates 11, a plurality of storage entries 12, and a plurality of output driver groups 13.

Inputs of the plurality of transmission gates 11 are connected to an input node INODE, and the plurality of transmission gates 11 are turned on in response to each of the write control signals EN_W1 to EN_WN and are inputted. Write data DATA_W is output. Here, the write control signals EN_W1 to EN_WN are output from a separate control circuit (not shown).

Each of the plurality of storage entries 12 includes a plurality of storage cells 14 connected in series and is connected in series to each of the plurality of transmission gates 11.

Each of the plurality of storage cells 14 is a latch circuit including inverters 15 and 16.

Each of the plurality of output driver groups 13 includes a plurality of output drivers 17. An input of each of the plurality of output drivers 17 is connected to an output terminal of each of the plurality of storage cells 14, and an output is connected to an output node PNODE.

In the register file 10, the transfer gate 11, the storage entry 12, and the output driver group 13 are connected in series to form one register line, and the input node INODE and the output node are connected to each other. A plurality of the resistor lines are connected in parallel between (PNODE).

In addition, each of the plurality of output drivers 17 includes NMOS transistors N1 and N2.

In the NMOS transistors N1, read control signals EN_R11 to EN_RNM are respectively input to a gate, a drain is connected to the output node PNODE, and a source is supplied to the drains of the NMOS transistors N2. Connected. The read control signals EN_R11 to EN_RNM are signals output from a separate control circuit (not shown).

The NMOS transistors N1 are turned on when the read control signals EN_R11 to EN_RNM are activated, and output the internal read data DATA_R1 to the output node PNODE.

In addition, gates of the NMOS transistors N2 are connected to output terminals of the storage cells 14, respectively, and a source thereof is connected to ground. The NMOS transistors N2 are turned on in response to an output signal of the storage cells 14.

The precharge circuit 20 may be implemented as a PMOS transistor P1. A source is connected to the output node PNODE, a drain is connected to a predetermined internal voltage VDD, and a predetermined precharge control signal EN_PR1 is input to the gate of the PMOS transistor P1.

The PMOS transistor P1 is turned on in response to the precharge control signal EN_PR1 to maintain the voltage of the output node PNODE at a constant voltage level.

The keeper circuit 30 may be implemented as a PMOS transistor P2 and an inverter 31. The PMOS transistor P2 has a gate connected to an output terminal of the inverter 31, a drain connected to the internal voltage VDD, and a source connected to the output node PNODE.

The inverter 31 inverts and outputs the internal output data DATA_R1 signal output to the output node PNODE, and the PMOS transistor P2 is turned on in response to the output signal of the inverter 31. Or turned off. The keeper circuit 30 maintains the voltage level of the internal output data DATA_R1 output to the output node PNODE at a predetermined voltage level.

The latch circuit 40 latches the internal output data DATA_R1 output from the keeper circuit 30 in response to a predetermined latch control signal EN_LA to read the data circuit 50 as the read data DATA_R2. Output to the input node (MNODE) of).

Here, the read data DATA_R2 includes prefetch data DATA_PU, arithmetic / logical data DATA_ALU, and load / store data DATA_LSU.

The prefetch data DATA_PU is input to the PU 60, arithmetic / logical data DATA_ALU is input to the ALU 70, and the load / store data DATA_LSU is input to the LSU 80. do.

The mux circuit 50 includes first to third muxes 51, 52, and 53, and the first to third muxes 51, 52, and 53 are a plurality of drivers 511 to 51K. , 521-52K, 531-53K). The first to third muxes 51, 52, and 53 are dynamic muxes, and the number of drivers may be variously set according to the number of input data.

Each of the drivers 511 to 51K may be implemented with NMOS transistors N11 and N21 to N1K and N2K, and each of the drivers 521 to 52K may be an NMOS transistor N31 and N41 to N3K and N4K. Can be executed. Each of the drivers 531 to 53K may be implemented by NMOS transistors N51 and N61 to N5K and N6K.

Select signals SEL11 to SEL1K are input to gates of the NMOS transistors N11 to N1K, a drain is connected to a first output terminal MOUT1, and drains of the NMOS transistors N21 to N2K. The source is connected to. The selection signals SEL11 to SEL1K are signals output from a separate control circuit (not shown).

The gate of the NMOS transistor N21 is connected to the input node MNODE, and the source is connected to ground. In addition, external input data INO11 to INO1K are input to the gates of the NMOS transistors N22 to N2K. The external input data INO11 to INO1K are data signals output from external function blocks.

When any one of the selection signals SEL11 to SEL1K is enabled, the first mux 51 operates any one of the plurality of drivers 511 to 51K to operate the read data DATA_R2 and the external device. One of the input data INO11 to INO1K is output to the first output terminal MOUT1. In this case, the read data DATA_R2 includes the prefetch data DATA_PU.

In addition, an additional precharge circuit implemented by the PMOS transistor P3 is connected to the output terminal of the first mux 51. A predetermined precharge control signal EN_PR2 is input to the gate of the PMOS transistor P3, a source is connected to the internal voltage VDD, and the drain is connected to the first output terminal MOUT1.

The PMOS transistor P3 precharges the output terminal of the first mux 51 to a predetermined voltage level.

Select signals SEL21 to SEL2K are input to a gate, a drain is connected to a second output terminal MOUT2, and drains of the NMOS transistors N41 to N4K are input to the NMOS transistors N31 to N3K. The source is connected to. The selection signals SEL21 to SEL2K are signals output from a separate control circuit (not shown).

The gate of the NMOS transistor N41 is connected to the input node MNODE, and the source is connected to ground. In addition, external input data INO21 to INO2K are input to the gates of the NMOS transistors N42 to N4K. The external input data INO21 to INO2K are data signals output from external functional blocks.

When any one of the selection signals SEL21 to SEL2K is enabled, the second mux 52 operates any one of the plurality of drivers 521 to 52K to operate the read data DATA_R2 and the external device. One of the input data INO21 to INO2K is output to the second output terminal MOUT2. In this case, the read data DATA_R2 includes the arithmetic / logical data DATA_ALU.

In addition, an additional precharge circuit implemented by the PMOS transistor P4 is connected to the output terminal of the second mux 52. The precharge control signal EN_PR2 is input to the gate of the PMOS transistor P4, a source is connected to the internal voltage VDD, and the drain is connected to the second output terminal MOUT2.

The PMOS transistor P4 precharges the output terminal of the second mux 52 to a predetermined voltage level.

Select signals SEL31 to SEL3K are input to gates of the NMOS transistors N51 to N5K, a drain is connected to a third output terminal MOUT3, and drains of the NMOS transistors N61 to N6K. The source is connected to. The selection signals SEL31 to SEL3K are signals output from a separate control circuit (not shown).

The gate of the NMOS transistor N61 is connected to the input node MNODE, and the source is connected to ground. In addition, external input data INO31 to INO3K are input to the gates of the NMOS transistors N62 to N6K. The external input data INO31 to INO3K are data signals output from external functional blocks.

When any one of the selection signals SEL31 to SEL3K is enabled, the third mux 53 operates any one of the plurality of drivers 531 to 53K to operate the read data DATA_R2 and the external device. One of the input data INO31 to INO3K is output to the third output terminal MOUT3. In this case, the read data DATA_R2 includes the load / store data DATA_LSU.

In addition, an additional precharge circuit implemented by the PMOS transistor P5 is connected to the output terminal of the third mux 53. The precharge control signal EN_PR2 is input to the gate of the PMOS transistor P5, a source is connected to the internal voltage VDD, and the drain is connected to the third output terminal MOUT3.

The PMOS transistor P5 precharges the output terminal of the third mux 53 to a predetermined voltage level.

However, in the register bank circuit according to the prior art as described above, since data read from the register file is output through the mux circuit, a delay time of one clock cycle until the read data is output after the read control signal is activated There is a problem that occurs.

In addition, in the register bank circuit according to the prior art as described above, since data read from the register file is output through the mux circuit, the data output path is long, thereby increasing the parasitic capacitance.

3 is a timing chart illustrating main input / output signals of the register bank circuit shown in FIG. 2. 3 illustrates an example in which the prefetch data DATA_PU is output from the first output terminal MOUT1.

As shown in FIG. 3, when the read control signal EN_R11 is enabled in synchronization with the falling edge of the clock signal CLOCK, the NMOS transistor N1 of the output driver 17 is turned on. As a result, the internal output data DATA_R1 having a predetermined voltage level is output to the output node PNODE precharged by the precharge circuit 20 to the internal voltage VDD level.

Thereafter, the keeper circuit 30 inverts and outputs the internal output data DATA_R1. When the latch control signal EN_LA is enabled, the latch circuit 40 outputs the output signal of the keeper circuit 30 as the read data DATA_R2. The read data DATA_R2 is input to the first mux 50.

When the selection signal SEL11 is enabled, the first mux 50 outputs the read data DATA_R2, that is, the prefetch data DATA_PU to the first output terminal MOUT1.

As illustrated in FIG. 3, the prefetch data DATA_PU is output after a time of one clock cycle elapses after the read control signal EN_R11 is enabled.

The output delay time of the read data generated in the register bank circuit as described above is a major factor in reducing the operation speed of the microprocessor. Therefore, there is an urgent need for a register bank circuit capable of shortening the output delay time of read data.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a register bank circuit which reduces a data read delay time of a register bank circuit and improves an operation speed of a microprocessor.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram illustrating a register bank circuit and functional blocks according to the prior art.

FIG. 2 is a detailed circuit diagram of the register bank circuit shown in FIG. 1.

FIG. 3 is a timing chart showing main input / output signals of the register bank circuit shown in FIG. 2.

4 is a block diagram illustrating a register bank circuit and functional blocks for improving an operating speed of a microprocessor according to an embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the register bank circuit shown in FIG. 4.

FIG. 6 is a timing chart illustrating main input / output signals of the register bank circuit shown in FIG. 5.

According to an aspect of the present invention, a register bank circuit for improving an operating speed of a microprocessor includes a register file, a keeper circuit, and a precharge circuit.

The register file stores write data input in response to a predetermined write control signal, and outputs read data read in response to a predetermined read control signal to any one of a plurality of output terminals. The keeper circuit is connected to each of the plurality of output terminals via a data bus, and maintains the voltage level of the read data carried on the data bus for a predetermined time. The precharge circuit is connected to the keeper circuit via a data bus and maintains the voltage of the data bus at a predetermined internal voltage level in response to a predetermined precharge control signal.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a block diagram illustrating a register bank circuit and functional blocks for improving an operating speed of a microprocessor according to an embodiment of the present invention.

As shown in FIG. 4, a register bank circuit according to an embodiment of the present invention may include a register file 110, first to third keeper circuits 120, 130, and 140, and first to third precharge circuits. Fields 150, 160, 170, a latch circuit 40, and first to third data buses 310, 320, and 330.

In addition, a prefetch unit (hereinafter referred to as a PU) 180 is connected to the first data bus 310, and an arithmetic and logic unit (hereinafter, referred to as a PU) is connected to the second data bus 320. ALU 190 is connected, and a load / store unit (hereinafter referred to as LSU) 200 is connected to the third data bus 330.

The register file 110 stores data DATA_W (hereinafter referred to as write data) input to the input terminal IN in response to a predetermined write control signal, and stores the data stored in response to a predetermined read control signal. The data DATA_W is output to any one of the first to third output terminals ROUT1 to ROUT3.

Here, the register file 110 outputs prefetch data DATA_PU used in the PU 180 to the first output terminal ROUT1 and the ALU 190 to the second output terminal ROUT2. Outputs the arithmetic / logical data (DATA_ALU) used in. The register file 110 outputs load / store data DATA_LSU used in the LSU 200 to the third output terminal ROUT3.

The first keeper circuit 120 is connected to the first output terminal ROUT1 through the first data bus 310, and the second keeper circuit 130 is connected through the second data bus 320. It is connected to the second output terminal (ROUT2), the third keeper circuit 140 is connected to the third output terminal (ROUT3) via the third data bus 330.

The first to third keeper circuits 120 to 140 may include the prefetch data DATA_PU, the arithmetic / logical data DATA_ALU, and the like which are output to the first to third data buses 310 to 330. The voltage level of the load / store data DATA_LSU is maintained at a predetermined voltage level.

The first to third keeper circuits 120 to 140 have voltage levels of the data DATA_PU, DATA_ALU, and DATA_LSU on the first to third data buses 120 to 140. Lowered to prevent output with wrong data.

The first to third keeper circuits 120 to 140 may preferably be implemented as flip-flops in the form of a sense amplifier.

The first precharge circuit 150 is connected to the first keeper circuit 120 through the first data bus 310, and the second precharge circuit 160 is connected to the second data bus 320. The second keeper circuit 130 is connected to the third keeper circuit 130, and the third precharge circuit 170 is connected to the third keeper circuit 140 through the third data bus 330.

Each of the first to third precharge circuits 150, 160, and 170 maintains the first to third data buses 310 to 330 at a predetermined voltage level in response to a predetermined precharge control signal. Precharge to stop the precharge operation when the data (DATA_PU, DATA_ALU, DATA_LSU) is output.

The register bank circuit according to an embodiment of the present invention configured as described above will be described in more detail with reference to FIG. 5 as follows.

FIG. 5 is a detailed circuit diagram of the register bank circuit shown in FIG. 4.

The register file 110 has a transfer gate 101, a storage entry (not shown), and an output driver group (not shown) connected in series to form a register line, and the input terminal IN (refer to FIG. 4) The plurality of register lines are connected in parallel between the first to third output terminals ROUT1 to ROUT3 (see FIG. 4).

The storage entry includes a plurality of storage cells 202 connected in series, and the output driver group includes a plurality of output driver circuits 205.

In FIG. 5, only one storage cell 202 of one register line is shown as part of the register file 110.

As shown in FIG. 5, the transfer gate 101 is turned on in response to a predetermined write control signal EN_W and outputs input write data DATA_W. Here, the write control signal EN_W is output from a separate control circuit (not shown).

The storage cell 202 is a latch circuit including first and second inverters 211 and 212, a third inverter 203 is further connected to an output terminal, and a fourth inverter 204 is added to an input terminal. Leads to.

First, third, and fifth output drivers 221, 223, and 225 of the output driver circuit 205 are connected to an output terminal of the third inverter 203, and the output is output to an output terminal of the inverter 204. Second, fourth, and sixth output drivers 222, 224, and 226 of the driver circuit 205 are connected.

Here, the first to sixth output drivers 221 to 226 form one output driver circuit 205. The output driver circuits 205 in the same number as the number of the plurality of storage cells 202 included in one storage entry form one output driver group.

The third and fourth inverters 203 and 204 are connected to the storage cell 202 to drive the first to sixth output drivers 221 to 226 having a large loading capacitance.

Output terminals of the first and second output drivers 221 and 222 are connected to the first output terminal ROUT1, and output terminals of the third and fourth output drivers 223 and 224 are the second output. The output terminal of the fifth and sixth output drivers 225 and 226 is connected to the third output terminal ROUT3.

The first data bus 310 is connected to the first output terminal ROUT1, the second data bus 320 is connected to the second output terminal ROUT2, and the third output terminal ROUT3 is connected to the first output terminal ROUT1. The third data bus 330 is connected thereto.

Here, each of the first to third data buses 310, 320, and 330 may include first, third, and fifth buses 311, 321, and 331 for transmitting a high data output signal, and low data. It is a dual rail bus including second, fourth, and sixth buses 312, 322, and 332 which transmit an output signal.

The first output driver 221 includes first and second NMOS transistors N71 and N72, and the second output driver 222 includes third and fourth NMOS transistors N73 and N74. The third output driver 223 includes fifth and sixth NMOS transistors N75 and N76.

The fourth output driver 224 includes seventh and eighth NMOS transistors N77 and N78, and the fifth output driver 225 includes ninth and tenth NMOS transistors N79 and N80. The sixth output driver 226 includes eleventh and twelfth NMOS transistors N81 and N82.

A first read control signal EN_R1 is input to a gate of the first and third NMOS transistors N71 and N73, and drains are respectively connected to the first and second buses 311 and 312.

In addition, the source of the first NMOS transistor N71 is connected to the drain of the second NMOS transistor N72. The gate of the second NMOS transistor N72 is connected to the output terminal of the third inverter 203, and the source is connected to ground.

The source of the third NMOS transistor N73 is connected to the drain of the fourth NMOS transistor N74. A gate of the fourth NMOS transistor N74 is connected to an output terminal of the fourth inverter 204, and a source thereof is connected to ground.

In the fifth and seventh NMOS transistors N75 and N77, a second read control signal EN_R2 is input to a gate and drains thereof are connected to the third and fourth buses 321 and 322, respectively.

In addition, the source of the fifth NMOS transistor N75 is connected to the drain of the sixth NMOS transistor N76. A gate of the sixth NMOS transistor N76 is connected to an output terminal of the third inverter 203, and a source thereof is connected to ground.

The source of the seventh NMOS transistor N77 is connected to the drain of the eighth NMOS transistor N78. A gate of the eighth NMOS transistor N78 is connected to an output terminal of the fourth inverter 204, and a source thereof is connected to ground.

The third read control signal EN_R3 is input to the gate of the ninth and eleventh NMOS transistors N79 and N81, and the drains are connected to the fifth and sixth buses 331 and 332, respectively.

In addition, a source of the ninth NMOS transistor N79 is connected to a drain of the tenth NMOS transistor N80. A gate of the tenth NMOS transistor N80 is connected to an output terminal of the third inverter 203, and a source thereof is connected to ground.

The source of the eleventh NMOS transistor N81 is connected to the drain of the twelfth NMOS transistor N82. A gate of the twelfth NMOS transistor N82 is connected to an output terminal of the fourth inverter 204, and a source thereof is connected to ground.

The first keeper circuit 120 includes first and second PMOS transistors P11 and P12, and the second keeper circuit 130 includes third and fourth PMOS transistors P13 and P14. The third keeper circuit 140 includes fifth and sixth PMOS transistors P15 and P16.

A drain of the first PMOS transistor P11 and a gate of the second PMOS transistor P12 are connected to the first bus 311, and a gate of the first PMOS transistor P11 and the second gate. A drain of the PMOS transistor P12 is connected to the second bus 312. In addition, sources of the first and second PMOS transistors P11 and P12 are connected to an internal voltage VDD.

A drain of the third PMOS transistor P13 and a gate of the fourth PMOS transistor P14 are connected to the third bus 321, and a gate of the third PMOS transistor P13 and the fourth gate. A drain of the PMOS transistor P14 is connected to the fourth bus 322. In addition, sources of the third and fourth PMOS transistors P13 and P14 are connected to an internal voltage VDD.

A drain of the fifth PMOS transistor P15 and a gate of the sixth PMOS transistor P16 are connected to the fifth bus 331, and a gate of the fifth PMOS transistor P15 and the sixth PMOS transistor P15 are connected to the fifth bus 331. A drain of the PMOS transistor P16 is connected to the sixth bus 332. In addition, the sources of the fifth and sixth PMOS transistors P15 and P16 are connected to an internal voltage VDD.

The first precharge circuit 150 includes seventh to ninth PMOS transistors P17 to P19, and the second precharge circuit 160 includes tenth to twelfth PMOS transistors P20 to P22. The third precharge circuit 170 includes thirteenth to fifteenth PMOS transistors P23 to P25.

The first precharge control signal EN_PR1 is input to the gates of the seventh to ninth PMOS transistors P17 to P19, and the sources of the seventh and eighth PMOS transistors P17 and P18 are input. The drain is connected to the internal voltage VDD and the drains are respectively connected to the first and second buses 311 and 312. The source and the drain of the ninth PMOS transistor P19 are connected to the drains of the seventh and eighth PMOS transistors P17 and P18.

Here, the ninth PMOS transistor P19 operates as an equalizer and maintains the same voltage level of the first and second buses 311 and 312.

The second precharge control signal EN_PR2 is input to the gates of the tenth to twelfth PMOS transistors P20 to P22, and the sources of the tenth and eleventh PMOS transistors P20 and P21 are input. The drain is connected to the internal voltage VDD and the drains are respectively connected to the third and fourth buses 321 and 322. Sources and drains of the twelfth PMOS transistor P22 are connected to drains of the tenth and eleventh PMOS transistors P20 and P21.

Here, the twelfth PMOS transistor P22 operates as an equalizer, and maintains the same voltage level of the third and fourth buses 321 and 322.

The third precharge control signal EN_PR3 is input to the gates of the thirteenth to fifteenth PMOS transistors P23 to P25, and the sources of the thirteenth and fourteenth PMOS transistors P23 and P24 are respectively connected to the gates of the thirteenth to fifteenth PMOS transistors P23 to P25. It is connected to the internal voltage VDD, and drains are connected to the fifth and sixth buses 331 and 332, respectively. Sources and drains of the fifteenth PMOS transistor P25 are connected to drains of the thirteenth and fourteenth PMOS transistors P23 and P24.

Here, the fifteenth PMOS transistor P25 operates as an equalizer and maintains the same voltage level of the fifth and sixth buses 331 and 332.

Here, the first to third precharge control signals EN_PR1 to EN_PR3 are signals output from a separate control circuit (not shown).

The operation of the register bank circuit according to an embodiment of the present invention configured as described above will be described in detail with reference to FIGS. 5 and 6.

FIG. 6 is a timing chart illustrating main input / output signals of the register bank circuit shown in FIG. 5.

First, the transfer gate 201 outputs write data DATA_W which is turned on as the write control signal EN_W is activated. The storage cell 202 stores the write data DATA_W output from the transmission gate 201.

The write data DATA_W preferably includes prefetch data DATA_PU_H and DATA_PU_L, arithmetic / logical data DATA_ALU_H and DATA_ALU_L, and load / store data DATA_LSU_H and DATA_LSU_L.

5 and 6, the case where the write data DATA_W is the prefetch data DATA_PU_H and DATA_PU_L will be described as an example.

When the first read control signal EN_R1 is activated in synchronization with a clock signal CLOCK, the first and third NMOS transistors N71 and N73 are turned on.

The third inverter 203 inverts the output data of the storage cell 202 and outputs the inverted data. Here, an example in which the write data DATA_W is '1' will be described below.

The write data DATA_W '1' is inverted by the second inverter 211 of the storage cell 202 and output as data '0'.

The third inverter 203 inverts the data '0' and outputs the data '1'. The second NMOS transistor N72 is turned on by inputting the data '1' to a gate.

The fourth inverter 204 inverts the write data DATA_W '1' and outputs data '0'. The fourth NMOS transistor N74 is turned off when the data '0' is input to a gate.

As a result, the prefetch data DATA_PU_H is output to the first bus 311 of the first data bus 310 by the first and second NMOS transistors N71 and N72.

In addition, even when the third NMOS transistor N73 is turned on, the fourth NMOS transistor N74 is turned off, and thus the prefetch data DATA_PU_L is not output to the second bus 312.

Here, the first and second buses 311 and 312 are precharged to the internal voltage VDD by the first precharge circuit 150.

Therefore, as the first and second NMOS transistors N71 and N72 are turned on, the voltage level of the prefetch data DATA_PU_H of the first bus 311 is as shown in FIG. 6. The voltage is changed from the internal voltage VDD level to the ground voltage level.

At this time, the voltage level of the prefetch data DATA_PU_L of the second bus 312 has the internal voltage VDD level.

In addition, the first PMOS transistor P11 of the first keeper circuit 120 is turned off because the internal voltage VDD is input to the gate, and the second PMOS transistor P12 has the ground voltage. It is turned on because it is input to the gate.

As the second PMOS transistor P12 is turned on, the voltage level of the prefetch data DATA_PU_L of the second bus 312 is continuously maintained at the internal voltage VDD level.

The first keeper circuit 120 prevents incorrect data from being output by changing the voltage levels of the prefetch data DATA_PU_H and DATA_PU_L according to an external voltage change.

As a result, the write data DATA_W '1' stored in the storage cell 202 is output as the prefetch data DATA_PU_H through the first bus 311.

In the first precharge circuit 150, as the first precharge control signal EN_PR1 is activated, the seventh to ninth PMOS transistors P17 to P19 are turned on.

As the seventh PMOS transistor P17 is turned on, the first bus 311 is precharged to the internal voltage VDD level, and as the eighth PMOS transistor P18 is turned on, the first bus 311 is turned on. The two buses 312 are also precharged to the internal voltage level VDD.

In addition, as the ninth PMOS transistor P19 is turned on, the first and second buses 311 and 312 are maintained at the same voltage level.

Here, since the first precharge control signal EN_PR1 is inactive when the first read control signal EN_R1 is active, when the prefetch data DATA_PU_H and DATA_PU_L are output, the first precharge control signal EN_R1 is inactive. The precharge circuit 150 stops the precharge operation.

Thereafter, the PU 180 may directly receive the prefetch data DATA_PU_H and DATA_PU_L mounted on the first and second buses 311 and 312.

Next, when the write data DATA_W is '0', the second NMOS transistor N72 is turned off as opposed to the case where the write data DATA_W is '1', and the fourth NMOS transistor is next. (N74) is turned on.

Accordingly, the prefetch data DATA_PU_L is output to the second bus 312 of the first data bus 310 by the third and fourth NMOS transistors N73 and N74.

In addition, even when the first NMOS transistor N71 is turned on, the second NMOS transistor N72 is turned off, and thus the prefetch data DATA_PU_L is not output to the first bus 311.

Next, when the write data DATA_W is the arithmetic / logical data DATA_ALU_H and DATA_ALU_L or the load / store data DATA_LSU_H and DATA_LSU_L, a specific data read operation of the register bank circuit may be performed from the register bank circuit. Since the fetch data DATA_PU_H and DATA_PU_L are the same as the case where the fetch data is read, the description will be omitted.

As described above, according to the register bank circuit of the present invention, as shown in FIG. 6, the delay time until the prefetch data DATA_PU_H is output after the read control signal EN_R1 is activated is conventional. Compared to the register bank circuit according to the technology can be shortened by about 1/2 clock period.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the register bank circuit of the present invention, since the data read delay time is shortened, the operation speed of the microprocessor can be improved.

In addition, according to the register bank circuit of the present invention, since the data is directly output to the dual rail bus connected to the register file without passing through the mux circuit, there is an effect that can reduce the parasitic capacitance.

Claims (15)

The data input in response to the predetermined write control signal (hereinafter referred to as write data) is stored, and the data read in response to the predetermined read control signal (hereinafter referred to as read data) is selected from among a plurality of output terminals. A register file to output to one; A keeper circuit connected to each of the plurality of output terminals through a data bus and maintaining a voltage level of the read data loaded on the data bus for a predetermined time; And A precharge circuit connected to the keeper circuit through the data bus, the precharge circuit maintaining a voltage of the data bus at a predetermined internal voltage level in response to a predetermined precharge control signal; Register bank circuit to improve the. The method of claim 1, wherein the read data, First read data output to a first output terminal of the plurality of output terminals; Second read data output to a second output terminal of the plurality of output terminals; And And a third read data output to a third output terminal of the plurality of output terminals. The method of claim 2, wherein the data bus, A first data bus coupled to the first output terminal and transmitting the first read data to a first functional block; A second data bus connected to the second output terminal and transmitting the second read data to a second functional block; And And a third data bus coupled to the third output terminal, the third data bus transferring the third read data to a third functional block. The method of claim 3, The first data bus, A first bus for transmitting a high signal of the first read data; And A second bus transmitting the low signal of the first read data; The second data bus is, A third bus transmitting a high signal of the second read data; And A fourth bus for transmitting a low signal of the second read data, The third data bus, A fifth bus transmitting a high signal of the third read data; And And a sixth bus for transmitting the low signal of the third read data. The method of claim 3, wherein the register file, A plurality of transmission gates turned on in response to the write control signal to output the write data; A plurality of storage entries, coupled to each of the plurality of transmission gates, for storing the write data; And A plurality of storage entries connected between the plurality of storage entries and the first to third output terminals, respectively, for outputting the read data to any one of the first to third output terminals in response to the read control signal. And a register bank circuit for improving the operation speed of the microprocessor. The method of claim 5, wherein each of the plurality of storage entries, And a plurality of storage cells which store the write data and are connected in series. The method of claim 6, wherein each of the plurality of output driver groups, The read data is connected between an input and an output of each of the plurality of storage cells and the first to third output terminals, respectively, in response to the write data signal and the read data signal of the plurality of storage cells. And a plurality of output driver circuits output to any one of the first to third output terminals. The method of claim 7, wherein each of the plurality of output driver circuits, A first output driver connected between an output of one of the plurality of storage cells and the first bus and turned on in response to a first read control signal of the read control signals; A second output driver connected between the input of the storage cell and the second bus and turned on in response to the first read control signal; A third output driver connected between an output of the storage cell and the third bus and turned on in response to a second read control signal of the read control signals; A fourth output driver connected between the input of the storage cell and the fourth bus and turned on in response to the second read control signal; A fifth output driver connected between an output of the storage cell and the fifth bus and turned on in response to a third read control signal of the read control signals; And And a sixth output driver connected between the input of the storage cell and the sixth bus and turned on in response to the third read control signal. The method of claim 8, wherein each of the plurality of storage entries, A plurality of first inverters connected to outputs of each of the plurality of storage cells and outputting the read data signal by inverting the read data signals; And And a plurality of second inverters connected to an input of each of the plurality of storage cells and inverting and outputting the write data signal. The method of claim 9, Each of the plurality of first inverters, Further connected to the first, third, and fifth output drivers, respectively driving the first, third, and fifth output drivers according to the read data signal, Each of the plurality of second inverters, The microprocessor is further connected to the second, fourth, and sixth output drivers, and drives the second, fourth, and sixth output drivers according to the write data signal. Register bank circuit to improve speed. The method of claim 10, wherein each of the first to sixth output drivers, A register bank circuit for improving the operation speed of a microprocessor, comprising a plurality of NMOS transistors. The method of claim 8, wherein the keeper circuit, A first keeper circuit connected to the first output terminal through the first data bus and maintaining a voltage level of the first read data for the predetermined time; A second keeper circuit connected to the second output terminal through the second data bus and maintaining a voltage level of the second read data for the predetermined time; And And a third keeper circuit connected to the third output terminal through the third data bus, the third keeper circuit maintaining the voltage level of the third read data for the predetermined time period. Register bank circuit. The method of claim 12, wherein each of the first to third keeper circuits, A register bank circuit for improving the operation speed of a microprocessor, characterized in that it comprises a plurality of PMOS transistors. The method of claim 13, wherein the precharge circuit, A first precharge circuit configured to precharge the first data bus to the internal voltage level in response to a first precharge control signal among the precharge control signals; A second precharge circuit configured to precharge the second data bus to the internal voltage level in response to a second precharge control signal among the precharge control signals; And And a third precharge circuit configured to precharge the third data bus to the internal voltage level in response to a third precharge control signal among the precharge control signals. Bank circuit. The method of claim 14, The first precharge control signal is inactive when the first read control signal is in an active state, The second precharge control signal is inactive when the second read control signal is active, And the third precharge control signal is inactive when the third read control signal is in an active state.