KR20040048457A - Chip stack package - Google Patents
Chip stack package Download PDFInfo
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- KR20040048457A KR20040048457A KR1020020076177A KR20020076177A KR20040048457A KR 20040048457 A KR20040048457 A KR 20040048457A KR 1020020076177 A KR1020020076177 A KR 1020020076177A KR 20020076177 A KR20020076177 A KR 20020076177A KR 20040048457 A KR20040048457 A KR 20040048457A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 스택된 칩들과 기판간의 전기적 연결이 용이하도록 한 칩 스택 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a chip stack package for facilitating electrical connection between stacked chips and a substrate.
전기/전자 제품의 고성능화가 진행됨에 따라 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 많은 기술들이 제안 및 연구되고 있다. 그런데, 패키지는 하나의 반도체 칩이 탑재되는 것을 기본으로 하기 때문에 용량 증가에 한계가 있다.As the performance of electrical / electronic products is advanced, many technologies for mounting a larger number of packages on a limited size substrate have been proposed and studied. However, since the package is based on one semiconductor chip mounted there is a limit to the capacity increase.
여기서, 메모리 칩의 용량 증대, 즉, 고집적화를 이룰 수 있는 방법으로는 한정된 공간 내에 보다 많은 수의 셀을 제조해 넣는 기술이 일반적으로 알려져 있다. 그런데, 이와 같은 방법은 정밀한 미세 선폭을 요구하는 등, 고난도의 공정 기술과 많은 개발 시간을 필요로 한다. 따라서, 보다 용이하게 고집적화를 이룰 수 있는 방법으로서 스택킹(stacking) 기술이 개발되었고, 현재 이에 대한 연구가 활발히 진행되고 있다.Here, as a method of increasing the capacity of the memory chip, that is, high integration, a technique of manufacturing a larger number of cells in a limited space is generally known. However, such a method requires a high level of process technology and a lot of development time, such as requiring a precise fine line width. Therefore, a stacking technology has been developed as a method of achieving high integration more easily, and researches on this are being actively conducted.
반도체 업계에서 말하는 스택킹이란, 적어도 2개 이상의 반도체 칩을 스택하여 메모리 용량을 배가시키는 기술이다. 이러한 스택킹 기술에 의하면, 2개의 64M DRAM급 칩을 스택하여 128M DRAM급으로 구성할 수 있고, 또한, 2개의 128M DRAM급 칩을 스택하여 256M DRAM급으로 구성할 수 있다. 게다가, 스택킹 기술에 의하면, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 잇점을 갖는다.Stacking as used in the semiconductor industry is a technique of stacking at least two or more semiconductor chips to double the memory capacity. According to such a stacking technology, two 64M DRAM chips can be stacked to form a 128M DRAM class, and two 128M DRAM chips can be stacked to be 256M DRAM class. In addition, the stacking technique has advantages in terms of mounting density and efficiency of mounting area use.
상기 2개의 반도체 칩을 스택하는 방법으로는 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 패키지를 스택하는 방법이 있으며, 효율면에서는 하나의 패키지 내에 2개의 칩을 내장시킨 칩 스택 패키지가 더 우수하다.The stacking method of the two semiconductor chips includes a method of embedding two stacked chips in one package and a method of stacking two packaged packages. In terms of efficiency, two chips are embedded in one package. The chip stack package is better.
도 1은 종래 기술에 따른 칩 스택 패키지의 일예를 도시한 단면도이다.1 is a cross-sectional view showing an example of a chip stack package according to the prior art.
도시된 바와 같이, 바텀 칩(4)과 탑 칩(6)은 패드 형성면이 위쪽에 배치되도록 접착제(3)에 의해 스택되어 회로패턴(2)을 구비한 기판(1) 상에 부착되어 있으며, 각 칩(4, 6)의 본딩패드들(도시안됨)은 금속 와이어(7)에 의해 기판(1)의 회로패턴(2)과 전기적으로 연결되어져 있다.As shown, the bottom chip 4 and the top chip 6 are stacked on the substrate 1 with the circuit pattern 2 stacked by an adhesive 3 so that the pad forming surface is disposed upward. The bonding pads (not shown) of the chips 4 and 6 are electrically connected to the circuit pattern 2 of the substrate 1 by the metal wires 7.
또한, 바텀 칩(4) 및 탑 칩(6)과 금속 와이어(7)를 포함한 기판(1)의 상부면은 봉지제(8)로 밀봉되어 있으며, 상기 기판(1)의 하부면에는 외부 회로와 전기적으로 접속되는 솔더 볼(9)이 부착되어져 있다.In addition, an upper surface of the substrate 1 including the bottom chip 4 and the top chip 6 and the metal wire 7 is sealed with an encapsulant 8, and an external circuit is provided on the lower surface of the substrate 1. Solder balls 9 are electrically attached to each other.
그러나, 전술한 종래의 칩 스택 패키지는 바텀 칩 및 탑 칩 모두가 각각 와이어 본딩 공정을 통해 기판 회로패턴과의 전기적 연결이 이루어져야 하므로, 제조 공정상의 어려움이 있다.However, in the above-described conventional chip stack package, since both the bottom chip and the top chip have to be electrically connected to the substrate circuit pattern through wire bonding processes, there is a difficulty in the manufacturing process.
또한, 종래의 칩 스택 패키지는 바텀 칩으로서 가장자리 패드형의 칩만이 적용될 수 있을 뿐, 센터 패드형 칩은 적용할 수 없다.In addition, the conventional chip stack package can be applied only to the edge pad type chip as the bottom chip, but not the center pad type chip.
게다가, 바텀 칩과 탑 칩간의 스택은 금속 와이어의 공간을 충분히 확보해 주어야 하므로, 구조상, 패키지의 높이를 줄이는데 한계가 있다.In addition, since the stack between the bottom chip and the top chip has to secure enough space of the metal wire, there is a limit in reducing the height of the package in structure.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 칩들과 기판간의 전기적 연결이 용이하도록 하면서 센터 패드형의 칩도 적용할 수 있는 칩 스택 패키지를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a chip stack package that can be applied to a center pad type chip while making electrical connection between chips and a substrate easy.
도 1은 종래의 칩 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional chip stack package.
도 2는 본 발명의 실시예에 따른 칩 스택 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a chip stack package according to an embodiment of the present invention.
도 3a 내지 도 3c는 본 발명의 실시예에 따른 칩 스택 패키지의 제조 공정을 설명하기 위한 단면도.3A to 3C are cross-sectional views illustrating a manufacturing process of a chip stack package according to an exemplary embodiment of the present invention.
도 4 내지 도 6은 본 발명의 다른 실시예들에 따른 칩 스택 패키지들을 도시한 단면도.4 through 6 are cross-sectional views illustrating chip stack packages according to other embodiments of the present invention.
도 7 및 도 8은 본 발명의 또 다른 실시예들에 따른 칩 스택 패키지들을 도시한 단면도.7 and 8 are cross-sectional views illustrating chip stack packages according to still other embodiments of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 기판 22 : 회로패턴21: substrate 22: circuit pattern
23 : 이방성 도전 필름 24 : 바텀 칩23: anisotropic conductive film 24: bottom chip
25 : 접착제 26 : 탑 칩25: adhesive 26: top chip
27 : 금속 와이어 28 : 봉지제27: metal wire 28: sealing agent
29 : 솔더 볼 30 : 마운트 스테이지29: solder ball 30: mount stage
40 : 마운트 헤드 50 : 리드프레임40: mount head 50: lead frame
50a : 인너리드 50b : 아우터리드50a: inner lead 50b: outer lead
상기와 같은 목적을 달성하기 위하여, 본 발명은, 회로패턴을 구비한 기판; 상기 기판 상에 이방성 도전 필름(Anisotropic Conductive Film)에 의해 페이스 다운 타입으로 부착되면서 그의 본딩패드가 기판의 회로패턴과 전기적으로 연결된 바텀 칩; 상기 바텀 칩의 후면 상에 접착제에 의해 페이스 업 타입으로 부착된 탑 칩; 상기 탑 칩의 본딩패드와 기판의 회로패턴간을 전기적으로 연결한 금속 와이어; 상기 바텀 칩과 탑 칩 및 금속 와이어를 포함한 기판의 상부면을 밀봉한 봉지제; 및 상기 기판의 하부면에 부착되어 외부 회로와 전기적으로 접속되는 솔더 볼을 포함하는 칩 스택 패키지를 제공한다.In order to achieve the above object, the present invention is a substrate having a circuit pattern; A bottom chip attached to the substrate by a face down type by an anisotropic conductive film and having a bonding pad electrically connected to a circuit pattern of the substrate; A top chip attached in a face up type by an adhesive on a rear surface of the bottom chip; A metal wire electrically connecting the bonding pad of the top chip to a circuit pattern of the substrate; An encapsulant sealing the upper surface of the substrate including the bottom chip, the top chip, and the metal wire; And a solder ball attached to a lower surface of the substrate and electrically connected to an external circuit.
여기서, 상기 바텀 칩 및 탑 칩은 센터 패드형 및 가장자리 패드형 칩 모두 적용된다. 상기 이방성 도전 필름은 니켈, 금도금 니켈, 은도금 니켈 및 구리로 구성된 그룹으로부터 선택되는 어느 하나의 전도체들을 구비한 에폭시 또는 폴리이미드의 접착제로 이루어지며, 상기 전도체는 1∼500㎛의 직경을 갖는 구(Sphere) 또는 직육면체(Rectangular) 형상을 갖는다. 상기 바텀 칩 상에 형성된 범프를 더 포함하며, 상기 범프는 솔더 범프, 니켈 범프, 금도금 솔더 범프 및 스터드 범프로 구성된 그룹으로부터 선택되는 어느 하나이고, 5㎛ 이상의 두께 및 30㎛ 이상의 크기를 갖는다.Here, the bottom chip and the top chip are applied to both a center pad type and an edge pad type chip. The anisotropic conductive film is made of an adhesive of epoxy or polyimide with any one of the conductors selected from the group consisting of nickel, gold plated nickel, silver plated nickel and copper, and the conductor has a diameter of 1 to 500 μm. It has a sphere or rectangular shape. Further comprising a bump formed on the bottom chip, the bump is any one selected from the group consisting of solder bumps, nickel bumps, gold-plated solder bumps and stud bumps, and has a thickness of 5㎛ or more and a size of 30㎛ or more.
또한, 본 발명은, 인너리드와 아우터리드로 구분되는 리드프레임; 상기 리드프레임의 인너리드 상에 이방성 도전 필름에 의해 페이스 다운 타입으로 부착되면서 본딩패드가 상기 인너리드와 전기적으로 연결된 바텀 칩; 상기 바텀 칩의 후면 상에 접착제에 의해 페이스 업 타입으로 부착된 탑 칩; 상기 탑 칩의 본딩패드와 리드프레임의 인너리드를 전기적으로 연결한 금속 와이어; 및 상기 리드프레임의 인너리드 상에 스택된 바텁 칩 및 탑 칩과 금속 와이어를 포함하는 공간적 영역을 상기 리드프레임의 아우터리드가 노출되도록 밀봉한 봉지제를 포함하는 칩 스택 패키지를 제공한다.In addition, the present invention, the lead frame is divided into inner lead and outer lead; A bottom chip attached to the inner lead of the lead frame by an anisotropic conductive film in a face down type while a bonding pad is electrically connected to the inner lead; A top chip attached in a face up type by an adhesive on a rear surface of the bottom chip; A metal wire electrically connecting a bonding pad of the top chip to an inner lead of the lead frame; And an encapsulant that seals the spatial region including the barb chip and the top chip and the metal wire stacked on the inner lead of the leadframe such that the outer region of the leadframe is exposed.
여기서, 상기 리드프레임의 인너리드는 신속한 열방출이 이루어질 수 있도록 그의 밑면이 봉지제로부터 노출될 수 있다.Here, the inner lead of the lead frame may be exposed from the bottom surface of the encapsulant so that rapid heat dissipation can be achieved.
본 발명에 따르면, 바텀 칩과 기판간을 이방성 도전 필름으로 연결시키기 때문에 센터 패드형의 칩도 용이하게 적용할 수 있으며, 또한, 바텀 칩에 대한 와이어 본딩 공정을 생략할 수 있으므로 공정 상의 어려움도 해결할 수 있고, 게다가, 칩들의 스택 높이를 낮출 수 있으므로 패키지의 전체 높이도 줄일 수 있다.According to the present invention, since the bottom chip and the substrate are connected by an anisotropic conductive film, the center pad type chip can be easily applied, and the wire bonding process for the bottom chip can be omitted. In addition, the stack height of the chips can be lowered, thus reducing the overall height of the package.
(실시예)(Example)
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세하게 설명하도록 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 따른 칩 스택 패키지를 도시한 단면도이다. 도시된 바와 같이, 본 발명의 칩 스택 패키지는 가장자리 패드형의 바텀 칩(24)이 이방성 도전 필름(Anisotropic Conductive Film : 이하, ACF)(23)에 의해 회로패턴(22)을 구비한 기판(21) 상에 페이스 다운 타입(face down type)으로 부착되고, 아울러, 상기 ACF(23)에 의해 그의 본딩패드와 기판(21)의 회로패턴(22)이 전기적으로 연결된 구조를 갖는다.2 is a cross-sectional view illustrating a chip stack package according to an exemplary embodiment of the present invention. As shown, the chip stack package of the present invention is a substrate 21 having a circuit pattern 22 by means of an anisotropic conductive film (ACF) 23 in which an edge pad bottom chip 24 is formed. It is attached to the face down type (face down type), and the bonding pad and the circuit pattern 22 of the substrate 21 is electrically connected by the ACF (23).
그리고, 가장자리 패드형의 탑 칩(26)은 접착제(25)에 의해서 페이스 업 타입(face up type)으로 바텁 칩(24)의 하부면 상에 부착되며, 그의 본딩패드는 와이어 본딩 공정을 통해서 금속 와이어(27)에 의해 기판(21)의 회로패턴(22)과 전기적으로 연결된다.The top pad 26 of the edge pad type is attached on the bottom surface of the bar chips 24 in a face up type by the adhesive 25, and the bonding pads thereof are made of metal through a wire bonding process. The wire 27 is electrically connected to the circuit pattern 22 of the substrate 21.
또한, 스택된 바텀 칩(24)과 탑 칩(26) 및 금속 와이어(27)를 포함한 상기 기판(21)의 상부면은 봉지제(29)에 의해 밀봉된다.In addition, the top surface of the substrate 21 including the stacked bottom chip 24 and the top chip 26 and the metal wire 27 is sealed by the encapsulant 29.
상기에서 ACF(23)는 니켈, 금도금 니켈, 은도금 니켈 또는 구리로 이루어진 전도체 알갱이들이 에폭시 또는 폴리이미드와 같은 접착 물질 내에 분산된 구조이며, 이때, 상기 전도체 알갱이는 대략 1∼500㎛의 직경을 갖는 구(Sphere) 또는 직육면체(Rectangular) 형상을 갖는다.The ACF 23 is a structure in which conductive grains made of nickel, gold-plated nickel, silver-plated nickel, or copper are dispersed in an adhesive material such as epoxy or polyimide, wherein the conductive grains have a diameter of about 1 to 500 μm. It has a spherical or rectangular shape.
이러한 ACF(23)는 그 자체로는 절연성 접착제이지만, 압력이 가해지는 경우, 바텀 칩(24)의 본딩패드와 기판(21)의 회로패턴(22) 사이에 배치된 전도체 알갱이들에 의해 상기 본딩패드와 회로패턴(22)간의 전기적 연결이 이루어진다.This ACF 23 is an insulating adhesive by itself, but when pressure is applied, the bonding is performed by conductor grains disposed between the bonding pad of the bottom chip 24 and the circuit pattern 22 of the substrate 21. Electrical connection is made between the pad and the circuit pattern 22.
이와 같은 본 발명의 칩 스택 패키지는 바텀 칩(24)의 경우 ACF(23)에 의해 기판(21) 상에 부착됨과 동시에 회로패턴(22)과의 전기적 연결이 이루어지므로, 상기 회로패턴(22)과의 전기적 연결을 위해 종래 수행하였던 와이어 본딩 공정을 생략할 수 있으며, 이에 따라, 그에 해당하는 만큼의 제조 공정상의 단순화를 얻을 수 있다.The chip stack package of the present invention is attached to the substrate 21 by the ACF 23 in the case of the bottom chip 24 and the electrical connection with the circuit pattern 22 is made, the circuit pattern 22 The wire bonding process, which has been conventionally performed for the electrical connection with the wires, may be omitted, and as a result, a simplification in the manufacturing process may be obtained.
또한, 상기 바텀 칩(24)은 ACF(23)에 의해 페이스 다운 타입으로 기판(21) 상에 배치되므로 가장자리 패드형은 물론 센터 패드형의 칩 또한 적용 가능하다.In addition, since the bottom chip 24 is disposed on the substrate 21 by the ACF 23 in the face down type, the edge pad type as well as the center pad type chip may be applied.
게다가, 상기 바텀 칩(24)과 탑 칩(26)은 단순히 접착제로(25)에 의해 후면들이 상호 부착되면 되므로, 금속 와이어의 손상을 방지하기 위해 충분히 확보해야했던 간격이 필요치 않으며, 그래서, 패키지 전체로 볼때 그 높이를 줄일 수 있다.In addition, since the bottom chip 24 and the top chip 26 simply need to be attached to each other by the adhesive layer 25, the bottom chip 24 and the top chip 26 need not be sufficiently spaced to prevent damage to the metal wire, so that the package In total, the height can be reduced.
아울러, 상기 ACF(23)는 금속 와이어에 비해 신호 전달 경로가 짧기 때문에, 금속 와이어에 의해 전기적 연결이 이루어지는 종래의 칩 스택 패키지 보다 본 발명의 칩 스택 패키지는 향상된 전기적 특성을 갖는다.In addition, since the ACF 23 has a shorter signal transmission path than the metal wire, the chip stack package of the present invention has improved electrical characteristics than the conventional chip stack package in which electrical connection is made by the metal wire.
이하에서는 전술한 칩 스택 패키지의 제조 공정을 설명하도록 한다.Hereinafter, the manufacturing process of the chip stack package described above will be described.
도 3a 내지 도 3c는 본 발명의 실시예에 따른 칩 스택 패키지 제조 공정을 설명하기 위한 단면도이다. 여기서, 전 공정들은 바람직하게 개별 칩이 아닌 스트립 단위로 진행되지만, 이에 대해서는 도시하지 않는다.3A to 3C are cross-sectional views illustrating a chip stack package manufacturing process according to an exemplary embodiment of the present invention. Here, the whole processes are preferably carried out in strip units, not individual chips, but are not shown.
먼저, 도 3a에 도시된 바와 같이, 회로패턴(22)을 구비한 기판(21)을 마운트 스테이지(30)에 올려 놓은 상태에서 상기 기판(21) 상에 ACF(23)를 부착시키고, 그런다음, 마운트 헤드(40)의 열과 압력을 이용해서 상기 ACF(23) 상에 본딩패드 형성면이 아래를 향하는 페이스 다운 타입으로 바텁 칩(24)을 부착시키고, 이와 동시에, 기판의 회로패턴(22)과 바텁 칩(24)의 본딩패드간을 전기적으로 연결시킨다.First, as shown in FIG. 3A, the ACF 23 is attached onto the substrate 21 while the substrate 21 having the circuit pattern 22 is placed on the mount stage 30. Using the heat and pressure of the mount head 40, the barb chip 24 is attached to the ACF 23 in a face down type with a bonding pad forming surface facing downward, and at the same time, the circuit pattern 22 of the substrate is attached. And the bonding pads of the bar chips 24 are electrically connected.
다음으로, 도 3b에 도시된 바와 같이, 상기 바텀 칩(24)의 하부면 상에 접착제(25)를 부착시키고, 마운트 헤드를 이용해서 상기 접착제(25) 상에 탑 칩(26)을 본딩패드 형성면이 위를 향하는 페이스트 업 타입으로 부착시킨다. 그런다음, 와이어 본딩 공정을 통해 탑 칩(26)의 본딩패드와 기판(21)의 회로패턴(22)간을 금속 와이어(27)로 연결시킨다.Next, as illustrated in FIG. 3B, an adhesive 25 is attached to the bottom surface of the bottom chip 24, and a bonding pad is bonded to the top chip 26 on the adhesive 25 using a mount head. It is attached by paste up type with the formation surface facing up. Then, a metal wire 27 is connected between the bonding pad of the top chip 26 and the circuit pattern 22 of the substrate 21 through a wire bonding process.
그리고나서, 도 3c에 도시된 바와 같이, 인캡슐레이션(Encapsulation) 공정을 통해 스택된 바텀 칩(24)과 탑 칩(26) 및 금속 와이어(27)를 포함한 기판(21)의 상부면을 봉지제(28)로 밀봉하고, 이어서, 인캡슐레이션 공정을 거진 자재에 대한 스트레스 제거 및 추가적인 화학 반응을 돕기 위해 높은 온도에서 열을 가하는 포스트 몰딩 큐어(post molding cure) 공정을 행한다.Then, as illustrated in FIG. 3C, the top surface of the substrate 21 including the bottom chip 24, the top chip 26, and the metal wires 27 stacked through an encapsulation process is encapsulated. Sealed with 28, then a post molding cure process is applied that heats at high temperatures to aid in stress relief and further chemical reactions to the material undergoing the encapsulation process.
이후, 도시하지는 않았으나, 기판(21)의 하부면에 솔더 볼을 부착한 후, 리플로우(reflow) 및 플럭스 클리닝(flux cleaning) 공정을 수행하고, 그런다음, 스트립 단위로 제조된 칩 스택 패키지들을 소잉 장비를 이용한 싱귤레이션 공정을 행하여 도 2에 도시된 바와 같은 본 발명의 칩 스택 패키지를 완성한다.Subsequently, although not shown, after attaching solder balls to the lower surface of the substrate 21, a reflow and flux cleaning process may be performed, and then chip stack packages manufactured in strip units may be manufactured. A singulation process is performed using a sawing equipment to complete the chip stack package of the present invention as shown in FIG.
도 4 내지 도 6은 본 발명의 다른 실시예들에 따른 칩 스택 패키지를 도시한 단면도이다. 여기서는 전술한 본 발명의 실시예에 따른 칩 스택 패키지와 상이한 부분에 대해서만 설명하도록 하며, 또한, 도면부호는 생략한다.4 to 6 are cross-sectional views illustrating chip stack packages according to other embodiments of the present invention. Here, only portions different from the chip stack package according to the embodiment of the present invention described above will be described, and reference numerals will be omitted.
도 4는 바텀 칩으로서 센터 패드형의 칩이 적용되고, 탑 칩으로서 가장자리 패드형의 칩이 적용된 예이다.4 shows an example in which a center pad type chip is applied as a bottom chip and an edge pad type chip is used as a top chip.
도 5는 바텀 칩 및 탑 칩 모두가 센터 패드형의 칩이 적용된 예이다.5 shows an example in which both a bottom chip and a top chip have a center pad type chip.
도 6은 바텀 칩으로서 가장자리 패드형의 칩이 적용되고, 탑 칩으로서 센터 패드형의 칩이 적용된 예이다.6 shows an example in which an edge pad type chip is applied as a bottom chip and a center pad type chip is used as a top chip.
도 7은 본 발명의 또 다른 실시예에 따른 칩 스택 패키지를 도시한 단면도로서, 도시된 바와 같이, 이 실시예에 따른 칩 스택 패키지는 기판이 아닌 리드프레임(50)을 이용하여 제조된다.7 is a cross-sectional view showing a chip stack package according to another embodiment of the present invention. As shown, the chip stack package according to this embodiment is manufactured using a lead frame 50 rather than a substrate.
즉, 바텀 칩(24)은 인너리드(50a)와 아우터리드(50b)로 구분되는 리드프레임 (50)의 상기 인너리드(50a) 상에 ACF(23)에 의해 부착되고, 그리고, 그의 본딩패드가 인너리드(50a)와 전기적으로 연결된다. 탑 칩(26)은 접착제(25)에 의해 바텀 칩(24)의 후면 상에 부착되고, 그의 본딩패드가 금속 와이어(27)에 의해 상기 인너리드(50a)와 전기적으로 연결된다. 그리고, 상기 인너리드(50a) 상에 스택된 바텁 칩(24) 및 탑 칩(26)과 금속 와이어(27)를 포함하는 공간적 영역을 상기 리드프레임(50)의 아우터리드(50b)가 노출되도록 봉지제(28)로 밀봉된다.That is, the bottom chip 24 is attached by the ACF 23 on the inner lead 50a of the lead frame 50 divided into the inner lead 50a and the outer lead 50b, and the bonding pad thereof. Is electrically connected to the inner lead 50a. The top chip 26 is attached on the rear surface of the bottom chip 24 by an adhesive 25, and a bonding pad thereof is electrically connected to the inner lead 50a by the metal wire 27. In addition, the outer region 50b of the lead frame 50 may be exposed to a spatial area including the bar chips 24 and the top chips 26 and the metal wires 27 stacked on the inner leads 50a. Sealed with encapsulant 28.
또한, 상기 봉지제(28)는, 도 8에 도시된 바와 같이, 인너리드(50a)의 밑면을 노출시키도록 형성될 수 있다. 이 경우, 칩(24, 26)서 발생되는 열의 외부로의 방출이 용이하며, 따라서, 열 발생에 의한 성능 저하를 방지할 수 있다.In addition, the encapsulant 28 may be formed to expose the bottom surface of the inner lead 50a, as shown in FIG. 8. In this case, the heat generated by the chips 24 and 26 can be easily released to the outside, and therefore, the performance degradation due to heat generation can be prevented.
한편, 도시하지는 않았으나, 바텀 칩의 기판 상의 부착시, 상기 바텀 칩의 본딩패드 상에 솔더 범프, 니켈 범프, 금도금 솔더 범프, 또는, 스터드 범프를 형성한 후에 ACF를 이용하여 상기 바텀 칩을 부착시킬 수 있다. 이때, 범프의 두께는 5㎛ 이상으로 하며, 크기는 30㎛ 이상으로 한다.Although not shown, when the bottom chip is attached onto the substrate, the bottom chip may be attached using ACF after forming a solder bump, a nickel bump, a gold plated solder bump, or a stud bump on a bonding pad of the bottom chip. Can be. At this time, the thickness of the bump is 5㎛ or more, the size is 30㎛ or more.
이 경우, 바텀 칩의 본딩패드와 기판 회로패턴간의 전기적 연결은 더욱 신뢰성있게 이룰 수 있다.In this case, the electrical connection between the bottom pad bonding pad and the substrate circuit pattern can be more reliably achieved.
이상에서와 같이, 본 발명은 바텀 칩과 기판간의 전기적 연결을 ACF로 이루기 때문에, 칩 스택시, 가장자리 패드형은 물론 센터 패드형의 칩도 바텀 칩으로 적용 가능하다.As described above, in the present invention, since the electrical connection between the bottom chip and the substrate is made of ACF, when the chip is stacked, not only the edge pad type but also the center pad type chip can be applied as the bottom chip.
또한, 본 발명은 바텀 칩과 기판간의 전기적 연결을 ACF로 이루기 때문에 바텀 칩에 대한 와이어 본딩 공정을 생략할 수 있으며, 이에 따라, 제조 공정 측면에서 단순화를 얻을 수 있다.In addition, in the present invention, since the electrical connection between the bottom chip and the substrate is made of ACF, the wire bonding process for the bottom chip can be omitted, thereby simplifying the manufacturing process.
게다가, 본 발명은 바텀 칩과 기판간의 전기적 연결을 ACF로 이루기 때문에 바텀 칩과 탑 칩간의 간격을 종래의 그것에 비해 줄일 수 있으며, 그래서, 패키지의 전체 높이를 낮출 수 있으므로 박형의 칩 스택 패키지를 제공할 수 있다.In addition, the present invention can reduce the distance between the bottom chip and the top chip compared to the conventional one because the electrical connection between the bottom chip and the substrate is made of ACF, so that the overall height of the package can be lowered, thereby providing a thin chip stack package. can do.
부가해서, 본 발명은 바텀 칩과 기판간의 전기적 연결을 ACF로 이루기 때문에 금속 와이어에 비해 짧은 신호 경로를 제공함으로써 전기적 특성을 향상시킬 수 있다.In addition, the present invention can improve the electrical characteristics by providing a short signal path compared to the metal wire because the electrical connection between the bottom chip and the substrate is made of ACF.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR1020020076177A KR100876876B1 (en) | 2002-12-03 | 2002-12-03 | Chip stack package |
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| KR100300496B1 (en) * | 1999-07-23 | 2001-11-01 | 이수남 | chip size stack package |
| US6437446B1 (en) * | 2000-03-16 | 2002-08-20 | Oki Electric Industry Co., Ltd. | Semiconductor device having first and second chips |
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