KR20040046326A - Input buffer for delay locked loop circuit - Google Patents

Abstract

PURPOSE: An input buffer for a delay locked loop(DLL) circuit is provided to prevent an error generated during a locking of the DLL circuit, by removing glitch of a clock pulse generator input signal using a glitch removal circuit. CONSTITUTION: The device includes a clock buffer(310), glitch removal circuit(320) and clock pulse generator. In operation, a clock buffer(310) stores an external clock signal and its inverted value temporarily, and outputs the stored signal as an internal clock signal according to the enabling of a refresh end and enable signal. A glitch removal circuit(320) removes glitch through a self latch process by receiving the internal clock signal, and then outputs it as the first clock signal. A clock pulse generator(330) generates the second clock signal enabled at an edge of a clock by receiving the first clock signal.

Description

INPUT BUFFER FOR DELAY LOCKED LOOP CIRCUIT}

The present invention relates to an input buffer for a delay locked loop circuit, and more particularly, to an input buffer for a delay locked loop circuit applied to an operation of a memory (DDR / QDR) using a delay locked loop (DLL) circuit. It is about.

In general, a delay locked loop (DLL) is a circuit used in a semiconductor memory device to match an internal clock of a synchronous memory using a clock with an external clock without error. That is, a timing delay occurs when an external clock is used internally. This timing delay is used to control an internal clock to be synchronized with an external clock.

1 is a block diagram illustrating an input buffer for a conventional delay locked loop circuit, and the input buffer for a conventional delay locked loop circuit receives an external clock signal (external CLK) and its inverted value (external CLKB) temporarily. A clock buffer 110 for storing the signal and outputting the stored signal as an internal clock signal according to the activation of the enable signal CKE; And a clock pulse generator 120 that receives the internal clock signal Internal clk and generates a clock input signal CLK that is activated at the edge of the clock, and outputs the clock input signal CLK to a DLL circuit (not shown). It includes.

2A to 2D are exemplary diagrams illustrating an operation of a conventional input buffer for a delay locked loop circuit. As can be seen, the enable signal CKE delayed by the buffer delay of a register is converted into an external clock signal. By coinciding with a specific section, which is the second logical step of High, a glitch occurs in the internal clock signal, and this glitch pulse is not recognized as a clock signal, so that a phase difference of one cycle occurs. DLL has a problem that can not perform the fixing process properly.

SUMMARY OF THE INVENTION The present invention devised to solve the above problems provides an input buffer for a delay locked loop circuit that eliminates glitches in a clock pulse generator input signal by using a glitch cancellation circuit, thereby preventing errors occurring in the fixing of the DLL circuit. The purpose is.

1 is a block diagram showing an input buffer for a conventional delay lock loop circuit;

2A to 2D are exemplary views showing the operation of an input buffer for a conventional delay locked loop circuit.

3 is a block diagram illustrating an input buffer for a delay locked loop circuit according to an embodiment of the present invention;

4 is a block diagram showing a glitch cancellation circuit mounted in an input buffer for a delay locked loop circuit according to an embodiment of the present invention;

5 is a block diagram illustrating a delay unit mounted in an input buffer for a delay locked loop circuit according to an embodiment of the present invention;

6 is a timing diagram illustrating an operation of an input buffer for a delay locked loop circuit according to an embodiment of the present invention;

7 is a block diagram showing a glitch cancellation circuit mounted in an input buffer for a delay locked loop circuit according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

310: clock buffer 320: glitch cancellation circuit

330: Clock Pulse Generator

In order to achieve the above object, the input buffer for a delay locked loop circuit of the present invention receives an external clock signal and its inverted value and temporarily stores the input buffer, and stores the stored signal as an internal clock signal according to the refresh termination and enable signal activation. An output clock buffer; A glitch removal circuit that receives the internal clock signal, removes glitch through a self latching process, and outputs the glitch as a first clock signal; And a clock pulse generator that receives the imaginary first clock signal and generates a second clock signal that is activated at an edge of the clock.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

First, FIG. 3 is a block diagram illustrating an input buffer for a delay locked loop circuit according to an embodiment of the present invention. The input buffer for the delay locked loop circuit of the present invention includes a clock buffer 310 and a glitch removal circuit 320. ) And a clock pulse generator 330.

The clock buffer 310 temporarily receives an external clock signal external CLK and its inverted value, and temporarily stores the internal clock signal, and stores the stored signal according to the refresh termination and the enable signal CKE. It serves to output as a clock signal (Internal clk).

In addition, the glitch removal circuit 320 receives the internal clock signal Internal clk from the clock buffer 310 and removes the glitch through a self-latch process, and then the first clock signal CLK1. As a clock pulse generator 330 to be described later.

On the other hand, the clock pulse generator 330 receives the first clock signal CLK1 from the glitch removal circuit 320 and generates a second clock signal CLK2 that is activated at the edge of the clock, and the second clock. Serves to output the signal CLK2 to a DLL circuit (not shown).

FIG. 4 is a block diagram illustrating a glitch cancellation circuit 320 mounted in an input buffer for a delay locked loop circuit according to an embodiment of the present invention. Same as

The delay unit 410 receives and delays the internal clock signal Internal clk from the clock buffer 310 and outputs the delayed signal to the latch unit 420 to be described later. Here, the delay unit 410 is implemented by including a metal option (Metal option) for determining the number of inverters are connected to the plurality of serially connected inverters and the internal clock signal as shown in FIG. Can be.

In addition, the latch unit 420 latches the internal clock signal (Internal clk) of the clock buffer 310 under the control of the output signal of the delay unit 410, and then outputs to the synchronization unit 430 to be described later. It plays a role. Here, the latch unit 420 will be described in detail as follows.

The first inverter 421 mounted in the latch unit 420 inverts the output signal of the delay unit 410 and then outputs a result value.

In addition, in the second inverter 422 mounted in the latch unit 420, an output signal of the delay unit 410 is a first logic step Low and an output signal of the first inverter 421 is second. In the case of the logic step High, it is activated to invert the internal clock signal Internal clk of the clock buffer 310 and then output the resultant value.

On the other hand, the inverter latch 423 mounted in the latch unit 420, latches the output signal of the second inverter 422 and serves to output to the synchronization unit 430 to be described later.

Meanwhile, the synchronizer 430 receives an output signal of the delay unit 410 and an output signal of the latch unit 420, synchronizes the output signal, and outputs the first clock signal CLK1. . Here, the synchronization unit 430 will be described in detail as follows.

The NAND gate 431 mounted in the synchronization unit 430 receives an output signal of the delay unit 410 and an output signal of the latch unit 420, performs a NAND operation, and then outputs a result value. It plays a role.

In addition, the third inverter 432 mounted in the synchronization unit 430 receives the inverted output signal of the NAND gate 431 and inverts the result signal, and outputs the result as the first clock signal CLK1. Play a role.

6 is a timing diagram illustrating an operation of an input buffer for a delay locked loop circuit according to an embodiment of the present invention. Referring to this, the operation of the input buffer for delay locked loop circuit of the present invention will be described below.

First, the glitch elimination circuit 320 receives an internal clock signal (Internal clk) formed through the clock buffer 310 to perform a self-latch. At this time, if the pulse width of the internal clock signal (Internal clk) is less than a predetermined level, the latch is not made by the control of the output signal of the delay unit 410, the pulse width of the internal clock signal (Internal clk) is a predetermined level In this case, the internal clock signal Internal clk is latched to the inverter latch 423 by controlling the output signal of the delay unit 410. This removes the glitch generated by the deformation due to the enable signal CKE. At this time, the delay amount of the delay unit 410 for removing the glitch may be adjusted by the metal option of FIG. 5.

FIG. 7 is a block diagram illustrating a glitch elimination circuit 320 mounted in an input buffer for a delay locked loop circuit according to another embodiment of the present invention, whereby the latch portion 420 in the glitch elimination circuit 320 is disposed. In the case where the output signal of the delay unit 410 is the first logic step Low and the output signal of the first inverter 421 is the second logic step High, instead of the second inverter 422. A passgate 722 for conducting the internal clock signal Internal clk of the clock buffer 310 may be mounted.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawings shown.

In the present invention, a glitch occurs in an internal clock signal, and this glitch pulse is not recognized as a clock signal, so that a phase difference of one cycle occurs, and the DLL cannot perform a fixing process properly. To solve this, there is an advantage of eliminating the glitch of the clock pulse generator input signal using a glitch rejection circuit, thereby avoiding errors occurring in the fixing of the DLL circuit.

Claims (6)

A clock buffer which receives an external clock signal and its inverted value and temporarily stores the received external clock signal and its inverted value, and outputs the stored signal as an internal clock signal according to activation of the refresh end and enable signals; A glitch removal circuit that receives the internal clock signal, removes glitch through a self latching process, and outputs the glitch as a first clock signal; And A clock pulse generator that receives an imaginary first clock signal and generates a second clock signal that is activated at an edge of the clock. Input buffer for a delay locked loop circuit comprising a. The glitch removal circuit of claim 1, wherein A delay unit which receives the internal clock signal from the clock buffer and delays the delayed output signal; A latch unit for latching and outputting the internal clock signal according to the control of the output signal of the delay unit; A synchronization unit which receives an output signal of the delay unit and an output signal of the latch unit and synchronizes the output signal, and outputs the first clock signal as the first clock signal; Input buffer for a delay locked loop circuit comprising a. The method of claim 2, The delay unit includes a metal option for determining the number of inverters to which the internal clock signal and the plurality of serially connected inverters are connected. And an input buffer for a delay locked loop circuit. The method of claim 2, wherein the latch unit, A first inverter for inverting the output signal of the delay unit; A second inverter activated when the output signal of the delay unit is a first logic stage and the output signal of the first inverter is a second logic stage, inverting the internal clock signal; And Inverter latch for outputting to the synchronizer after latching the output signal of the second inverter Input buffer for a delay locked loop circuit comprising a. The method of claim 2, wherein the synchronization unit, A NAND gate configured to receive an output signal of the delay unit and an output signal of the latch unit to perform a NAND operation; And A third inverter that receives the output signal of the NAND gate, inverts the resultant signal, and outputs the result as the first clock signal; Input buffer for a delay locked loop circuit comprising a. The method of claim 2, wherein the latch unit, A first inverter for inverting the output signal of the delay unit; A pass gate for conducting the internal clock signal when the output signal of the delay unit is a first logic stage and the output signal of the first inverter is a second logic stage; And Inverter latch for outputting to the synchronizer after latching the output signal of the second inverter Input buffer for a delay locked loop circuit comprising a.