KR20040045575A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20040045575A KR20040045575A KR1020020073395A KR20020073395A KR20040045575A KR 20040045575 A KR20040045575 A KR 20040045575A KR 1020020073395 A KR1020020073395 A KR 1020020073395A KR 20020073395 A KR20020073395 A KR 20020073395A KR 20040045575 A KR20040045575 A KR 20040045575A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 239000000203 mixture Substances 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 9
- 238000005121 nitriding Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 6
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 229910052776 Thorium Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- 229910052746 lanthanum Inorganic materials 0.000 claims description 6
- 229910052758 niobium Inorganic materials 0.000 claims description 6
- 229910052712 strontium Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052720 vanadium Inorganic materials 0.000 claims description 6
- 229910052727 yttrium Inorganic materials 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 3
- 239000002356 single layer Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 7
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000000452 restraining effect Effects 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
- 230000035515 penetration Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 고유전막의 게이트 절연막을 적용한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to which a gate insulating film of a high dielectric film is applied.
반도체 소자의 고집적화, 저전력화 및 고성능화에 따라, 게이트 절연막의 두께도 점점 더 감소하고 있으며, 최근에는 전기적 두께가 35Å 이하인 게이트 절연막을 로직 트랜지스터(logic transistor) 및 디램(Dynamic Random Access Memory;DRAM) 등에 적용하고자 하는 연구가 활발히 진행되고 있다. 그러나, 게이트 절연막으로서 일반적으로 사용되는 SiO2나 옥시나이트라이드(oxynitride)는 유전용량이 비교적 낮기 때문에, 두께가 35Å 이하로 감소하게 되면 정터널링(direct tunneling)에 의해 게이트의 누설전류가 커져서 소자의 리프레시(refresh) 및 GOI(gate oxide integrity) 특성 등의 열화와 높은 대기 전류(high standby current) 등의 문제가 발생한다.As the semiconductor devices have higher integration, lower power, and higher performance, the thickness of the gate insulating film is gradually decreasing. Recently, the gate insulating film having an electrical thickness of 35 Å or less is used for logic transistors and dynamic random access memory (DRAM). The research to apply is being actively conducted. However, since SiO 2 or oxynitride, which is generally used as a gate insulating film, has a relatively low dielectric capacity, when the thickness is reduced to 35 kΩ or less, the gate leakage current increases due to direct tunneling. Problems such as deterioration such as refresh and GOI (gate oxide integrity) characteristics and high standby current occur.
이러한 문제를 해결하기 위하여, 게이트 절연막을 유전용량이 높은 고유전막으로 적용하는 방법이 제시되었으나, 고유전막의 경우 P＋ 폴리실리콘 게이트와 N＋ 폴리실리콘 게이트를 포함하는 이중 게이트(dual gate) 적용시 발생되는 P＋ 폴리실리콘 게이트의 B (boron) 이온의 기판으로의 침투(penetration)에 대한 억제능력이 SiO2에 비해 매우 열악하기 때문에, B 이온의 기판으로의 침투로 인해 야기되는 문턱전압(threshold voltage; Vt) 변화(shift) 및 불안정(fluctuation)에 의한 소자특성 저하를 막을 수 없다. 따라서, 최근에는 고유전막을 증착하기 전에 약 10Å 내외의 두께로 SiO2막의 계면산화막을 형성하고, 리모트 플라즈마 질화(Remote Plasma Nitrification; RPN)나 완화 플라즈마 질화(Decoupled Plasma Nitrification; DPN) 처리를 수행하여 계면산화막을 질화시킴으로써 고유전막의 게이트 절연막 적용시 기판으로의 B 이온 침투에 대한 억제능력을 향상시키는 방법에 제시되었다. 그러나, RPN의 경우에는 비교적 고온에서 공정이 이루어지기 때문에 계면산화막의 두께가 증가될 뿐만 아니라 막의 균일성(uniformity)이 열악한 문제가 있는 반면, DPN의 경우에는 비교적 공정이 저온에서 이루어지기 때문에 막의 균일성이 우수하고 계면산화막의 두께 증가가 야기되지 않지만 플라즈마에 의한 손상이 커서 실리콘 기판까지 영향을 미침으로써 소자 특성을 저하시키는 문제가 있다.In order to solve this problem, a method of applying the gate insulating film as a high dielectric film having a high dielectric capacity has been proposed. However, in the case of the high dielectric film, a double gate including a P + polysilicon gate and an N + polysilicon gate is generated. Since the ability of the P + polysilicon gate to inhibit penetration of B (boron) ions into the substrate is very poor compared to SiO 2 , the threshold voltage (Vt) caused by the penetration of B ions into the substrate. ) Deterioration of device characteristics due to shift and fluctuation cannot be prevented. Therefore, in recent years, before depositing a high dielectric film, an interfacial oxide film of a SiO 2 film is formed to a thickness of about 10 GPa and subjected to Remote Plasma Nitrification (RPN) or Decoupled Plasma Nitrification (DPN) treatment. By nitriding an interfacial oxide film, a method of improving the suppression ability of B ion permeation into a substrate when a gate insulating film is applied to a high dielectric film is proposed. However, in the case of RPN, since the process is performed at a relatively high temperature, not only the thickness of the interfacial oxide film is increased but also the film uniformity is poor, whereas in the case of DPN, the film is uniform because the process is performed at a low temperature. Although it has excellent properties and does not cause an increase in the thickness of the interfacial oxide film, there is a problem of deteriorating device characteristics by affecting the silicon substrate due to the large damage caused by plasma.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 고유전막의 게이트 절연막 적용시 계면산화막의 두께증가 및 플라즈마에 의한 기판 손상을 방지함과 동시에 게이트 절연막에 대하여 기판으로의 B 이온 침투에 대한 억제능력을 향상시킬 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and increases the thickness of the interfacial oxide film and damages the substrate by plasma while applying the gate insulating film of the high-k dielectric film, and at the same time prevents the B ion from the gate insulating film to the substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving the ability to suppress penetration.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 필드산화막10 semiconductor substrate 11 field oxide film
12 : 계면산화막 13 : 고유전막12: interfacial oxide film 13: high dielectric film
13A : 질화막13A: nitride film
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판 상에 계면산화막을 형성하는 단계; 계면산화막 상에 고유전막을 형성하는 단계; 및 고유전막의 상부를 소정 두께만큼 DPN 처리로 질화시켜 질화막을 형성하는 단계를 포함하는 반도체 소자의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of forming an interfacial oxide film on a semiconductor substrate; Forming a high dielectric film on the interfacial oxide film; And nitriding the upper portion of the high-k dielectric film by a predetermined thickness to form a nitride film.
여기서, DPN 처리는 플라즈마 소오스 기체로서 N2, NO, N2O, NH3, ND3, NF3또는 이들 기체들의 혼합기체를 사용하여, 100 내지 1000W의 소오스 플라즈마 파워및 0W의 바이어스 플라즈마 파워 하에서, 기판온도를 0 내지 600℃로 조절하고 상기 소오스 기체의 유량을 5 내지 500sccm으로 조절하여 5 내지 500 초 동안 수행한다.Here, the DPN treatment is carried out under a source plasma power of 100 to 1000 W and a bias plasma power of 0 W using N 2 , NO, N 2 O, NH 3 , ND 3 , NF 3 or a mixture of these gases as the plasma source gas. The substrate temperature is adjusted to 0 to 600 ° C. and the flow rate of the source gas is adjusted to 5 to 500 sccm for 5 to 500 seconds.
또한, 계면산화막은 5 내지 15Å의 두께로 SiO2막 또는 SiOxNy막으로 형성하거나, Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, Gd 중 선택되는 하나의 금속을 포함하는 실리케이트막으로 형성하는데, SiOxNy막의 x 및 y는 0.03 내지 3.00의 값을 갖는다.In addition, the interfacial oxide film is formed of a SiO 2 film or a SiO x N y film with a thickness of 5 to 15 GPa, or is selected from Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, and Gd. It is formed of a silicate film containing one metal, wherein x and y of the SiO x N y film have a value of 0.03 to 3.00.
또한, 고유전막은 30 내지 150Å의 두께로 Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, Gd 중 선택되는 하나의 금속을 포함하는 금속산화막 또는 실리케이트막의 단일막으로 형성하거나, 금속산화막의 혼합물 또는 금속산화막이 소정층 만큼 적층된 다층막으로 형성하거나, 실리케이트막의 혼합물 또는 실리케이트막이 소정층 만큼 적층된 다층막으로 형성하거나, 금속산화막과 실리케이트막의 혼합물 또는 금속산화막과 실리케이트막이 소정층 만큼 교대로 적층된 다층막으로 형성한다.In addition, the high dielectric film is a metal oxide film containing one metal selected from Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, Gd to a thickness of 30 to 150Å or It is formed as a single film of silicate film, or it is formed as a multilayer film in which a mixture of metal oxide films or metal oxide films are laminated by a predetermined layer, or is formed as a multilayer film in which a mixture of silicate films or silicate films are laminated by a predetermined layer, or a mixture of metal oxide films and silicate films or metal An oxide film and a silicate film are formed as a multilayer film alternately laminated by a predetermined layer.
또한, 반도체 기판은 Si 기판, Si1-xGex기판, SOI(Silicon On Insulator) 기판, 폴리실리콘 기판, 또는 폴리실리콘-Si1-xGex기판으로 이루어지며, Si1-xGex의 x는 0.1 내지 1.0의 값을 갖는다.Further, the semiconductor substrate is Si substrate, Si 1-x Ge x substrate, SOI (Silicon On Insulator) made of a substrate, a polysilicon substrate or a polysilicon substrate -Si 1-x Ge x, Si 1-x Ge x x has a value between 0.1 and 1.0.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 고유전막을 적용한 반도체 소자의 제조방법을 설명하기 위한 단면도로서, 본 실시예에서는 고유전막을 게이트 절연막에 적용한 경우를 나타낸다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device to which a high dielectric film according to an embodiment of the present invention is applied. In this embodiment, a high dielectric film is applied to a gate insulating film.
도 1a를 참조하면, 반도체 기판(10) 상에 필드산화막(11)을 형성하고, 웰형성을 위한 이온주입 공정 및 채널이온주입 공정 등을 각각 수행하여 웰영역(미도시) 및 채널영역(미도시)을 한정한다. 여기서, 반도체 기판(10)은 Si 기판, Si1-xGex기판, SOI(Silicon On Insulator) 기판, 폴리실리콘 기판, 또는 폴리실리콘-Si1-xGex기판으로 이루어지며, Si1-xGex의 x는 0.1 내지 1.0의 값을 갖는다.Referring to FIG. 1A, a field oxide film 11 is formed on a semiconductor substrate 10, and an ion implantation process and a channel ion implantation process for well formation are performed, respectively, to form a well region (not shown) and a channel region (not shown). H). Here, the semiconductor substrate 10 is made of a Si substrate, a Si 1-x Ge x substrate, a silicon on insulator (SOI) substrate, a polysilicon substrate, or a polysilicon-Si 1-x Ge x substrate, and Si 1-x X of Ge x has a value of 0.1 to 1.0.
도 1b를 참조하면, 기판(10) 전면 상에 5 내지 15Å의 비교적 얇은 두께로 계면산화막(12)을 형성한다. 바람직하게, 계면산화막(12)은 SiO2막 또는 SiOxNy막으로 형성하거나, Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, Gd 중 선택되는 하나의 금속을 포함하는 실리케이트막으로 형성한다. 여기서, SiOxNy막의 x 및 y는 0.03 내지 3.00의 값을 갖는다.Referring to FIG. 1B, an interfacial oxide film 12 is formed on the entire surface of the substrate 10 with a relatively thin thickness of 5 to 15 GPa. Preferably, the interfacial oxide film 12 is formed of a SiO 2 film or a SiO x N y film, or one selected from Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, and Gd. It is formed of a silicate film containing a metal. Here, x and y of the SiO x N y film have a value of 0.03 to 3.00.
도 1c를 참조하면, 계면산화막(12) 상부에 게이트 절연막으로서 고유전막 (13)을 30 내지 150Å의 두께로 형성한다. 바람직하게, 고유전막(13)은 Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, Gd 중 선택되는 하나의 금속을 포함하는 금속산화막 또는 실리케이트막의 단일막으로 형성한다. 또한, 고유전막(13)은 상기 금속산화막의 혼합물 또는 금속산화막이 소정 층만큼 적층된 다층막(multi-layer)으로 형성하거나, 상기 실리케이트막의 혼합물 또는 실리케이트막이 소정 층만큼 적층된 다층막으로 형성할 수 있다. 또한, 고유전막(13)은 금속산화막과 실리케이트막의 혼합물 또는 금속산화막과 실리케이트막이 소정층만큼 교대로 적층된 다층막으로 형성할 수 있다.Referring to FIG. 1C, a high dielectric film 13 is formed on the interfacial oxide film 12 as a gate insulating film with a thickness of 30 to 150 kPa. Preferably, the high dielectric film 13 is formed of a metal oxide film or silicate film containing one metal selected from Hf, Zr, Al, Y, Ce, Ta, Ti, Th, La, Pr, V, Nb, Sr, and Gd. It is formed as a single film. In addition, the high-k dielectric layer 13 may be formed as a multi-layer in which the mixture of the metal oxide film or the metal oxide film is laminated by a predetermined layer, or may be formed as a multilayer film in which the mixture or the silicate film is laminated by the predetermined layer. . In addition, the high dielectric film 13 may be formed of a mixture of a metal oxide film and a silicate film or a multilayer film in which metal oxide films and silicate films are alternately stacked by a predetermined layer.
도 1c를 참조하면, 고유전막(13)의 상부를 소정 두께만큼 질화시켜 질화막(13A)을 형성한다. 바람직하게, 질화는 DPN 처리로 수행하며, DPN 처리는 플라즈마 소오스(source) 기체로서 N2, NO, N2O, NH3, ND3, NF3또는 이들 기체들의 혼합기체를 사용하여, 100 내지 1000W의 소오스 플라즈마 파워 및 0W의 바이어스 플라즈마 파워 하에서, 기판온도를 0 내지 600℃로 조절하고 소오스 기체의 유량을 5 내지 500sccm으로 조절하여 5 내지 500 초 동안 수행한다.Referring to FIG. 1C, a nitride film 13A is formed by nitriding an upper portion of the high dielectric film 13 by a predetermined thickness. Preferably, nitriding is carried out by DPN treatment, which is 100 to 100 using N 2 , NO, N 2 O, NH 3 , ND 3 , NF 3, or a mixture of these gases as a plasma source gas. Under source plasma power of 1000 W and bias plasma power of 0 W, the substrate temperature is adjusted to 0 to 600 ° C. and the flow rate of the source gas is adjusted to 5 to 500 sccm for 5 to 500 seconds.
상기 실시예에 의하면, 계면산화막을 질화처리 하는 대신 게이트 절연막인 고유전막을 DPN 처리하여 질화시킴으로써 듀얼 게이트 형성에 따른 기판으로의 B 이온 침투에 대한 억제능력을 향상시킬 수 있다. 또한, 고유전막의 질화가 DPN 처리에 의해 비교적 저온에서 이루어지기 때문에 막의 균일성이 우수하고 계면산화막의 두께증가가 야기되지 않을 뿐만 아니라 고유전막 상부에서만 DPN 처리가 이루어지기 때문에 플라즈마에 의한 실리콘 손상을 방지할 수 있게 됨으로써, 소자의 특성을 향상시킬 수 있게 된다.According to the above embodiment, instead of nitriding the interfacial oxide film, the high dielectric film serving as the gate insulating film is DPN-treated and nitrided to improve the suppression ability of B ion penetration into the substrate due to the dual gate formation. In addition, since the nitride of the high dielectric film is made at a relatively low temperature by DPN treatment, the film uniformity is excellent and the thickness of the interfacial oxide film is not increased, and since the DPN treatment is performed only on the high dielectric film, silicon damage by plasma is prevented. By being able to prevent, the characteristic of an element can be improved.
한편, 상기 실시예에서는 DPN 처리를 적용한 고유전막을 게이트 절연막에 한정하여 설명하였지만, 캐패시터의 유전막에도 동일하게 적용하여 실시할 수 있다.In the above embodiment, the high dielectric film to which the DPN treatment is applied is limited to the gate insulating film. However, the same can be applied to the dielectric film of the capacitor.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 고유전막의 게이트 절연막 적용시 계면산화막의 두께증가 및 플라즈마에 의한 기판 손상을 방지함과 동시에 게이트 절연막에 대하여 기판으로의 B 이온 침투에 대한 억제능력을 향상시킴으로써 소자의 특성을 향상시킬 수 있다.The present invention described above improves the characteristics of the device by preventing the increase of the thickness of the interfacial oxide film and the damage of the substrate by the plasma when the gate insulating film is applied to the high dielectric film, and the ability to suppress the penetration of B ions into the substrate with respect to the gate insulating film. You can.
Claims (12)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100780645B1 (en) * | 2006-09-28 | 2007-11-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with bulb type recess gate |
| KR100943492B1 (en) * | 2007-12-04 | 2010-02-22 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
| US8673711B2 (en) | 2010-11-22 | 2014-03-18 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device having a high-K gate dielectric layer and semiconductor devices fabricated thereby |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100780645B1 (en) * | 2006-09-28 | 2007-11-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device with bulb type recess gate |
| KR100943492B1 (en) * | 2007-12-04 | 2010-02-22 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
| US8673711B2 (en) | 2010-11-22 | 2014-03-18 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device having a high-K gate dielectric layer and semiconductor devices fabricated thereby |
| US8912611B2 (en) | 2010-11-22 | 2014-12-16 | Samsung Electronics Co., Ltd. | Semiconductor device having a high-K gate dielectric layer |
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