KR20040044766A - A variable array module with serial and parallel architecture - Google Patents

Abstract

PURPOSE: A variable capacitor array module is provided to improve an operation of a capacitor bank by adding switches to unit capacitor cells of an array module capacitor. CONSTITUTION: A variable capacitor array module includes a column/row decoder, a capacitor array module, and a serial/parallel connection selector. The column/row decoder(100) is used for selecting a column and a row of a variable capacitor module. The capacitor array module(200) is formed with unit capacitor cells of nxn number. The serial/parallel connection selector(300) is used for connecting serially or in parallel the unit capacitors selected from the unit capacitor cells of nxn number.

Description

A variable array module with serial and parallel architecture}

The present invention relates to a variable capacitor array module capable of serial / parallel connection, and more particularly, to a row decoder capable of selecting a row of a variable capacitor module and a column decoder and a variable capacitor module capable of selecting a column of a variable capacitor module. Improving the operation of the capacitor bank by adding a switch to each unit capacitor cell of the array module capacitor and the array module capacitor consisting of a series / parallel connection selector capable of connecting each capacitor selected from n × n cells in series / parallel. It is for.

In the past, attempts have been made to design a capacitor circuit having a variable capacitance that has a large capacitance using a small capacitor and that can vary the capacitance by a control logic circuit.

In Korean Patent Laid-Open Publication No. 1998-079060, at least one transistor selectively operated to vary the capacitance of a capacitor charged to a predetermined capacitance by a power supply voltage supplied from a power supply voltage source to achieve the above object. And a current divider for variably classifying a current generated by an input voltage to supply the capacitor and a control circuit for controlling an operation of the at least one transistor to control a current ratio of the current divider. It can be seen that the capacitor variable circuit of the capacitor is already known.

In addition, in the related art, there has been a variable capacitor bank capable of only parallel connection in connecting each unit capacitor cell.

Figure 1 shows the structure of a conventional variable capacitor bank and will be described the operation principle in more detail below.

The conventional variable capacitor bank includes a row decoder and a column decoder, and has a structure of an n × n array having a capacitance c_cell of a unit capacitor cell. The row and column decoders allow the user to select the unit capacitor cells in the range they require, and the capacitors in these selected unit capacitor cells are connected in parallel to determine the module capacitance of the variable capacitor module. The capacitance value is as follows.

c_cell ≤ module capacitance ≤ (n × n) × c_cell

In each unit capacitor cell of the conventional variable capacitor bank, the lower end of the capacitor is directly connected to the ground so that all selected unit capacitor cells are connected in parallel, and the module capacitance is determined according to the number of selected unit capacitor cells. capacitance) changes. For example, assuming that m and n rows of n × n unit capacitor cells are selected by a row decoder and a column decoder to select a cell in a range required by the user, the total module capacitance of the selected capacitor (total module) capacitance) can be obtained as (n × m + l) × c_cell.

However, in the conventional variable capacitor array module as described above, when a capacitor bank having an n × n array structure is implemented by using the conventional technology, each unit capacitor cell is connected only in parallel so that the module capacitance The variable variation of C_cell has a variable region from c_cell to (n × n) × c_cell, in which case the unit capacitor cells cannot be connected in series, so the capacitors for the scale of the minute region for the capacitance below the unit capacitor cell There was a problem that is difficult to implement.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, comprising a row decoder that can select a row of the variable capacitor module and a column decoder and a variable capacitor module that can select the column of the variable capacitor module. By adding a switch to each unit capacitor cell of the variable capacitor array module capacitor and the variable capacitor array module capacitor composed of a series / parallel connection selector capable of series / parallel connection of each selected capacitor among n × n unit capacitor cells. Accordingly, an object of the present invention is to reduce the size of a circuit when designing an entire circuit and expanding a change region of a variable capacitor through an improved structure and performance of a variable capacitor array that can be arbitrarily set when designing an integrated circuit.

1 shows the structure of a conventional capacitor bank.

2 shows a capacitor bank implemented by the present invention.

3 illustrates a circuit configured in each cell of a capacitor module for implementing the present invention.

4 shows a parallel connection capacitor bank implemented by the capacitor bank of the present invention.

Figure 5 shows an embodiment of 3/8 pF when connected in series by the capacitor bank of the present invention.

The above object of the present invention is to series each capacitor selected from a row decoder capable of selecting a row of a variable capacitor module, a column decoder capable of selecting a column of a variable capacitor module, and n × n unit capacitance cells constituting the variable capacitor module. It is achieved by a variable capacitor array module capable of serial and parallel connection consisting of a series / parallel connection selector that can be connected in parallel.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

First, Figure 2 shows a capacitor bank in a novel manner implemented by the present invention.

The capacitor bank according to the present invention includes a row / column decoder 100 capable of selecting a row / column of a variable capacitor module, a capacitor array module 200 composed of n × n unit capacitor cells, and n × constituting a variable capacitor module. It consists of a series / parallel connection selector 300 that can connect each unit capacitor selected from the cells of n in series / parallel.

In the embodiment of the capacitor bank according to the present invention, an 8 × 8 array capacitor array module was used.

The series / parallel selector 300 determines whether each unit capacitor cell of the capacitor module is connected in parallel or in series using a value of 1 bit received from the outside. The operation process will be described in detail below.

The series line selector S [1: 8] of the series / parallel selector 300 is a sum of the unit capacitances of the respective unit capacitances located inside each of the variable array capacitors grouped by the unit capacitance cells. In series with S), the series connection between the columns of unit capacitance cells is determined by the series parallel selector P: S [0: 1]. After the serial connection is determined, the first row and the next columns are separated by the serial row selector S [1: 8], and the serial / parallel connection selector is connected to the serial / parallel selector (P: One end is connected to S) and the first switch selector An [n: n] connected to the switch A of the unit capacitor cell and the switch A of the unit capacitor cell, and the other end is directly The unit capacitor cells having respective series connections are implemented by the second switch selector A [n: n] connected to the sum S of the unit capacitances of the unit capacitor cells of the next row.

The above embodiment can be realized in the same manner as the above implementation operation even in parallel connection. That is, the serial / parallel connection selector is connected to the serial / parallel selector P: S and the same as the number of switches in which the first row and the subsequent rows are separated and parallel-selected by the parallel row selector P [1: 8]. The first switch selector An [n: n] connected to the switch A of the unit capacitor cell alone and the switch A of the unit capacitor cell are connected to one end, and the other end is the unit of the next row. Unit capacitor cells having respective parallel connections are implemented by a second switch selector A [n: n] connected to the sum S of the unit capacitances of the capacitor cells.

Figure 3 shows a circuit configured in each cell of the capacitor module for the implementation of the variable capacitor array module capable of series / parallel connection of the present invention.

The component circuit includes a unit power failure in which all values of the row portion R, the column portion C, the row / column selection portion E for selecting rows and columns, the unit capacitance unit C, and the unit capacitance in series connection are added up. It consists of the sum total part S of a capacitance, the switch A, and ground GND.

Unlike the conventional technology, the configuration circuit has a structure in which one end of unit capacitance can be connected to ground through the switch A without directly connecting to ground (GND). That is, the switch A is connected to the sum S of the unit capacitances of the unit capacitance cells in the next row after the switch is turned off in series connection of the series / parallel connection selector 300.

In the basic operation of the configuration circuit, first, the row part R or the column part C capable of selecting rows and columns is selected by the selection signal of the row / column selection part E, and thus the rows and columns are selected. As a result, the unit capacitances are connected to each other to realize a capacitance having a capacitance value summed up by the sum S of the unit capacitances.

In series connection, the switch A is connected to the sum of the unit capacitances of the next row, so that the unit capacitor cell is connected by the sum of the unit capacitances of the first row and the selected switches A. After being connected in series, it is connected to ground (GND) to achieve fine capacitance below the unit capacitor cell.

Unlike the previous invention, in which the lower end of the capacitor is connected only to the ground, and only parallel connection is possible, the unit capacitor cell of the variable capacitor module is connected to the unit capacitor of the next unit capacitor cell by adding a switch to each unit capacitor cell. One can choose between the sum of capacitance (S) and ground, so that even if each unit capacitor cell is connected in series or in parallel, the capacitance value of each desired unit capacitor cell can be selected to improve the performance of the capacitor bank. .

Figure 4 shows an embodiment of implementing a conventional parallel connection capacitor bank by the capacitor bank of the present invention. By selecting each unit capacitor cell of the capacitor in parallel in the series / parallel selector, it is possible to obtain the module capacitance of the parallel capacitor bank as before. That is, the turn on cell shown in the figure is a capacitance having a capacitance of 21 pF when each unit capacitor cell is connected in parallel and the capacitance of each unit capacitor cell is 1 pF in an array module of 8 × 8 arrays. It is shown.

Figure 5 shows an embodiment when connected in series by the capacitor bank of the present invention.

By selecting each module of the capacitor in series in the series / parallel selector 300, the cells of the capacitor modules in each column are connected in series, wherein the user can select as many as 1 / n × c_cell capacitors among n variable capacitor array modules. Capacitor module of can be selected and used. The range of the variable capacitance of the variable capacitor array module implemented through this is as follows.

1 / n × c_cell ≤ module capacitance ≤ (n × n) × c_cell

Table 1 and Table 2 show the operation of obtaining the specific capacitance value of the variable capacitor array module by the capacitor bank according to the present invention shown in FIG.

In the table, "1" is "high", "0" is "low", "-" is "don't care", P is parallel selection, S is serial selection, and "floating" Denotes “plotting a particular node”, and the capacitance of the unit capacitor cell is 1 pF.

S1 One A1 0 An1 0 C1 One R1 One E1 One P: S P S2 One A2 0 An2 0 C2 One R2 One E2 One S3 One A3 0 An3 0 C3 One R3 One E3 One S4 0 A4 0 An4 0 C4 0 R4 0 E4 0 S5 0 A5 0 An5 0 C5 0 R5 0 E5 floating S6 0 A6 0 An6 0 C6 0 R6 0 E6 floating S7 0 A7 0 An7 0 C7 0 R7 0 E7 floating S8 0 A8 0 An8 0 C8 0 R8 0 E8 floating

Table 1 shows the three unit capacitances of the rows up to the third row and the fourth row of the capacitor bank of the 8 × 8 array module as shown in FIG. 4, that is, the area indicated by the turn on cell in the figure. This parallel connection shows the operation of a 21pF capacitance.

S1 0 A1 One An1 0 C1 - R1 - E1 One P: S S S2 0 A2 One An2 0 C2 - R2 - E2 One S3 0 A3 0 An3 One C3 - R3 - E3 One S4 0 A4 0 An4 0 C4 - R4 - E4 0 S5 0 A5 0 An5 0 C5 - R5 - E5 floating S6 0 A6 0 An6 0 C6 - R6 - E6 floating S7 0 A7 0 An7 0 C7 - R7 - E7 floating S8 0 A8 0 An8 0 C8 - R8 - E8 floating

Table 2 shows an operation of implementing a capacitance of 3/8 pF by connecting each unit capacitor cell in series in the series / parallel selector 300.

Specific implementation operations of Table 2 include switches A [1: 2] on, A [3: 8] off, An [3] on, An [1: 2] off, An [4: 8] is achieved by turning it off, and as a result, as shown in Fig. 5, in the capacitor bank of the array module of the 8 × 8 array, the area indicated by the cells turned on in the figure, that is, the first to third columns. Since only the unit capacitance of is connected in series and connected to ground, fine capacitance of 3/8 pF or less unit capacitor cells summed by the sum S of the unit capacitances of the unit capacitance cells is realized.

The implementation of the capacitance below the unit capacitor cell of 3/8 pF is just one preferred embodiment, and various embodiments may be readily implemented by those skilled in the art.

The implementation of the fine capacitor below the unit capacitor cell according to the embodiment of Table 2 is realized by adding a switch to the unit capacitor cell of the first row and the unit capacitor cell of the nth row in the capacitor bank of the array module of the n × n array. As a result, the capacitance of the unit capacitor cell is changed from 1 / n × c_cell to (n1) / n × c_cell by adding the switching scheme in the implementation of the same number of array modules. Unit capacitor cells may be further implemented.

Accordingly, the variable capacitor array module capable of serial / parallel connection according to the present invention includes a capacitor array module 200 including a row / column decoder 100 capable of selecting rows / columns of the variable capacitor module and n × n unit capacitor cells; When a capacitor bank having an n × n array structure is implemented by configuring a series / parallel connection selector 300 that can connect each unit capacitor selected from n × n cells constituting the variable capacitor module in series / parallel, The connection of each unit capacitor cell can have a structure of series and parallel connection, so that a small circuit change and addition extends the variable range of module capacitance from 1 / n × c_cell to (n × n) × c_cell In the case of using a conventional varactor diode, when the control voltage is used from 0 to 8 volts, the capacitance has a value of 80 pF to 5 pF, but according to the present invention, When the unit capacitor cell is used as 1pF, it is possible to implement a fine capacitor from 80pF to 1 / 8pF, and there is a technical advantage that a variable capacitor module having a wide variable area can be realized compared to the existing structure having a similar circuit area.

Claims (8)

In the implementation of a capacitor bank capable of series and parallel connection, A row / column decoder 100 capable of selecting the row / column of the variable capacitor module; a capacitor array module 200 composed of n × n unit capacitor cells; And Series / parallel connection selector 300 that can connect each unit capacitor selected from n × n unit capacitor cells constituting the variable capacitor module in series / parallel Variable capacitor array module capable of series / parallel connection, characterized in that consisting of. The method of claim 1, When the capacitor array module 200 connects the row portion R, the column portion C, the row / column selection portion E for selecting rows / columns, the unit capacitance unit C, and each unit capacitor cell in series, A variable capacitor array module capable of series / parallel connection, comprising a component circuit comprising a sum S of unit capacitances, a switch A, and a ground GND that add up all values of unit capacitance. The method of claim 2, The switch A is connected to the sum S of the unit capacitances of the unit capacitance cells in the next row when the series / parallel connection selector 300 is connected in series. Variable Capacitor Array Module. The method of claim 3, And the switch (A) is connected to the ground (GND) after being connected to the sum (S) of the unit capacitance. The method of claim 1, The series / parallel connection selector 300 may include a serial group selector S [n: n], a first switch selector An [n: n], and a second switch selector A [n: n]. And a series / parallel selector (P: S). The method of claim 5, The series hang selector S [n: n] is connected to a sum S of each unit capacitance located inside each of the variable array capacitors grouped by the unit capacitance cells. Variable capacitor array module with serial / parallel connection. The method of claim 5, The first switch selector (An [n: n]) is connected in series with the switch (A) of the unit capacitor cell in one stage variable capacitor array module capable of parallel / parallel connection. The method of claim 5, The second switch selector A [n: n] has one end connected to a switch A of the unit capacitor cell, and the other end of the second switch selector A [n: n] is the sum of the unit capacitances of the unit capacitor cells of the next row. Variable capacitor array module capable of connecting in series / parallel, characterized in that the connection.