KR20040041879A - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
KR20040041879A
KR20040041879A KR1020020069978A KR20020069978A KR20040041879A KR 20040041879 A KR20040041879 A KR 20040041879A KR 1020020069978 A KR1020020069978 A KR 1020020069978A KR 20020069978 A KR20020069978 A KR 20020069978A KR 20040041879 A KR20040041879 A KR 20040041879A
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South Korea
Prior art keywords
trench
metal
layer
plating layer
metal plating
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KR1020020069978A
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Korean (ko)
Inventor
이민형
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주식회사 하이닉스반도체
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Priority to KR1020020069978A priority Critical patent/KR20040041879A/en
Publication of KR20040041879A publication Critical patent/KR20040041879A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve the adhesive characteristic with an insulating layer and prevent the generation of defect on the surface of copper by forming a shallow metal layer on a copper layer using a sputtering process. CONSTITUTION: An interlayer dielectric(12) is formed on a semiconductor substrate(10). A trench is formed by carrying out a patterning process on the interlayer dielectric. A metal plating layer(18) is formed for partially filling the trench. Then, the trench is completely filled by forming a metal layer(20) on the metal plating layer. A dielectric layer(22) is formed on the entire surface of the resultant structure. Preferably, the metal layer is made of one selected from a group consisting of aluminum, tantalum, and tungsten. Preferably, the metal plating layer is made of copper.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 구리를 이용한 금속막 상부의 계면특성을 향상할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the interfacial properties of an upper portion of a metal film using copper.

최근의 반도체 소자의 제조 공정에서 저항이 낮은 구리를 금속물질로 많이 사용하게 되었다. 구리를 이용한 금속막을 형성할 경우, 금속막 상부에 다른 금속의 자연 산화막에 비해 조직이 조밀하지 못한 구조의 자연 산화막(CuO)이 형성된다.In the recent semiconductor device manufacturing process, low resistance copper has been used as a metal material. When the metal film using copper is formed, a natural oxide film (CuO) having a structure in which the structure is not dense as compared with the natural oxide film of another metal is formed on the metal film.

조밀하지 못한 자연 산화막으로 인해, 자연 산화막 상에 절연막을 증착하면 자연 산화막과 절연막간의 접착이 잘되지 않게 되는 문제점이 발생한다. 이를 해결하기 위해 350 내지 400℃의 고온에서 NH3을 이용한 플라즈마 처리를 통해 산화막을 환원하여 제거하게 된다. 플라즈마 처리를 통한 자연 산화막 제거시에 구리 표면의 평탄화가 깨지는 결함(힐록(Hillock)이 발생)이 발생하여 후속 공정에서의 패턴 왜곡을 가져오는 문제점이 발생한다.Due to the dense natural oxide film, when the insulating film is deposited on the natural oxide film, a problem arises in that adhesion between the natural oxide film and the insulating film becomes poor. In order to solve this problem, the oxide film is reduced and removed by plasma treatment using NH 3 at a high temperature of 350 to 400 ° C. When the natural oxide film is removed through the plasma treatment, defects in which the planarization of the copper surface is broken (Hillock is generated) occur, which causes pattern distortion in subsequent processes.

따라서, 본 발명은 상기의 문제점을 해결하기 위하여 구리 금속막 상부에 스퍼터링 방법으로 얇은 금속층을 형성함으로서 절연막과의 접착 특성과 구리 표면의 결함발생을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a semiconductor device that can prevent the occurrence of defects on the copper surface and the adhesive properties of the insulating film by forming a thin metal layer on the copper metal film by the sputtering method to solve the above problems. There is a purpose.

도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판12 : 층간 절연막10 semiconductor substrate 12 interlayer insulating film

14 : 트렌치16 : 금속 장벽층14 trench 16: metal barrier layer

18 : 금속 도금층20 : 금속막18 metal plating layer 20 metal film

22 : 다이일렉트릭막22: electric film

본 발명에 따른 반도체 기판 상에 층간 절연막을 증착한 다음 패터닝 공정을실시하여 트렌치를 형성하는 단계와, 상기 트렌치 바닥으로 부터 상기 트렌치의 전체 깊이 보다는 낮게 매립되도록 금속도금층으로 매립하는 단계와, 상기 금속 도금층 상부에 금속막을 형성하여 상기 트렌치를 매립하는 단계 및 전체 구조 상부에 다이일렉트릭 막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.Depositing an interlayer insulating film on a semiconductor substrate according to the present invention and then performing a patterning process to form a trench, and filling the metal plating layer so that the trench is buried below the entire depth of the trench from the bottom of the trench; A method of manufacturing a semiconductor device comprising forming a metal film on an upper portion of a plating layer to fill the trench, and forming a direct film on the entire structure.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도들 이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 1a를 참조하면, 트랜지스터나 커패시터와 같은 반도체 소자(도시되지 않음)를 포함하여 여러 요소가 형성된 반도체 기판(10) 상에 층간 절연막(12)을 증착한 다음 패터닝 공정을 실시하여 트렌치(14)를 형성한다. 전체 구조 상부에 그 단차를 따라 금속 장벽층(16)과 시드층(미도시)을 증착한다. 금속 장벽층(16)은 탄탈륨(Ta), 탄탈륨질화막(TaN), 탄탈륨알루미늄질화막(TaAlN), 탄탈륨실리콘질화막(TaSiN), 탄탈륨실리사이드(TaSi2), 티타늄(Ti), 티타늄질화막(TiN), 티타늄실리콘질화막(TiSiN), 텅스텐질화막(WN), 코발트(Co) 및 코발트실리사이드(CoSi2) 중 적어도 어느 하나를 이용하여 형성한다. 금속 장벽층(16) 상의 전면에 도금을 위한 시드층을 구리를 이용하여 형성한다. 시드층은 구리뿐만 아니라 플래티늄(Platinum), 팔라듐(Palladium), 루비(Rubidium), 스토론튬(Strontium), 로듐(Rhodium) 및 코발트(Cobalt)등의 전이 금속을 이용하여 형성한다. 시드층의 형성 방법은 스퍼터링 등의 물리적 화학 기상증착(Physical Vapor Deposition; PVD)법 또는 화학적 기상증착(Chemical Vapor Deposition; CVD)법을 사용한다.Referring to FIG. 1A, an interlayer insulating film 12 is deposited on a semiconductor substrate 10 having various elements including a semiconductor device (not shown) such as a transistor or a capacitor, and then a patterning process is performed to form a trench 14. To form. A metal barrier layer 16 and seed layer (not shown) are deposited along the steps above the entire structure. The metal barrier layer 16 includes tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi 2 ), titanium (Ti), titanium nitride (TiN), It is formed using at least one of a titanium silicon nitride film (TiSiN), a tungsten nitride film (WN), cobalt (Co) and cobalt silicide (CoSi 2 ). A seed layer for plating is formed on the entire surface of the metal barrier layer 16 using copper. The seed layer is formed using not only copper but also transition metals such as platinum, palladium, rubidium, strontium, rhodium, and cobalt. The seed layer is formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method such as sputtering.

도 1b를 참조하면, 도금공정을 실시하여 트렌치(14) 내부의 일부만을 금속 도금층(18)으로 매립한다. 도금 공정은 전해 도금법 및 무전해 도금법을 사용한다. 구리에 대한 전해 도금은 구리 이온이 포함된 전해용액내로 시드층이 형성된 기판을 넣은 후 이를 음극으로 하여 전압을 인가하면 구리 금속 도금층(18)이 형성된다. 한편 무전해 도금법은 팔라듐처리를 수행한 후 구리 이온을 포함한 도금액에 집어넣으면 구리 금속 도금층(18)이 형성된다. 구리를 이용한 도금공정시, 트랜지(14) 하부에서부터 상부까지 완전히 매립하였을 경우를 100%로 하였을 때, 트랜지(14) 하부로 부터 85 내지 95%만을 구리로 매립하여 금속 도금층(18)을 형성한다.Referring to FIG. 1B, only a part of the inside of the trench 14 is filled with the metal plating layer 18 by performing a plating process. The plating process uses an electrolytic plating method and an electroless plating method. In electrolytic plating of copper, a copper metal plating layer 18 is formed by applying a voltage by placing a substrate having a seed layer into an electrolytic solution containing copper ions and then using this as a cathode. On the other hand, in the electroless plating method, after the palladium treatment, the copper metal plating layer 18 is formed by placing it in a plating solution containing copper ions. In the plating process using copper, when the total filling from the lower part of the trench 14 to the upper part is 100%, only 85 to 95% of the lower part of the transistor 14 is embedded with copper to form the metal plating layer 18. Form.

상술한 바와 같이 트렌치(14) 내부의 85 내지 95%를 금속으로 매립하여 금속 도금층(18)을 형성하기 위해서는 도금 공정의 시간 즉, 전해 용액 또는 도금액 내에 침전되어 있는 기판의 시간을 조절하여 트렌치(14) 내부에 매립되는 구리의 높이를 제어하는 방법과, 시드층을 증착한 다음 식각공정을 실시하여 금속 장벽층(16) 상부의 시드층과 트렌치(14) 상부영역의 시드층을 제거하여 형성하는 방법과, 전체 구조 상부에 금속 도금층(18)을 형성한 다음 식각공정을 실시하여 트렌치(14) 상부영역에 형성된 금속 도금층(18)의 일부를 제거하는 방법을 사용한다.As described above, in order to form the metal plating layer 18 by filling 85 to 95% of the inside of the trench 14 with metal, the time of the plating process, that is, the time of the substrate deposited in the electrolytic solution or the plating liquid is controlled to adjust the trench ( 14) forming a seed layer by depositing a seed layer and then performing an etching process to remove the seed layer on the metal barrier layer 16 and the seed layer on the upper region of the trench 14 by depositing a seed layer. And the metal plating layer 18 is formed on the entire structure and then etched to remove a portion of the metal plating layer 18 formed in the upper region of the trench 14.

구체적으로, 시드층의 식각은 트렌치(14)의 측벽에 형성된 시드층을 100%로 하였을 경우 측벽 상부로부터 5 내지 15%의 시드층을 식각한다. 이로인해 도금공정을 실시하게 되면 시드층이 증착된 부분만 금속 도금층(18)이 형성된다.Specifically, when the seed layer is etched, when the seed layer formed on the sidewall of the trench 14 is 100%, 5 to 15% of the seed layer is etched from the top of the sidewall. As a result, when the plating process is performed, only the portion where the seed layer is deposited is formed with the metal plating layer 18.

한편 금속 도금층(18)의 제거 방법은, 상기 시드층을 식각하지 않고 도금 공정을 실시하여 전체 구조 상부에 금속 도금층(18)을 형성한다. 식각공정을 통해 금속 장벽층(16) 상부의 금속 도금층(18)을 제거하고, 과도식각을 실시하여 트렌치 상부영역의 금속 도금층(18)의 일부를 제거한다. 이때 트렌치 상부의 5 내지 15%의 금속 도금층(18)을 식각함으로서 트렌치 내부의 85 내지 95%를 금속 도금층(18)을 잔류시킨다.In the method of removing the metal plating layer 18, the metal plating layer 18 is formed on the entire structure by performing a plating process without etching the seed layer. The metal plating layer 18 on the metal barrier layer 16 is removed through an etching process, and a portion of the metal plating layer 18 in the upper region of the trench is removed by performing excessive etching. At this time, 5 to 15% of the metal plating layer 18 in the upper portion of the trench is etched to leave 85 to 95% of the metal plating layer 18 in the trench.

도 1c 및 1d를 참조하면, 전도성물질을 이용하여 트렌치(14) 내부를 완전히 매립함으로서 금속 도금층(18) 상부에 금속막(20)을 증착한다. 평탄화 공정을 실시하여 층간 절연막(12) 상부에 형성된 금속장벽층(16)과 금속막(20)을 제거하여 층간 절연막(12)을 노출시킨다. 전체 구조 상부에 다이일렉트릭(Dielectric)막(22)을 증착한다.1C and 1D, a metal film 20 is deposited on the metal plating layer 18 by completely filling the inside of the trench 14 using a conductive material. The planarization process is performed to remove the metal barrier layer 16 and the metal film 20 formed on the interlayer insulating film 12 to expose the interlayer insulating film 12. A dielectric film 22 is deposited over the entire structure.

금속막(20)은 알루미늄(Al), 탄탈륨(Ta) 및 텅스텐(W) 중 적어도 어느 하나를 상온 스퍼터링 등의 CVD방법 또는 PVD방법을 이용하여 형성한다. 이로써 트렌치 상부의 표면에 노출되는 분율은 금속막에 비해 매우 작게 된다. 구리로 구성된 금속 도금층 상에 알루미늄, 탄탈륨 및 텅스텐 중 적어도 어느 하나를 이용한 금속막을 형성하여 치밀한 자연 산화막을 형성할 수 있다. 또한, 구리에 의해 형성된 CuO를 제거하기 위한 트리트먼트(Treatment) 공정을 실시하지 않음으로써 공정의 단순화와 트리트먼트 공정에 의한 문제점들을 방지할 수 있다.The metal film 20 is formed of at least one of aluminum (Al), tantalum (Ta), and tungsten (W) using a CVD method such as normal temperature sputtering or a PVD method. As a result, the fraction exposed to the surface of the trench is very small compared to the metal film. A metal film using at least one of aluminum, tantalum and tungsten may be formed on the metal plating layer made of copper to form a dense natural oxide film. In addition, by not performing a treatment process for removing CuO formed by copper, it is possible to simplify the process and to prevent problems due to the treatment process.

상술한 바와 같이, 본 발명은 구리로 구성된 금속 도금층 상에 알루미늄, 탄탈륨 및 텅스텐 중 적어도 어느 하나를 이용한 금속막을 형성하여 치밀한 자연 산화막을 형성할 수 있다.As described above, the present invention can form a dense natural oxide film by forming a metal film using at least one of aluminum, tantalum and tungsten on the metal plating layer made of copper.

또한, 치밀한 자연 산화막으로 인해 구리로 구성된 금속 도금층과 다이익렉트릭막의 계면특성을 향상할 수 있다.In addition, due to the dense natural oxide film, it is possible to improve the interfacial properties of the metal plating layer made of copper and the multi- profit electric film.

또한, 구리에 의해 형성된 CuO를 제거하기 위한 트리트먼트 공정을 실시하지 않음으로써 공정의 단순화와 트리트먼트 공정에 의한 문제점들을 방지할 수 있다.In addition, by not performing a treatment process for removing CuO formed by copper, it is possible to simplify the process and prevent problems caused by the treatment process.

Claims (7)

(a)반도체 기판 상에 층간 절연막을 증착한 다음 패터닝 공정을 실시하여 트렌치를 형성하는 단계;(a) depositing an interlayer insulating film on the semiconductor substrate and then performing a patterning process to form a trench; (b)상기 트렌치 바닥으로부터 상기 트렌치의 전체 깊이 보다는 낮게 매립되도록 금속 도금층으로 매립하는 단계;(b) embedding the metal plating layer so that the trench is buried below the entire depth of the trench from the bottom of the trench; (c)상기 금속 도금층 상부에 금속막을 형성하여 상기 트렌치를 매립하는 단계; 및(c) filling the trench by forming a metal film on the metal plating layer; And (d)전체 구조 상부에 다이일렉트릭 막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.(d) forming a direct film over the entire structure. 제 1 항에 있어서,The method of claim 1, 상기 금속막은 알루미늄, 탄탈륨 및 텅스텐 중 적어도 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the metal film is formed using at least one of aluminum, tantalum and tungsten. 제 1 항에 있어서,The method of claim 1, 상기 금속 도금층은 구리인 것을 특징으로 하는 반도체 소자의 제조 방법.The metal plating layer is a manufacturing method of a semiconductor device, characterized in that the copper. 제 1 항에 있어서, 상기 (b)단계는,According to claim 1, wherein step (b), 전체 구조 상부에 씨드층을 증착하는 단계;Depositing a seed layer over the entire structure; 상기 층간 절연막 상부와 상기 트렌치 상부 코너부분에 형성된 상기 씨드층을 제거하는 단계; 및Removing the seed layer formed on the interlayer insulating layer and the upper corner portion of the trench; And 전기 도금 공정을 실시하여 상기 트랜치내의 상기 시드층 상에 상기 금속 도금층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Performing an electroplating process to form the metal plating layer on the seed layer in the trench. 제 1 항에 있어서, 상기 (b)단계는,According to claim 1, wherein step (b), 전체 구조 상부에 씨드층을 증착하는 단계;Depositing a seed layer over the entire structure; 전기 도금 공정을 실시하여 상기 금속 도금층을 형성하는 단계; 및Performing an electroplating process to form the metal plating layer; And 상기 층간 절연막 상부와 상기 트렌치 상부영역에 형성된 상기 금속 도금층을 제거하고, 상기 트렌치 내부로 상기 금속 도금층이 리세스 되게 상기 금속 도금층을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.And removing the metal plating layer formed on the interlayer insulating layer and the trench upper region, and etching the metal plating layer to recess the metal plating layer in the trench. 제 1 항에 있어서, 상기 (a)단계와 상기 (b)단계 사이에,The method of claim 1, wherein between step (a) and step (b), 전체 구조 상부에 단차를 따라 금속 장벽층을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.And forming a metal barrier layer on the entire structure along the step. 제 1 항에 있어서, 상기 (c)단계는,The method of claim 1, wherein step (c) comprises: 전체 구조 상부에 상기 금속막을 증착하는 단계; 및Depositing the metal film on the entire structure; And CMP를 이용한 평탄화 공정을 실시하여 상기 층간 절연막 상부의 상기 금속막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.And removing the metal film on the interlayer insulating film by performing a planarization process using CMP.
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