KR20040041459A - Apparatus for Spreading and Modulation of CDMA Communication System - Google Patents

Abstract

PURPOSE: A spreading and modulating device is provided to achieve improved efficiency of use of hardware and allow for ease of reconfiguration of system by permitting the device to perform spreading and modulation functions of a wide variety of CDMA standards. CONSTITUTION: A spreading and modulating device comprises a common Walsh and OVSF(orthogonal variable spreading factor) code generator(22) for generating Walshes and OVSF codes in accordance with CDMA standards; a pseudo noise code generator(24) for generating pseudo noise codes in accordance with CDMA standards same as those of the common Walsh and OVSF code generator; and a circuit unit including a plurality of multiplexers, multipliers, and adders(44 to 46) for selecting input value and calculated value in accordance with CDMA standards and generating simple and plural scrambling codes.

Description

Apparatus for Spreading and Modulation of CDMA Communication System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to spreading and modulators in a code division multiple access (CDMA) communication system, and satisfies various CDMA standards and can be commonly used. The spreading and modulators of CDMA communication systems supporting various standards using code generators and common Walsh and Orthogonal Variable Spreading Factor (OVSF) code generators. to provide.

Conventional CDMA systems mainly support a single standard due to a hardware structure optimized for a single standard.

In addition, a CDMA system supporting multiple standards also had a structure supporting multiple standards by simply combining structures optimized for a single standard. As a result, there is a problem that the hardware area is inefficient and difficult to expand and modify in the future.

As the conventional technology as described above, the hardware structure of spreading and modulation part of WCDMA and IS-95 (similar to CDMA2000) standard is used.

1 shows a forward spreading and modulation process of the IS-95. Input data is spread through Walsh codes and a modulo-2 adder. The spread data is divided into I and Q channels and added through an I channel pilot PN code, a Q channel pilot PN code, and a modulo-2 adder, respectively. The spreading by the Walsh code and the I / Q channel pilot PN code is for distinguishing a user from a base station. The spread data is filtered through a baseband filter and a carrier (cos, sin) value is applied to each I / Q channel. Is added and then transmitted.

The IS-95 includes Walsh code spreading, I / Q channel pilot PN code spreading, and quadrature phase shift keying (QPSK) modulation as described above. In addition, CDMA2000 uses the same spreading code as IS-95, but on the other hand uses a CQPSK (Complex QPSK) modulation scheme.

2 shows a Walsh code generator of the IS-95 for generating a conventional Walsh code, which is composed of a 6-bit register, a 6-bit counter, and an AND and XOR elements. When the Walsh code number (0 to 63) to be generated is input to the 6-bit register, the Walsh code number is ANDed bit by bit and the output value of the counter every clock. The Walsh code is then generated by performing an XOR operation on all of the ANDed values. The Walsh code used in the IS-95 uses only 64-chips, so it uses 6-bit counters and registers.

In general, a shift register and an XOR element are used to generate a random sequence of PN codes.

3 shows a PN code generator used in the IS-95, in which the values of the register are shifted to the right every clock. When shifted, the values are changed by the XOR element between the registers. Since the XOR element simply passes the other input when 0 is input to one input, the XOR element can be selected to enable the desired XOR operation by inserting 1 into the generated polynomial. Therefore, various register values can be obtained by changing the position of the XOR element according to the generation polynomial. The AND device of FIG. 3 can select each XOR device according to the generated polynomial. In addition, every register value is ANDed with the mask value and then modulated with a modulo two adder to output a PN code of one chip.

Here, the IS-95's I-channel pilot PN code generator is a shift register of 15 registers. An XOR element is connected after the 2nd, 6th, 7th, 8th, and 10th registers to update the register value. After spreading by the I / Q channel pilot PN code, the carrier is multiplied by the baseband filter and transmitted.

4 shows a conventional WCDMA forward spreader and modulator, which is comprised of a serial-to-parallel converter, an OVSF code generator, a scrambling code generator, a waveform shaping filter, and a plurality of multipliers and adders.

The operation method of the WCDMA forward spreading and modulator separates input data into I / Q channels through a serial / parallel converter, and multiplies each channel by a multiplier using an OVSF code generated by the OVSF code generator. Next, the multiplied value is multiplied and multiplied by the scrambling code generated by the scrambling code generator. At this time, unlike the IS-95, WCDMA uses complex scrambling, and complexly multiplies I / Q channel data with an I / Q scrambling code. That is, (I data x I scrambling code-Q data x Q scrambling code) is the output of the I channel, and (I data x Q scrambling code + Q data x I scrambling code) is the output of the Q channel. As described above, the scrambled output passes through the waveform shaping filter, and after the carrier wave is multiplied, the I output and the Q output are added to the adder and output.

In WCDMA, a scrambling code is used to distinguish between base stations, and a scrambling code generator as shown in FIG. 5 is used to generate the scrambling code. The scrambling code generator, like the PN code generator of the IS-95, is composed of shift registers and XOR elements for value updating. However, unlike the IS-95's PN code generator, there are two shift registers, and I / Q scrambling codes are generated by XORing the output values of the two shift registers. The value of the register is shifted to the right every clock. At this time, the selected register values are modulated by 2 to generate an output value of the shift register. In addition, the register value is updated by performing an XOR operation on the selected register.

As mentioned above, the spreading and modulator structures of the three CDMA standards are similar. That is, it has a spreading and scrambling structure using pseudo-random code and orthogonal code. In addition, new CDMA communication systems in the future will basically have such a structure. Therefore, since the spreader and the modulator using the PN code generator, the OVSF code generator, the scrambling code generator, and the like are all implemented to be used in a single standard, there is a problem that it is difficult to apply to the current CDMA technology requiring various standards.

Accordingly, an object of the present invention is to provide a spreader and a modulator of a common CDMA communication system capable of applying various CDMA standards based on the above similarity.

In order to achieve the above object, the present invention provides a common Walsh and OVSF code generator for generating different Walsh and OVSF codes according to the CDMA standard, and a standard such as the common Walsh and OVSF code generators. A pseudo noise code generator for generating a pseudo noise code with an input value according to the Walsh and OVSF code generated by the common Walsh and OVSF code generator and the pseudo noise code generator, and a CDMA standard using pseudo noise code and input data. It further features circuitry consisting of multiple multiblackers, multipliers, and multipliers that select calculated values to generate simple and multiple scrambling codes, thereby characterizing the spreading and modulators of a CDMA system capable of applying various CDMA standards.

1 is a diagram showing a forward spreading and modulation structure of a conventional IS-95 (Interim Standard-95).

2 shows a conventional Walsh code generator.

3 illustrates a conventional pseudo noise code generator.

4 is a diagram illustrating a forward spreading and modulation structure of a conventional wideband CDMA (WCDMA).

Figure 5 shows a scrambling code generator of a conventional WCDMA.

6 illustrates an I / Q channel pilot PN code and forward scrambling code generator or long code and reverse scrambling code generator constituting a pseudo noise code generator in accordance with the present invention.

FIG. 7 shows an embodiment of an I-channel pilot PN code generator of IS-95 and CDMA2000 using the pseudo-noise code generator of FIG.

FIG. 8 illustrates an embodiment of a scrambling code generator of WCDMA using the pseudo noise code generator of FIG.

9 illustrates an OVSF code generation tree.

Figure 10 illustrates a circuit capable of generating Walsh codes and OVSF codes in accordance with the present invention.

11 illustrates a common structure for spreading and modulation of a CDMA communication system according to the present invention.

12 illustrates a pseudo noise code generator in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

11, 12: Register 13: XOR element

14 to 17: AND element 20: data mapper

21: serial / parallel conversion unit 22: Walsh and OVSF code generator

23, 28: numerically controlled oscillator 24: pseudo noise (PN) code generator

25, 27: waveform shaping filter 26: coefficient storage of the filter

29 ~ 37,53 ~ 55: Multiplier 38 ~ 43,56,57: Multiplexer

44 ~ 46: Adder

50: I / Q channel pilot PN code and forward scrambling code generator

51: Long Code and Reverse Scrambling Code Generator

52: 2: 1 Decimator

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

Spreaders and modulators of CDMA communication systems for use in the various standards of the present invention include PN code generators and common Walsh and OVSF code generators.

6 shows an I / Q channel pilot PN code and a forward scrambling code generator or a long code and a reverse scrambling code generator constituting a PN code generator according to the present invention. The number and output value determination method can be accommodated. The I / Q channel pilot PN code and forward scrambling code generator or long code and reverse scrambling code generator may include an AND element 15 for selecting an XOR element 13 between a plurality of registers 11 and a register separation for register isolation. The AND element 14 is inserted. In addition, AND elements 16 and 17 and a modulo 2 adder are added for register value update and output value selection.

The feedback signal selection shown in Fig. 6 selects register values to be used for updating the top register 11 via the multiplexer 10 after modulo 2 addition. The mask or Q selection serves to selectively output or mask register values. In addition, the separation signal is a signal for separating the registers to support various register numbers.

In more detail, the register value updating method can be adjusted by the generation polynomial of FIG. 6 and the feedback signal selection. As described above, when the value is updated by placing the XOR element 13 between the registers, the XOR element at a desired position can be selected by inserting values of 1 and 0 into the generated polynomial as in the conventional method. That is, the AND element 15 inputted with zero by the generation polynomial in FIG. 6 causes one input of the connected XOR element 13 to be zero. The XOR element 13 then outputs the other input (the output of register 11) as it is (the input of register 12). This is the same as when there is no XOR element. Conversely, if 1 is input by the generator polynomial, the value is updated by the XOR element. When the value is updated by an XOR element outside the shift register, 0 is input to all of the generator polynomials, and 1 and 0 are input to the feedback signal selection to select the register value to be used for updating the highest register value. The selected values are used by the multiplexer 10 to update the register values after modulo 2 addition.

Next, the AND elements 14 between the registers in Fig. 6 are for determining the number of shift registers used when the number of registers used for each standard is different. When the register separation signal becomes 0, the value is not transferred between the two connected registers 11 and 12, and the other input signal of the XOR element 13 is output as it is. This allows you to separate between connected registers.

Finally, the output value can be selected with a mask or Q selection signal. If 0 is input to the AND element 17 connected to the mask or Q selection, the effect of not selecting the value of the connected resistor 11 is obtained. This is a modulo 2 addition that is affected only by the number of 1s and does not affect the final output value, PN code or Q. Therefore, the value of the register can be masked or selected for output. Also use the value of the lowest register for the other output I.

7 and 8 show the WCDMA forward scrambling code (one of a pair of shift registers) used in the PN code generator according to the present invention described in FIG. 6 and the I-channel pilot PN code of IS-95 (CDMA2000). An operating circuit for the following is shown. In order to update the highest register value, in FIG. 6, all register values can be selected. In FIG. 7 and FIG. 8, this is simplified, and only the part used for generating the scrambling code of WCDMA is modulated through a modulo 2 addition (XOR element). To be entered. The thick lines in Fig. 7 and Fig. 8 show portions used in the case of IS-95 (CDMA2000) and WCDMA, respectively.

FIG. 7 illustrates a case of using the I-channel pilot PN code generator of the IS-95 (CDMA2000) according to the present invention. In the generated polynomial, all 1s are inputted so that the register value is updated by XOR between registers. Also, enter 0 for the isolated signal so that only 15 registers are used. For mask or Q selection, enter 0 in the most significant 3 bits so that only 15 bits are used to determine the output value. The final output will be the value of the PN code or Q signal.

FIG. 8 illustrates the portion of WCDMA used as the forward scrambling code generator of FIG. 6, in which all of the 18 registers are input by inputting all zeros to the generated polynomial so that XOR between registers is not used and inputting one for the separation signal. use. Register value updating occurs by adding the selected register to the module 2 and entering the top register through the multiplexer. The output is a modulated signal plus the register value selected by the mask or Q select signal and the value I of the lowest register. Finally, the output is a PN code or Q and I.

Next, a description will be given when the PN code generator according to the present invention is applied to all PN code generators used for IS-95 (CDMA2000) and WCDMA. First, WCDMA's forward scrambling code generator uses a pair of 18 registers, and IS-95 (CDMA2000) uses 15 registers for each of the I and Q channel pilot PN code generators. Therefore, it is efficient to combine the two. This case is shown in FIG. In this case, in the case of WCDMA, the final Q value is obtained by adding two PN codes or Q signals of two shift registers to a module and the two I signals are added two modules to a final I value. Next, the WCDMA reverse scrambling code generator uses a pair of 25 registers and the IS-95 (CDMA2000) long code generator uses 40 registers. Therefore, combine the two. In this case, the circuit for separation is inserted in the 25th and 40th registers, and the XOR element is inserted in accordance with the long code XOR element position. In order to obtain the output value in the case of WCDMA, the 25th and lowest register values are added to the module to obtain the I signal, and the Q signal is obtained by modulating the values of the selected registers into the module 2.

Thus, the IS-95 (CDMA2000) and WCDMA pseudo-noise code generators can be switched to each other by giving only the parameters of the generation polynomial, the separation signal, and the Q selection. In other words, by changing only the parameters based on common hardware, it can serve as various pseudo noise code generators not only in the aforementioned CDMA but also in future CDMA communication systems.

Next, a common Walsh and OVSF code generator according to the present invention will be described. WCDMA uses OVSF code, which is generated the same way as Walsh code. However, the OVSF code has a different sequence of Walsh codes and the order of the rows, which can be achieved by bit reverse of the code number. In addition, the OVSF code requires a code having a variable length depending on the transmission data rate.

Figure 9 shows the generation of the OVSF code, two lower codes are generated from one higher code, the first code generated is repeated the upper code twice and the second code is repeated and inverted the upper code once This is the code you repeated once. Thus, the longest code contains all of the parent code. Therefore, if you generate the longest code and cut it to the proper length, you can generate all the higher codes.

Next, FIG. 10 illustrates a common Walsh and OVSF code generator based on the present invention based on the code generation process. A shifter and a bit reverse are added to the basic structure of the conventional Walsh code generator shown in FIG. The counter is a counter with a reset function after counting by a spreading factor (SF). In FIG. 10, n represents the number of bits and may represent 2 ⁿ code numbers.

In more detail, as input, the shifter receives the SF and code number to generate the longest (lowest) code number. When the input code number is shifted to the left of n-log ₂ SF, the smallest code number among the lowest codes belonging to the input code is generated. Using this code number, the latter part can generate code with the same structure as a conventional OVSF code generator. After the code number is selected, the counter continues to give the value of 2 ⁿ chips. The counter resets after counting the number of SFs. So only the code you want is repeated. When used as a Walsh code generator, it is bit reversed and the rest is the same as when generating OVSF code. In this way, Walsh codes and OVSF codes of various lengths can be generated.

N = 9 when used as a common Walsh and OVSF code generator for IS-95 (CDMA2000) and WCDMA. This is because in the case of WCDMA, the 512 (2 ⁹ ) chip is the longest code. In future CDMA communication systems, various codes can be generated by selecting n appropriately according to the code length used.

11 shows a spreader and a modulator of a CDMA communication system using the PN code generator of FIG. 6 and the Walsh and OVSF code generators of FIG. 10. The basic structure includes data mapper, serial / parallel conversion, spreading, and scrambling. , Waveform shaping, and quadrature modulation. In more detail, the spreading and modulator of the present invention includes Walsh and OVSF code generators 22 and PN code generators 24, which are used to select values to use between input binary data and Walsh codes to be used instead of input data. A multiplexer 38, a first multiplier 29 for multiplying a value selected by the first multiplexer, and a long code generated by the PN code generator, an output value of the first multiplier 29, and a first multiplexer 38 The second multiplexer 39 for selecting among the selection values of the &quot;), the data mapper 20 for converting the input data selected by the second multiplexer 39 into a real value, and the data mapper 20 converted by the data mapper 20. The Walsh and OVSF codes and I generated by the Walsh and OVSF code generators 22 and controlled by the serial / parallel converter 21 and the numerically controlled oscillator 23 for parallelizing real values into I / Q data. Multiply your data A third multiplier 30 for spreading by multiplying with the second multiplier 31 for spreading and Q data, a third multiplexer 41 for selecting among I data not multiplied with I data multiplied by the Walsh code, and A fourth multiplexer 40 for selecting among Q data multiplied by a Walsh code and Q data not multiplied, and an I code generated by the PN code generator 24 controlled by the numerically controlled oscillator 23 and the first Fourth and fifth multipliers 32 and 33 for multiplying the value output from the three multiplexer 41, the Q code generated by the PN code generator 24 and the value output from the fourth multiplexer 40 A sixth and seventh multipliers 34 and 35 for multiplication, a value multiplied by the fifth multiplier 33 and a value multiplied by the sixth multiplier 34, and a first adder 44 for complex scrambling, Further, the value multiplied by the fourth multiplier 32 and the value multiplied by the seventh multiplier 35 are further added. A second adder 45 for complex scrambling, and a fifth multiplexer for selecting between an I code and a simple scrambled value through the fourth multiplier 33 and a complex scrambled value through the first adder 44 (43), a sixth multiplexer 42 for selecting among the Q code, the simple scrambled value, and the complex scrambled case through the Q code and the sixth multiplier 34, and the fifth and sixth multiplexers The first and second waveform filters 25 and 27 for shaping the waveform through the filter coefficients generated by the filter counter 26 and the values filtered through the waveform filters 25 and 27. Eighth and ninth multipliers 37 and 38 for multiplying the carriers cos (wt) and -sin (wt) of the numerically controlled oscillator 28, and outputs by adding the values multiplied by the eighth and ninth multipliers. And a third adder 46 for transmission.

Compared with the spreading and modulator of Figs. 1 and 4, the scrambling code or PN code in the above structure of the present invention can be selected and multiplied according to a standard, and complex scrambling can be performed or not. The multiplexer was used for this. This allows various functions by changing the path of data while leaving the operator itself the same. Filters and oscillators also feature filters with variable coefficients and numerically controlled oscillators to meet various standards.

As used in each standard, first multiplier 29, which multiplies long codes, is used for forward spreading and modulation of IS-95 and CDMA2000. In the case of WCDMA, the second multiplexer 39 makes it possible to use signals that are not multiplied by the long code.

In the reverse direction of IS-95, the Walsh code is output instead of the Walsh code. That is, the input data is input to the Walsh and OVSF code generators, and use corresponding Walsh code outputs as data. It is input by the first multiplexer 38 in place of the original input data. Then, the third and fourth multiplexers 40 and 41 are not used to multiply the Walsh codes.

In addition, CDMA2000 and WCDMA use complex scrambling and IS-95 uses simple scrambling. The fifth and sixth multiplexers 42 and 43 are used to select this. The fifth and sixth multiplexers 42 and 43 receive two inputs, one of which is complex scrambled data (outputs of the first adder 44 and the second adder 45), and one of the I / Q channels. The data is scrambled respectively. The fifth and sixth multiplexers 42 and 43 select them according to the standard.

The pseudo noise code generator used in the spreading and modulator of a CDMA system for applying various standards according to the present invention as described above is used for all codes used (forward scrambling code, reverse scrambling code, long code, I / Q channel). Pilot PN code).

Fig. 12 shows the PN code generator used in Fig. 11, which shows the long code and reverse scrambling code generator 51 for generating the long code of IS-95 and CDMA2000 and the reverse scrambling code of WCDMA, and the IS-95 and CDMA2000. An I / Q channel pilot PN code and a forward scrambling code generator 50 for generating an I / Q channel pilot PN code and a WCDMA forward scrambling code, the I / Q channel pilot PN code and a forward scrambling code generator A first multiplier 53 and a second multiplier 54 for multiplying the I and Q outputs generated at 50 by the long code generated by the long code and the reverse scrambling code generator 51, and by the multiplier 53 A first multiplexer 56 for alternately outputting the I code from among the multiplied value and the I output generated by the long code and the reverse scrambling code generator 51 and the value multiplied by the multiplier 54 And a second multiplexer 57 for selecting among the Q outputs generated by the reverse scrambling code generator 51 and a 2: 1 decimator for executing the 2: 1 decimation of the value selected by the second multiplexer 57. And a third multiplier 55 for multiplying the 2: 1 decimated value by the I code and outputting the Q code.

When the three standards are in the forward direction, the output codes I and Q of the I / Q channel pilot PN code and the forward scrambling code generator 50 become the I code and the Q code of FIG.

In the reverse direction of CDMA2000, the Q-channel is decimated by the 2: 1 decimator 52 after multiplying the output by the long code. This value is then multiplied by the I channel value +1 -1 +1 -1 ... repeated code to generate a Q code. The I code is a signal multiplied by the long code of the I output.

In the reverse direction of WCDMA, the output of the reverse scrambling code is selected by the multiplexers 56 and 57, and the Q channel performs 2: 1 decimation 52 on this signal. This value is then multiplied by the I channel value +1 -1 +1 -1 ... repeated code to generate a Q code. I code is I output.

As described above, the present invention can support future CDMA communication systems by adding signal flow control or circuitry in accordance with the standard to a common basic structure.

As described above, the present invention can be efficiently used in a communication system supporting multiple CDMA standards by providing a spreading and modulator that can be commonly used in various standards in a CDMA communication system. That is, it can be used as a structure for reconfiguring a CDMA communication system to support multi-mode, multi-band in a future communication market characterized by coexistence of various standards and convergence between these standards. The present invention is a hardware structure for a portion requiring high-speed processing of a CDMA communication system, and can perform spreading and modulation functions of various CDMA standards through control signals based on common hardware. Therefore, the spreading and modulator of the present invention has the advantage that it can facilitate the reconfiguration of the system with efficient hardware use.

Claims (8)

In the spreading and modulator of a CDMA communication system, A common Walsh and OVSF code generator that generates different Walsh and OVSF codes according to the CDMA standard, A pseudo noise code generator for generating a pseudo noise code to a standard such as the common Walsh and OVSF code generator, Generates simple and multiple scrambling codes by selecting input values and calculation values according to Walsh and OVSF codes generated by the common Walsh and OVSF code generators and pseudo noise code generators, and CDMA standards using pseudo noise codes and input data. Spreader and modulator in CDMA systems that can apply various CDMA standards, including circuitry consisting of multiple multiblacksers, multipliers, and multipliers The method of claim 1, The circuit unit comprises: a first multiplexer for selecting a value to use among input binary data and Walsh codes to be used instead of the input data; A first multiplier for multiplying a value selected by the first multiplexer and a long code generated by the PN code generator; A second multiplexer for selecting between an output value of the first multiplier and a selection value of the first multiplexer, A data mapper for converting input data selected by the second multiplexer into a real value; A serial / parallel conversion unit for converting the real value converted by the data mapper into I / Q data in parallel; A third multiplier controlled by a numerically controlled oscillator and multiplied by a second multiplier and a Q data to multiply and spread Walsh and OVSF codes generated by the Walsh and OVSF code generators, and I data; A third multiplexer for selecting between I data multiplied by Walsh code and I data not multiplied, A fourth multiplexer for selecting among Q data multiplied by the Walsh code and Q data not multiplied; Fourth and fifth multipliers for simple scrambling by controlling the numerically controlled oscillator and multiplying the I code generated by the PN code generator 24 and the value output from the third multiplexer; A sixth and seventh multipliers for multiplying the Q code generated by the PN code generator and a value output from the third multiplexer; A first adder for complex scrambling by adding the value multiplied by the fourth multiplier and the value multiplied by the sixth multiplier, A second adder for complex scrambling by adding the value multiplied by the fifth multiplier and the value multiplied by the seventh multiplier, A fifth multiplexer for selecting among complex scrambled values through the first adder and I code and simple scrambled values through the fourth multiplier, A sixth multiplexer for selecting among the Q code, the simple scrambled value, and the complex scrambled case through the Q code and the sixth multiplier, First and second waveform filters for shaping a waveform through filter coefficients generated by a filter counter, the values selected by the fifth and sixth multiplexers; An eighth and ninth multipliers for multiplying the values filtered through the waveform forming filters with the carriers of the numerically controlled oscillator (cos (wt), -sin (wt)); And a third adder for adding, outputting, and transmitting the multiplied values of the eighth and ninth multipliers. The method of claim 1, Wherein the standard selects an output of a multiplier multiplied by a long code in the second multiplexer when the IS-95 and CDMA2000 are forward-forward and backward-modulated and modulated by the IS-95. The method of claim 1, And if the standard is WCDMA, causing a second multiplexer to select a signal that is not multiplied by a long code. The method of claim 1, In the case of the reverse direction of the IS-95, the input data is input to the Walsh and OVSF code generators and uses corresponding Walsh code outputs as data, and is input by the first multiplexer instead of the original input data, and the third and the third input signals. 4 spreader and modulator of a CDMA system, characterized in that the multiplexer does not select the outputs of the second and third multipliers. The method of claim 1, The Walsh code and OVSF code generator includes a shift circuit for shifting an input code number to a number of the longest code to support; Circuitry for bit-reversing the input code number upon Walsh code generation; And a counter for performing a reset after counting the input SF value to output codes of various lengths. The method of claim 1, The pseudo noise code generator includes a long code and a reverse scrambling code generator for generating a long code of IS-95 and CDMA2000 and a reverse scrambling code of WCDMA; I / Q channel pilot PN code and forward scrambling code generator for generating I / Q channel pilot PN code of IS-95 and CDMA2000 and forward scrambling code of WCDMA, A first multiplier and a second multiplier for multiplying the I and Q outputs generated by the I / Q channel pilot PN code and the forward scrambling code generator with the long codes generated by the long code and the reverse scrambling code generator; A first multiplexer for alternatively outputting an I code among a value multiplied by the multiplier and an I output generated by a long code and backward scrambling code generator; A second multiplexer for selecting between the value multiplied by the multiplier and the Q output generated by the long code and backward scrambling code generator; 2: 1 decimation for performing a 2: 1 decimation on the value selected by the second multiplexer, And a third multiplier for outputting a Q code by multiplying and multiplying the 2: 1 decimated value by the I code. The method of claim 7, wherein The long code and reverse scrambling code generator or the I / Q channel pilot PN code and the forward scrambling code generator may include a plurality of registers; An AND element inserted between the registers to adjust the number of the plurality of registers to separate the shift registers; Two modulo-2 adders for updating the insert of the most significant register and masking the insertion of the shift register, And a multiplexer for selectively inputting the result of the modulo-adder into a most significant register.