KR20040040150A - Apparatus for controlling current equilibrium in parallel-coupled eletric power devices - Google Patents

Abstract

PURPOSE: A current balance control unit of parallel-connected power devices is provided to distribute uniformly the current to the parallel connected power devices by controlling a current deviation between the parallel-connected power devices. CONSTITUTION: A current balance control unit of parallel-connected power devices includes a first and a second subtracter(31,41), a first and a second amplifier(32,42), a first and a second integrator(33,43), a first and a second RC circuit(34,44), and a first and a second comparator(35,45). The first and the second subtracters(31,41) are used for calculating a current deviation of a first and a second current detection value between a first and a second power device and a load. The first and the second amplifiers(32,42) are used for amplifying the current deviation. The first and the second integrators(33,43) are used for integrating the output signals of the first and the second amplifiers and outputting integration signals. The first and the second RC circuits(34,44) are used for receiving a control pulse from a main control unit. The first and the second RC circuits are connected to positive terminals of the first and the second comparators(35,45). The first and the second comparators(35,45) are used for outputting a first and a second gate control signal to each gate of the first and the second power devices.

Description

Current balancing control device of parallel connected power devices {APPARATUS FOR CONTROLLING CURRENT EQUILIBRIUM IN PARALLEL-COUPLED ELETRIC POWER DEVICES}

The present invention relates to a device for controlling the current deviation of the parallel-connected power devices, the present invention relates to a current balance control device of parallel-connected power devices that can achieve a current balance by properly delaying the gate signal of the power device.

In general, in order to increase a current driving capacity supplied to a load, a plurality of power devices are connected in parallel to a large current power supply and a load, and a plurality of power devices connected in parallel are simultaneously driven to supply a desired amount of current to one load. At this time, the current flowing through each of the devices is a deviation because the characteristics of the plurality of power devices connected in parallel are not the same. The current deviation of the power device may damage the power device or lower the total driving current capacity.

In order to improve the current deviation between the power devices, current balance is controlled, and FIG. 1 is a current balance control circuit diagram of a general parallel power device driving apparatus, and the output current of the first and second power devices 10a and 10b is first. It is sensed by the two current sensors 11a and 11b. The first and second current detectors 12a and 12b detect current from each of the first and second current sensors 11a and 11b and transmit the current to the current balance controller 50. The current balance controller 50 receives the currents CTS1 and CTS2 received from the first and second current detectors 12a and 12b and a control pulse CP having a predetermined width from the main controller 20. A signal for controlling the current deviation is output to the two power devices 10a and 10b.

At this time, the current balance control unit 50 controls the current balance based on the difference between the first current detection signal CTS1 and the second current detection signal CTS2 detected by the first and second current detection units 12a and 12b. Calculate the correction amount for. The correction amount is set to the delay time DT by A / D conversion, and the delay time DT is counted by the high speed pulse generator of the current balance control unit 50.

2 is a time chart of gate signals of the first and second power devices 10a and 10b. The current balance control unit 50 includes a signal time delay circuit, and delays the input signal CS1 of the signal time delay circuit by the number of pulses of the delay time DT when the control pulse CP is a rising edge. (Delayed CS1) is applied to the gates of the first and second power devices.

However, the current balance control unit 50 is complicated by the high speed pulse generator and the counting device, and the delay time is adjusted in units of cycles of the generated pulse.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object thereof is to control the current sharing ratio between power devices to be equal by using an RC circuit and a comparator in order to control the current deviation of the power devices connected in parallel. It is to provide a current balancing control device of the power device driving device connected in parallel.

1 is a current balancing control device of a general parallel connected power device.

2 is a time chart of a gate signal of a conventional parallel-connected power device.

3 is a block diagram of a current balancing control device of a parallel connected power device according to the present invention.

4 is a time chart of a gate signal of a parallel-connected power device according to the present invention.

5 is a flowchart showing the operation of the current balancing control device of the power device connected in parallel in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

30,40: first and second asymmetric signal delay circuit

31,41: 1st, 2nd subtractor

32,42: first and second amplifiers

33,43: first and second integrator

34,44: 1st, 2RC circuit

35,45: 1st and 2nd comparators

50: current balance control

As a means for achieving the above object of the present invention, by using the current detection value (CTS1, CTS2) flowing in the first and second power devices connected in parallel between the large current power supply and the load, and the control pulse (CP) of the main controller, Current balance control device of the parallel connected power devices for controlling the gate current of the first and second power devices

First and second subtractors for calculating a current deviation between a first current detection value CTS1 and a second current detection value CTS2 flowing between the first and second power devices and a load;

First and second amplifiers for amplifying the current deviation values of the first and second subtractors with a predetermined gain;

First and second integrators for outputting integrated signals RF1 and RF2 by integrating the output signals of the first and second amplifiers;

First and second control circuit (CP) is input from the main control unit, the other end of the first and second RC circuit connected to the (+) end of the first and second comparators; And

The positive terminal is inputted with the waveform according to the time constant τ of the first and second RC circuits, and the negative terminal is inputted with the integrated signals RF1 and RF2, so that the gates of the first and second power devices are input. First and second comparators for outputting first and second gate control signals Delayed CS1 and Delayed CS2 as current;

Characterized in having a.

Hereinafter, a current balancing control device of parallel connected power devices will be described in detail with reference to the accompanying drawings. Components having the same configuration and function in the drawings referred to in the present invention will use the same reference numerals.

Referring to the current balance control device of the parallel-connected power device of the present invention with reference to Figure 3, the parallel-connected power device driving device is a parallel between the large current power supply (1), the large current power supply (1) and the load (13) First and second power devices 10a and 10b connected to each other, first and second current sensors 11a and 11b for detecting output currents of the first power devices 10a and 10b, and the first and second currents. And 1.2th current detectors 14a and 14b for detecting current from the sensors 11a and 11b, respectively, and a main controller 20 for outputting a control pulse CP having a predetermined width.

The current balancing control device according to the present invention applied to the parallel connected power device driving device includes a first current detection value CTS1 and a second current detection value flowing between the first and second power devices 10a and 10b and a load. First and second subtractors 31 and 41 for calculating the current deviation of the CTS2, and First and second amplifiers 32 for amplifying the current deviation values of the first and second subtractors 31 and 41 with a predetermined gain. And 42, first and second integrators 33 and 43 for integrating the output signals of the first and second amplifiers 32 and 42 and outputting the integrated signals RF1 and RF2, and one end of the main controller 20, the control pulse (CP) is input, the other end of the first and second RC circuits (34, 44) and (+) end connected to the (+) end of the first and second comparators (35, 45), Waveforms according to time constants τ of the first and second RC circuits 34 and 44 are input, and the integrated signals RF1 and RF2 are input to the negative terminal, and the first and second power devices 102, First and second comparators 35 for outputting the first and second gate control signals Delayed CS1 and Delayed CS2 with the gate current of 10b). , 45).

In the large current power supply 1, power is supplied to the load through the first and second power devices 10a and 10b, and the on / off of the first power device 10a and the second power device 10b is a current. The first gate control signal CS1 and the second gate control signal CS2 which are output signals of the balance controller 50 are controlled. The current supplied to the load 13 through the first and second power devices 10a and 10b is detected by the first and second current sensors 11a and 11b and the first and second current detectors 12a and 12b, respectively. The first and second current detection signals CT1 and CT2 of the first and second current detection units are input to the current balance control unit 50.

The operation according to the structure of the current balance control unit 50 described above will be described with reference to the time chart of FIG. 4 and the flowchart of FIG. 5, wherein the current balance control unit 50 is provided from the first and second current detection units 12a and 12b. Since the first and second current detection signals CT1 and CT2, which are input through the control panel, are controlled in the same process, the first and second current detection signals CT1 and CT2 will be described based on the first current detection signal CT1.

When the first and second current detection signals CT1 and CT2 are input to the first subtractor 31 (S101), the first subtractor 31 calculates a current deviation between the two signals (S102). The output signal of the first subtractor 31 has a value of 0 when the current of the first current detection signal CT1 and the second current detection signal CT2 is the same, and increases when CT1 is greater than CT2. And decreases if CT1 is less than CT2. The current deviation of the first subtractor 31 is input to the first amplifier 32 and amplified with a predetermined gain (S103), and the amplified current deviation is integrated into the integrated signal RF1 by the first integrator 33. (S104), the first asymmetric time delay circuit 30 is input to the negative terminal of the first comparator 35 (S105).

The control pulse CP is input to the first RC circuit 34 from the main controller 20 (S106). The first RC circuit 34 includes a first resistor R1, a first capacitor C1, and a first capacitor. It includes a diode (D1), the first diode (D1) is connected in parallel to the first resistor (R1). As a result, the output signal of the first RC circuit gradually rises to the time constant τ determined by the resistor R and the capacitor C at the time of rising, and rapidly falls by the first diode D1 at the time of falling. As a signal, it is input to the (+) side of the first comparator 35 (S107).

The first comparator 35 compares an input signal of the (+) terminal, which is an output signal of the first RC circuit 34, with an input signal of the (-) terminal, which is an integral signal RF1 of the first integrator 33. do. The time delay principle of the first and second gate control signals CS1 and CS2 of the first comparator 35 is described with reference to the time chart of FIG. 4.

In the first comparator 35, when the input signal of the (+) stage is larger than the input signal of the (-) stage (S108), the first gate whose first time constant (τ) is larger than the first integration signal RF1 The control signal Delayed CS1 is output to the first power device 10a (S109). If the (+) stage input signal of the first comparator 35 is less than or equal to the (−) stage input signal, 0 is output to the first power device 10a (S110). That is, the time at which 0 is output from the first comparator 35 becomes the delay time DT of the gate signal CS1 of the first power device 10a.

Therefore, since the positive input signal of the first comparator 35 has a constant time constant τ according to the characteristics of RC, the larger the first integrated signal RF1 of the negative terminal, the delay time DT becomes larger. Longer The rising time of the first gate control signal Delayed CS1, which is the output signal of the first comparator 35, is delayed by the delay time DT, and the falling time is the same as the control pulse CP.

Since the operation of the second asymmetric time delay circuit 40 is also the same as the first asymmetric time delay circuit 30 described above, the current sharing ratios of the two power devices 11a and 11b are adjusted.

The present invention has the effect of ensuring a more stable system operation and increase the total current drive capacity by controlling the current deviation between the power devices connected in parallel using an RC circuit and a comparator to maintain a constant current share between the two power devices.

Claims (2)

The gate current of the first and second power devices is controlled by using the current detection values CTS1 and CTS2 flowing in the first and second power devices connected in parallel between the large current power supply unit and the load, and the control pulse CP of the main control unit. In the current balance control device of parallel connected power devices First and second subtractors for calculating a current deviation between a first current detection value CTS1 and a second current detection value CTS2 flowing between the first and second power devices and a load; First and second amplifiers for amplifying the current deviation values of the first and second subtractors with a predetermined gain; First and second integrators for outputting integrated signals RF1 and RF2 by integrating the output signals of the first and second amplifiers; First and second control circuit (CP) is input from the main control unit, the other end of the first and second RC circuit connected to the (+) end of the first and second comparators; And The positive terminal is inputted with the waveform according to the time constant τ of the first and second RC circuits, and the negative terminal is inputted with the integrated signals RF1 and RF2, so that the gates of the first and second power devices are input. First and second comparators for outputting first and second gate control signals Delayed CS1 and Delayed CS2 as current; Current balance control device of the power device driving device connected in parallel. The method of claim 1, wherein the first and second comparators First and second resistors R1 and R2, first capacitors C1 and C1, and first diodes D1 and D2, and the first and second diodes D1 and D2 include the twelfth resistor R1. Is connected in parallel to R2, and the time constant (τ) curve gradually increases by the first and second resistors R1 and R2 and the first and second capacitors C1 and C2, and controls the main control part at the lower phase. A current balancing control device of a power device driving device connected in parallel, characterized in that the same as the falling time of the pulse (CP).