KR20040038054A - Network interface line card system - Google Patents

Abstract

PURPOSE: A network interface line card system is provided to utilize a network processor with the use of a data link device having a PCI bus interface, thereby maximizing data rate performance between an HDLC controller and the network processor. CONSTITUTION: A PMD(Physical Media Dependent) module(100) comprises as follows. An LIU(Line Interface Unit)/framer(110) converts a data frame. An HDLC controller(120) processes an HDLC function. A CPLD(Complex Programmable Logic Device)(130) connects a local bus of the LIU/framer(110) with a PCI bus. A PCI bridge(140) is connected to a PCI bridge(210) of an IOP(Input Output Processor) module(200) through a connector. The IOP module(200) comprises as follows. A Gigabit Ethernet MAC unit(240) processes a Gigabit Ethernet frame. A network processor(220) processes the data frame transmitted from the HDLC controller(120). An SDRAM(250) stores a program code, program data, and packet data. A host CPU(230) executes a routing protocol or a system management program.

Description

Network interface line card system {NETWORK INTERFACE LINE CARD SYSTEM}

The present invention relates to an apparatus and method for delivering data received from an external line interface within a data communication equipment to a data processing engine and transmitting data from the data processing engine via an external line interface. In particular, the present invention relates to a data processor in which a data processing engine is a network processor including a Peripheral Component Interconnect (PCI) bus interface and a CPU core, and a device of a data link layer connected to an external interface has a PCI bus interface. It can be used efficiently in (e.g. routers). That is, the present invention relates to an apparatus and method for maximizing efficiency in using a universal PCI bus for the connection between a network processor and a data link device, which are data processing engines.

Commonly used network interface line cards with bandwidths such as DS-1 (1.544 Mbps), DS-1E (2.048 Mbps), DS-3 (44.736 Mbps), and DS-3E (32.768 Mbps). This uses a data link device with a PCI bus interface and a general purpose CPU that can be connected to the PCI bus. This is because the PCI bus is a standardized bus structure, so many devices support it and can be purchased at low cost. However, this method has the following limitations in implementing a higher bandwidth network interface. First, most commonly used PCI devices operate at 32bit and 33MHz, so the bandwidth of the bus does not exceed 1Gbps. Second, general purpose CPUs cannot handle high-bandwidth network traffic because they are not designed to process network packets. In general, it is known that general-purpose CPUs that are widely used today can handle data of up to several hundred Mbps.

Meanwhile, the most commonly used method to handle high bandwidths of OC-48 (2.5Gbps) and OC-192 (10Gbps) is hardware implemented using ASIC. This method has the advantage of being able to process high-speed data quickly, but the disadvantages are that it is expensive to manufacture and because it is implemented in hardware, it is difficult to flexibly change a function according to a customer's request. Overcoming this drawback, the concept of network processors was created to handle high-bandwidth network data and is now manufactured and sold by many vendors.

Network processors can be processed by software rather than hardware for flexibility, but in order to overcome the processing limitations of general-purpose CPUs, there are several dedicated RISC processors inside the packet processing. This Packet Processing Dedicated Reduced Instruction Set Computer (RISC) processor is called by various names depending on the manufacturer, but the term " -Engine " In addition to the μ-Engine, a general purpose CPU core is often embedded in the chip for other uses. A dedicated high speed bus is used to connect the network processor and the data link device. Dedicated high-speed buses are defined differently for different network processors, but these high-speed buses are becoming more and more standardized.

One problem that arises when implementing a line card using a network processor is that it is sometimes difficult to find a suitable data link device. Typically, manufacturers of network processors manufacture together data link devices that can be used with the network processor. However, not all data link devices are manufactured and sold, so implementing such a line card is not difficult at all. In the case of the present invention, the Intel network processor IXP1200 was used, but there were no devices supporting DS-1, DS-1E, DS-3, and DS-3E that can be connected to the dedicated bus IX-bus. In this case, a common solution is to select one of the data link devices with the same functionality but with different bus structures to design and use bus conversion logic using an FPGA. However, this increases the manufacturing cost of the line card and the development period.

Accordingly, the present invention is to provide a line card system using a network processor using a data link device having a PCI bus interface that many network processors have a general purpose CPU core, and can be easily obtained by focusing on supporting a PCI bus interface.

Although the present invention has limitations that are difficult to use for high-speed data interfaces of hundreds of Mbps or more, it can be effectively used for bandwidths of less than that. DS-1, DS-1E, DS-3, DS-3E line cards used in the present invention Suffice. These line cards are still in demand in the market, so this technology can be fully utilized. In addition, the present invention proposes a method of maximizing data transmission performance between a high-level Data Link Control (HDLC) controller and a network processor.

1 is a diagram showing the configuration of a network interface line card system according to the present invention;

2 is a view showing the flow of data and control signals generated at each stage of reception when receiving frame data in the network interface line card system according to the present invention;

3 is a view showing a structure of a data frame transmitted and received between an HDLC controller and a network processor μ-Engine in a network interface line card system according to the present invention;

4 is a view showing a protocol field value of a frame according to the present invention;

5 is a view showing the flow of data and control signals generated in each step of the transmission when transmitting the frame data in the network interface line card system according to the present invention;

6 is a diagram illustrating a packet flow between a network processor core and a network processor μ-Engine in the network processor 220 according to the present invention.

7 is a diagram illustrating a frame processing method in a network processor μ-Engine.

In order to achieve the above object of the present invention, the present invention provides a network interface line card system for data communication equipment using a network processor having a peripheral component interconnect (PCI) bus and a data link device having a PCI bus. Line Interface Uint (LIU) / Framer to convert DS (Digital Signal) -n standard data frame from electrical signal, HDLC connected to LIU / Framer and responsible for High-level Data Link Control (HDLC) processing The controller 120 is connected to the LIU / framer to connect the local bus of the LIU / framer to the PCI bus, and a PCI bridge connected to the PCI bridge in the input / output processor module through a connector. A Physical Media Dependent (PMD) module, and a connector to the Physical Media Dependent module through a connector. Is a PCI bridge connected to a PCI bridge, a Gigabit Ethernet Media Access Control (MAC), which is a two-layer device that processes Gigabit Ethernet frames, a network processor connected to the Gigabit Ethernet MAC to process data frames from the HDLC controller, and the network processor Synchronous Dynamic Random Access Memory (SDRAM), which stores program code and program data to be executed in the network, packet data from a line interface, and the like, and a host CPU connected to a bus of the PCI bridge and executing routing protocols or system management programs. And an input / output processor (IOP) module.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

The present invention can be effectively used in data communication equipment that satisfies the following several conditions. The conditions are that the data processing engine is a network processor that includes a PCI bus interface and a CPU core, and the device in the data link layer connected to the external interface has a PCI bus interface. The present invention provides an apparatus and method for maximizing efficiency in using a universal PCI bus for connection between a network processor and a data link device, which are data processing engines. Typical network processors have dedicated buses to handle high-speed data, but they also have PCI bus interfaces for system control management. PCI buses cannot handle high-speed data like dedicated buses, but they are sufficient for data processing from a few Mbps to tens of Mbps. There are many low speed data link devices with PCI bus interfaces. In the present invention, since the HDLC controller providing the DS-1, DS-1E, DS-3, and DS-3E standards is used as the data link device, the present technology will be described based on this, but as described above, other link devices and physical devices are described. Applicable to the interface as well.

Meanwhile, in the present invention, a network processor is a packet processor that distinguishes packets according to known attributes such as packet classification, address, and protocol, and packet modification: IP (Internet Protocol) and ATM (Asynchronous Transfer Mode). Modification of packets to follow, Queue / Policy management: Reflecting design policies in queuing and squeezing packets according to specific purposes, and packet forwarding: Sending and receiving data to and from the switch fabric Refers to a programmable integrated circuit capable of performing one or more of packet forwarding and routing functions to a processor, see US Pat. No. 6,404,752.

The term network processor is used in the present invention as defined above, and many semiconductor chip manufacturers sell semiconductor chips supporting the above functions in the market. (Semiconductor chip manufacturers include Intel, IBM, and Motorola.)

1 is a diagram showing the configuration of a network interface line card system according to the present invention.

Referring to FIG. 1, a network interface line card system is divided into a physical media dependent (PMD) module 100 and an input / output processor module (hereinafter referred to as an IOP) module 200. The PMD module 100 is a part dependent on the physical layer interface, and there are different modules according to the physical layer. (Eg, Fast Ethernet PMD, Gigabit Ethernet PMD, DS-1 PMD, DS-3 PMD, OC-3 PMD, OC-12 PMD, etc.) The IOP module 200 performs a common function of processing network data. Thus, one module may be connected to each PMD module and used. DS (Digital Signal) -n PMD module has a line interface unit (LIU) / framer (hereinafter referred to as 'LIU / Framer') that converts DS-n standard data frames from electrical signals coming from external lines. 110). The LIU / Framer 110 is connected to the HDLC controller 120. The HDLC controller 120 is responsible for HDLC processing and is connected to the PCI bridge 140 through the PCI bus. The LIU / Framer 110 is also connected to a Complex Programmable Logic Device (CPLD) 130. The CPLD 130 is responsible for connecting the PCI bus 132 and the local bus 112 of the LIU / Framer 110. The host CPU 230 or the network processor (NP) 220 core in the IOP 200 finds out the state inside the LIU / Framer 110 or modifies necessary information through the CPLD 130.

CPLD 130 is also connected to PCI bridge 140. PCI bridge 140 is coupled to PCI bridge 210 in IOP 200 through a connector. The two PCI bridges 140 and 210 were used because of their electrical characteristics and appear to be functionally transparent to other devices. Several devices are connected to the primary bus 212 of the PCI bridge 210. The network processor 220 processes data frames coming from the HDLC controller 120. The network processor 220 is connected to a Giga-bit Ethernet Media Access Control (MAC) 240. Gigabit Ethernet MAC 240 is a layer 2 device that processes Gigabit Ethernet frames. Synchronous Dynamic Random Access Memory (SDRAM) 250 is connected to the network processor 220, which stores program code and program data to be executed in the network processor, packet data from a line interface, and the like. Another device connected to the primary bus 212 of the PCI bridge 210 is the host CPU 230. The host CPU 230 executes routing protocols or system management programs. The SDRAM 260 is also connected to the host CPU 230, which stores program codes and data to be executed in the host CPU 260.

Hereinafter, the operation of the network interface line card system according to the present invention will be divided into frame reception and frame transmission.

2 is a view showing the flow of data and control signals generated at each stage of reception when receiving frame data in the network interface line card system according to the present invention.

First, the HDLC / PPP frame received from the LIU / Framer 110 is transmitted by the HDLC controller 120 to the SDRAM 250 using a direct memory access (DMA) function. At this time, the PCI bridges 140 and 210 in the middle of the path transmit data without change (①). Specifically, the HDLC frame received by the HDLC controller 120 is later processed by the network processor μ-Engine. The HDLC controller 120 and the network processor μ-Engine have separate descriptor tables for frame processing. This descriptor table contains a lot of information, but the most important is the start address of the frame stored in the SDRAM. If these start addresses can be matched, frames can be shared, so there is no need to copy the same data into memory, which can greatly improve performance. The present invention solves this by informing the HDLC controller 120 of the frame start address required by the network processor μ-Engine. Since the network processor μ-Engine requires the start address to be aligned to 8 bytes for fast processing of the frame, the network processor μ-Engine informs the HDLC controller 120 of the frame start address in consideration of this.

3 is a diagram illustrating a structure of a data frame transmitted and received between an HDLC controller and a network processor μ-Engine in a network interface line card system according to the present invention.

The network processor μ-Engine requires an Ethernet frame type but the HDLC controller 120 provides an HDLC frame. The Ethernet frame and the HDLC frame have different header information. In this case, the problem is the size of the header. Ethernet frames have a 14-byte header, and HDLC frames have a 4-byte header. In the present invention, when the HDLC controller 120 transmits data to iSDRAM, 10 bytes are left at the start address required by the network processor μ-Engine, and then the HDCL frame is written to the memory. The network processor μ-Engine can then erase the 4 bytes of the HDLC frame header and then write the Ethernet header into 14 bytes of space with the 10 bytes left empty.

Referring back to FIG. 2, the HDLC controller 120 transmits an HDLC / PPP frame to the SDRAM 250 using a direct memory access (DMA) function, and then uses an interrupt to indicate that the DMA transfer is completed. (220). Then, the HDLC controller 120 analyzes the PPP header and sends a PPP frame to the PPP process module in the network processor CPU core 220 if it is a control type (③). Meanwhile, the HDLC controller 120 analyzes the PPP header and informs the network processor μ-Engine to process the PPP frame of the SDRAM if it is a data type (③).

That is, the HDLC controller 120 must distinguish whether a frame received and stored in the SDRAM is a control frame or a data frame. This can be seen by looking at the protocol field values in the HDLC header.

4 is a diagram showing protocol field values of a frame according to the present invention. The HDLC controller 120 refers to the protocol field value of the frame as shown in FIG. 4 to discriminate whether it is a control packet or a data packet. After the analysis is completed, the HDLC controller 120 processes the control frame in the Network Processor CPU core and processes the data in the Network Processor μ-Engine. PPP control frames are processed in the Network Processor CPU core. The reason that PPP control frame is processed in Network Processor CPU core is because there are so many ways to process control frame according to its type. These are too complex to write in low-level languages such as assembly language. In the present invention, PPP control frame processing uses software already written in a high level language. On the other hand, the PPP data frame was processed at the Network Processor μ-Engine because it was simple but needed to be processed very fast.

The network processor μ-Engine then takes the PPP frame from the SDRAM and performs IP packet header processing and lookup (④). The network processor μ-Engine forwards the packet to the corresponding output port after the lookup (⑤).

FIG. 5 is a diagram illustrating the flow of data and control signals generated at each stage of transmission when transmitting frame data in the network interface line card system according to the present invention.

First, the network processor μ-Engine receives an Ethernet frame via the Giga MAC 240 (①). Next, the network processor μ-Engine stores the received Ethernet frame in the SDRAM 250 (2). The network processor μ-Engine performs an IP header processing and lookup from the received frame and then notifies the network processor CPU core through an interrupt to process the frame (③). The network processor CPU core tells the HDLC controller to take the frame after the Ethernet frame is made into a PPP / HDLC frame. The HDLC controller 120 takes the PPP / HDLC frame from the SDRAM 5 and passes it to the Framer / LIU 110.

6 is a diagram illustrating a packet flow between a network processor core and a network processor μ-Engine in the network processor 220 according to the present invention.

1 and 6, the network processor 220 includes a network processor core and a network processor μ-Engine. The network processor CPU core is shown as the HDLC controller driver 222. That is, the HDLC controller driver 222 uses three types of queues 270, 272, and 274 to transmit the PPP data frame between the Network Processor CPUcore and the µ-Engine. Each queue (270, 272, 274) has three fields, a packet pointer (270), a packet size (packet size (272) and a channel number (274)) as one item, and the loss of a frame To prevent this, the queue size must be large enough to hold enough items Rx queue 278 is used for data transfer from the HDLC controller driver 222 to the μ-Engine. 278) is always checked and processed when a new frame enters the queue The processed frame enters the Rx Free queue 280 and notifies the HDLC controller driver 222 via an interrupt. ) Releases the memory area where the used HDLC frame is stored for reuse, and the frame from the μ-Engine to the HDLC controller driver 222 enters the TX queue 276. The μ-Engine writes frame information to the TX queue. After via an interrupt that informs the data to be sent to the HDLC controller driver. HDLC controller driver will then process the frame should be turned off so that the memory can be reused later.

7 is a diagram illustrating a frame processing method in a network processor μ-Engine.

Referring to FIG. 7, in the present invention, a network processor having six μ-Engines is used. Each μ-Engine is labeled UE0 to UE5 (300-305). Four threads of UE 1 301 handle 16 ports of DS-1 Rx queues I 311 (the number of ports may vary depending on the case), and each thread round-robins four ports. It operates in the same way as it is responsible for incoming packets for each port. UE 3 303 removes the normal packet from the queue in the DS1 Rx queue II 312 and forwards the packet. In this case, the control packet is sent to the Network Processor CPU core, and in the case of the data packet, the destination address is looked up and then DS1 Tx queues I 315 or Giga Tx queue ( 314). In addition, UE 4 304 enqueues a transmission packet to DS1 Tx queue II 316 by each thread having four ports in DS1 Tx queues I. When the μ-Engine sends a packet to the HDLC driver (written in DS1 Rx free queue, DS1 Tx queue II), it is notified of the interrupt and processed by the HDLC driver.

In the present invention, since the high-level data link control (HDLC) controller providing the DS-1, DS-1E, DS-3, and DS-3E standards is used as the data link device, the present technology will be described based on this. As can be applied to other link devices and physical interfaces.

As described above, the present invention implements a line card using a network processor using a data link device (HDLC controller) having a PCI bus interface. This technology can be used efficiently when there is no dedicated data link device when constructing a line card using a network processor that supports network interfaces from several Mbps to several tens of Mbps. In addition, the method proposed in the present invention can guarantee that the network processor operates as efficiently as possible.

Claims (3)

In the network interface line card system of a data communication equipment using a network processor having a peripheral component interconnect (PCI) bus and a data link device having a PCI bus, Line Interface Unit (FRU) / Framer to convert DS (Digital Signal) -n standard data frames from electrical signals coming from external lines, connected to the LIU / Framer, and processing HDLC (High-level Data Link Control) The HDLC controller 120 which is in charge of the controller, a CPLD (Complex Programmable Logic Device) connected to the LIU / framer to connect the local bus of the LIU / framer to the PCI bus, and a PCI bridge in the I / O processor module through a connector. A Physical Media Dependent (PMD) module containing connected PCI bridges, A PCI bridge connected to the PCI bridge in the physical medium dependent module through the connector, a Gigabit Ethernet MAC (Gigabit Ethernet Media Access Control), which is a two-layer device that processes Gigabit Ethernet frames, and a data frame connected to the Gigabit Ethernet MAC and entered from the HDLC controller. A network processor for processing a network, a synchronous dynamic random access memory (SDRAM) storing program code and program data to be executed in the network processor, packet data from a line interface, and a bus of the PCI bridge, and a routing protocol or system management. A network interface line card system comprising an input output processor (IOP) module including a host CPU on which programs are executed. The network interface line card system of claim 1, wherein a host CPU or a network processor of the input / output processor module detects a state of the LIU / framer or modifies necessary information through the CPLD. The network interface line card system of claim 1, wherein the input / output processor module further comprises an SDRAM connected to a host CPU to store program code and data to be executed in the host CPU.