KR20040034660A - The structure of a new memory and its operating method. - Google Patents

Abstract

PURPOSE: A structure of a semiconductor memory device and its driving method are provided to simplify a production structure by integrating various volatile memories and to improve productivity, and to reduce power consumption and a driving voltage. CONSTITUTION: A memory device is based on a selection transistor for switch constituted on a semiconductor substrate and a ferroelectric capacitor. A structure of a memory unit cell and its driving method are based on the selection transistor for switch and the ferroelectric capacitor. And in a memory block, unit bundle of the unit cell or memory are arranged longitudinally and laterally. Data is recorded in the memory device based on the ferroelectric capacitor, and the stored data is recovered. Signals of several bit line pairs outputting data signals in several cells at the same time in one unit cell or one block are sensed and then one of the signals is selected.

Description

Structure of a new memory and its operating method

The present invention relates to a structure of a semiconductor memory device and a driving method thereof. More specifically, by adding a refresh concept used in a conventional DRAM to a structure and a driving method of a conventional ferroelectric memory, a function is added to secure a data state stored in the memory to ensure stable operation. A patent on memory.

Among the patents of the conventional ferroelectric memory and DRAM (Dynamic RAM), US patent 4873664, the most basic and important patent of the memory to which the ferroelectric capacitor is applied. In US Patent 4809225, a ferroelectric capacitor is added to SRAM to store data in the event of a power failure. The refresh function, which is a data recovery function in DRAM, is conventionally described. It is now widely applied to the products of which are known to the known facts.

A conventional example of a semiconductor memory device in which a memory cell having a ferroelectric capacitor and a select transistor for a switch is arranged in a matrix form as a conventional technique applied to a ferroelectric memory will be described with reference to FIG.

In FIG. 4, four memory cells MC0, MC1, MC2, and MC3 are arranged in a matrix form of two rows and two columns, and the memory cell MC0 includes one ferroelectric capacitor C0 and one switch selection transistor ( T0), and this semiconductor memory device is an operation system composed of one transistor and one capacitor 1T1C.

A pair of the bit line BL ₀ and the bit line BL ₀ , and another pair of the bit line BL ₁ and the bit line BL ₁ , are paired bit lines necessary for reading a signal of a unit cell. The bit line BL for signal transmission among the pair of bit lines BL ₀ and BL ₀ is the drain of the select transistor T0 for switching, and the bit line bar BL ₀ for providing the reference voltage is the bit line. It is connected to the drain of the transistor which comprises the signal reading reference voltage generator circuit.

The word lines WL ₀ and WL ₁ are connected to gates of the select transistors for switching of memory cells arranged in the word line direction, respectively.

The cell plate lines PL ₀ and PL ₁ are connected to the upper electrode of the capacitor in parallel with the word line on the other side of the pair of electrodes of the ferroelectric capacitors of the memory cells arranged in the word line direction.

As shown in Fig. 4, the input terminal of the sense amplifier S / A0 is connected to the bit lines BL ₀ and BL ₀ constituting the bit line pair, and the output terminal of the sense amplifier S / A0 is a pair of data buses. line which is connected to the (DL _0, DL _0), in addition, other sense amplifier (S / A1) is also the bit lines constituting the bit line pairs (BL _1, BL ₁₎ and a pair of data bus lines (DL ₁ , DL ₁ ) is connected in the same manner as S / A0.

In the conventional driving method, a ferroelectric capacitor and a switch selection transistor exist between the bit line and the plane line, and the driving method is used to read, write, and store them in an appropriate order. Their operation is driven in the manner of the waveform diagrams of Figs. In the semiconductor memory device configured as shown in Fig. 4, the operation of writing and reading data will be described.

First, the data write operation to the memory cell MC0 is performed by one ferroelectric capacitor constituting the memory cell to which data is written, one of the polarization states D0 or D1 opposite to each other, as shown in FIG. By generating each. That is, as shown in Figs. 4 and 6, after precharging the corresponding bit line and applying an operation signal voltage to the word line WL ₀ , the switch selection transistor T0 is turned ON and then the cell plane is turned on. An operating signal voltage is applied to the trace line PL ₀ to apply an operating voltage between both ends of the ferroelectric capacitor. At this time, a polarization phenomenon is generated inside the ferroelectric material by the voltage applied between both ends, and this polarization phenomenon sets one of the polarization states D0 or D1 shown in FIG.

At this time, the polarization state of the ferroelectric material is determined according to the polarity of the voltage applied between the both ends of the ferroelectric capacitor. That is, as shown in Fig. 3, when the high voltage is applied to the plane line and the low voltage is applied to the source electrode of the selection transistor, the polarization state of the ferroelectric capacitor CO is as shown in Fig. 9. Upwards, the polarization state on the characteristic curve becomes state 1, and data "D0" is recorded. On the other hand, when the opposite voltage is applied to each of the bit line and the plate line, as shown in Fig. 9, the polarization state of the ferroelectric capacitor C0 is downward and the polarization state on the characteristic curve is state 4, so that the data "D1" is obtained. Is recorded.

Next, the data reading operation will be described.

In order to read the polarization state set by the above write operation, the bit lines BL ₀ and BL _{1 in} Fig. 4 are precharged to a low level or a reference voltage level. Next, as shown in FIG. 7, a high voltage is applied to the word line WL ₀ to turn on the select transistors T0 and T1 for the switch, thereby electrically connecting the bit line and the ferroelectric capacitor to form a ferroelectric capacitor. Prepare to drive. Thereafter, a high voltage is applied to the cell plate CP0 to drive the ferroelectric capacitor.

At this time, depending on the polarization state already present in the ferroelectric capacitor, the polarization reversal occurs inside the ferroelectric or the existing polarization state is maintained as it is. When polarization reversal occurs, the generated charge is relatively large and is read as D1. When polarization reversal does not occur, only negligible charges are generated and are read as D0. In this way, different voltages are generated in the bit lines BL ₀ and BL ₁ as charges having different magnitudes are transferred to the bit lines according to different polarization states, and these voltages are located on opposite sides of the paired bit lines. Compared with the reference voltages of the other bit lines BL ₀ and BL ₁ , the voltage difference is amplified by the sense amplifiers S / A0 and S / A1. The first amplified signal is transmitted to the data bus and then output (DL ₀ and DL ₀ , DL ₁ and DL ₁ ) through the second amplifying stage for signal amplification of the data bus line, wherein the output of the data bus line is high (Hi). ), The stored data is read as "D1" in response to the ferroelectric capacitor being in a downwardly polarized state. On the contrary, if the output of the data bus line is low, the stored data is corresponding to that in which the ferroelectric capacitor is polarized upward. Is read as D0 ". In such a conventional semiconductor memory device, driving is completed by an operation of writing and reading and returning data to its original state as shown in Figs.

At this time, since the amount of charge transferred to the bit line is determined by dividing by the bit line capacity and the ferroelectric capacitor capacity, a low voltage is applied to the word line of the select transistor for switching between T1 and T2 as shown in FIG. Is electrically cut off to minimize the influence of the load by the plate line to maximize the amount of charge transferred to the bit line.

Finally, a storage operation of a memory to which a conventional ferroelectric capacitor is applied will be described. The storage operation generates polarization in the up polarization state D0 or in the down polarization state D1, as shown in Fig. 9, which is the polarization state set in the above write operation, even after the signal applied to both ends of the ferroelectric capacitor is removed. By using the characteristics of the ferroelectric material in which the polarization state is maintained, the polarization generated is maintained as it is, and a method of maintaining the stored data is used. That is, if no voltage is applied externally during the storage period, the polarization state inside the material does not change, and thus the data stored at the time of writing is preserved.

After the primary writing, a low voltage is applied to the corresponding word lines WL ₀ and WL ₁ to electrically cut the switch selection transistors (T0, T1, T2, and T3). It is electrically disconnected from BL ₀ , BL ₁ ). Next, when the plate line is placed at a low voltage, both ends of C0, C1, C2, and C3 of the ferroelectric capacitor are in the "Low" state, respectively, and the power source is removed. At this time, the ferroelectric capacitor becomes the position of polarization state 1 or state 4 in Fig. 9, and remains as data of D0 or D1. That is, D0 remains at 1, which is in an upwardly polarized state, and D1 remains at 4, which is in a downwardly polarized state.

Such a conventional storage method is established assuming that the characteristics of the ferroelectric capacitor applied to the memory are ideal. In the actual product, since the polarization state is not ideal, the stored data is damaged. Therefore, the conventional driving method cannot satisfy all the requirements of the nonvolatile memory. As a result, as shown in Fig. 9, the ferroelectric characteristic changes from curve 1 to curve 2, resulting in the loss of memory function, which is an obstacle to the practical use of the ferroelectric memory.

In the conventional ferroelectric memory device, for the operation of the ferroelectric memory, the read and write functions are operated by the schemes shown in Figs. 5 and 6. Therefore, the data stored in the ferroelectric capacitor is recorded in the state " 1 " and the state D1 in the state " 4 " as shown in Fig. 9, so that each polarization state is preserved even when power is removed from the periphery thereof. Keep the corresponding data. However, if the data is stored in this manner, the stored data may be deteriorated due to the deterioration of the ferroelectric material used for the capacitor and the residual charge remaining at the interface between the upper and lower electrodes and the ferroelectric material forming the structure of the ferroelectric capacitor. Damage. This result in deterioration of the reliability of the ferroelectric memory, which causes problems in memory function.

Due to this deterioration of polarization, as shown in Fig. 9, the characteristic curve of the ferroelectric capacitor is changed from curve 1 to curve 2, so that the reaction process corresponding to DO is performed in the characteristic curves of state 1 and state 2. Altered by the characteristic curves of states 1 'and 2', the signal voltage transmitted to the bit line gradually increases. If the degree becomes severe, the corresponding data voltage transferred to the bit line becomes higher than the reference level, resulting in D0 being read as D1. Conversely, the reaction process corresponding to D1 deteriorates from the characteristic curves of states 4 and 2 to the characteristic curves of states 4 'and 2', so that the corresponding bit line signal voltage is reduced. If the degree becomes severe, the corresponding data voltage transferred to the bit line is lowered below the reference level, resulting in a result of reading D1 to D0 as shown in FIG. That is, the stored data is deteriorated and read as the data which are opposite to each other, thereby causing a malfunction in the function of the memory.

In other words, the characteristic curve of the ferroelectric capacitor occurs due to the deterioration of the ferroelectric capacitor, and the characteristic curve in the characteristic curve following the trajectory of 2 → 1 → 3 → 5 → 4 of characteristic curve 1 of Fig. 9 The trajectory of curve 2 '2' → 1 '→ 4' → 5 'is changed. As a result, the spread of the entire cell array exhibits a change in dispersion as shown in FIG. That is, the dispersion curve 1 deteriorates to the dispersion curve 2, so that the characteristic curve 2 → 1 changes to the characteristic curve 2 '→ 1' as shown in Fig. 9, so that the voltage for D0 changes the read reference voltage. The voltage for D1 will fall below the read reference voltage. As this phenomenon gradually worsens and the number of such cells increases, as shown in Fig. 10, the number of failbits in which D1 data is read into D0 and D0 is read into D1 increases. This phenomenon is called deterioration due to imprint, and is a key phenomenon that degrades the storage function of the ferroelectric.

In the semiconductor device according to the present invention, a data recovery operation which is a driving method which prevents the change from the characteristic curve 1 to the characteristic curve 2 as shown in FIG. 9 by adding the function of FIG. 7. To add. That is, by applying this function periodically or non-periodically while data is stored in the ferroelectric capacitor, the imprint phenomenon is prevented to maintain the storage function more completely. That is, while the data is written and stored in the cell, the drive environment is created so that the written data is not damaged by the imprint phenomenon through the function of automatically recovering or reading and rewriting data at regular intervals. These operating conditions are appropriately adjusted according to the ferroelectric material properties to optimize the storage function to be maintained at the best condition.

In this way, the data recovery cycle can be optimized to reduce power consumption during operation. For example, in conventional DRAM (Dynamic Random Access Memory), each word line has to recover data every 15.6μs and each block every 64ms. However, the memory of the present invention has a data of one second, one hour, or several hours. The number of driving required for data retention is reduced by that since Therefore, the power consumption can be saved by that much. In addition, the memory of the present invention does not need to apply a voltage between the capacitor and both ends during the standby period for operation, so that no leakage current is generated during the standby period, thereby significantly reducing the power consumption during the standby period. By utilizing these advantages, it can be driven at a significantly lower power than the power consumption of conventional DRAM, pseudo-SRAM and SRAM.

In addition, the structure of a capacitor constituting a unit cell of a conventional DRAM or SRAM is complicated, and the limit of the manufacturing process is gradually reached. In other words, as the degree of integration in a conventional memory increases, the allowable area per unit cell decreases, and in attempting to realize the same capacitor capacity in such a reduced area, the capacitor's stack cell or depth cell increases. There are many technical problems in the process. In further detail, in order to realize a capacity of 30 fF to 25 fF per unit capacitor, the height of the stack capacitor is gradually increased as shown in 40 of FIG. 12, and as shown in FIG. 13, the height of the capacitor is about 1.8 μm. It is true. This phenomenon is a great burden in the manufacturing process of 0.1μm. On the other hand, when the ferroelectric capacitor is used, the height thereof is lowered to about 0.3 or 0.5 μm, thereby eliminating difficulties in the manufacturing process.

In addition, the unit cell structure of the conventional SRAM is configured as six individual elements as shown in FIG. This is an obstacle to high integration because it is composed of a large number of devices compared to a DRAM composed of one transistor and one capacitor or a conventional ferroelectric memory. Therefore, high density memory has been developed mainly around DRAM, and SRAM has been mainly used where stable and high speed operation is required. The memory of the present invention is composed of one transistor and one capacitor whose unit cell structure is simpler than that of SRAM, and is easier to integrate than SRAM.

Finally, data damage caused by alpha light particles (αparticle or cosmic ray), which is a type of radiation injected from a package or atmosphere, commonly experienced by conventional memories such as DRAM, Pseudo-SRAM, SRAM, Flash or EEPROM. You can solve the problem. In other words, the memory of the present invention employs a ferroelectric material that is resistant to such particles, so that stable operation is possible in the presence of such particles in space or in the atmosphere. Thus, there is no need to use the heavy and thick Tungsten vessels used in satellites or spacecraft to protect conventional memory, saving the cost of such devices.

1 is an equivalent circuit of a conventional DRAM cell,

2 is an equivalent circuit of a conventional SRAM cell,

3 is an equivalent circuit of a unit cell of the memory device of the embodiment;

4 is a memory cell array equivalent circuit of an embodiment;

5 is a sense amplifier of an embodiment,

6 is a data writing scheme of a conventional and embodiment;

7 is a data reading scheme of a conventional and embodiment;

8 is a data recovery scheme of an embodiment of the invention;

9 is a characteristic curve of a conventional ferroelectric capacitor,

10 is a data distribution diagram of a conventional ferroelectric memory;

11 is a memory storage characteristic distribution curve of the invention,

12 is a cross-sectional view of a conventional DRAM cell,

13 is a cross-sectional view of a capacitor of a conventional DRAM cell;

14 is a cross-sectional view of a capacitor of the embodiment,

15 is an equivalent circuit of the invention memory cell.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate 10a, b: device layer and well region

11a, b: device isolation region 12a: drain region

12b: source region 13: gate oxide film

14: gate electrode 20, 20a, 20b: interlayer insulating film

30a: drain electrode 30b: source contact plug

40: capacitor 40a, c: lower, upper electrode

40b: oxide film for dielectric 50: plate line

Explanation of Terms in Drawings

WL, WL ₀ , WL ₁ : word line and word line for gate control and its 0 and 1

BL, BL ₀ , BL ₁ : Bit line and bit line for signal transmission and its 0 and 1

BL , BL ₀ , BL ₁ : Bit line bar for transmitting reference voltage for signal reading and its 0 and 1

PL, PL ₀ , PL ₁ : plate wire for ferroelectric capacitor control and its 0 and 1

M1, M2: NMOS transistors 1 and 2 of the inverter circuit

M3, M4: PMOS transistors 3 and 4 of the inverter circuit

M5, M6: cell select transistors 5, 6

Cx, C0, C1, C2, C3: ferroelectric capacitors x, 0, 1, 2, 3

Tx, T0, T1, T2, T3: Selection transistors for switches x, 0, 1, 2, 3

MCx, MC0, MC1, MC2, MC3: x, 0, 1, 2, 3 of unit memory cell

DL ₀ , DL ₁ , DL ₀ , DL ₁ : Data bus lines 0, 1 and data bus lines 0, 1

S / A0, S / A1: Sense Amplifier 0, 1

SAE, NPL: Sense amplifier drive terminals, unpatterned plate ends

SB: small unit block

D1, D0, T _rec. : Data 1 and 0, data recovery cycle

Vx, V _CC : applied voltage across the ferroelectric capacitor, internal drive voltage

V _DD , Vss: The power supply for the inverter circuit. V _DD is high "Hi" voltage and Vss is low.

Voltage

DRAM, SRAM: Dynamic Random Access Memory, Static Random Access Memory

In order to achieve the above object, in the semiconductor memory device according to the present invention, a unit cell of a memory is composed of a ferroelectric capacitor and a switch selection transistor, and the ferroelectric capacitor has a pair of ferroelectric films for storing data due to polarization phenomenon. One electrode, which is a lower electrode of the two electrodes, is connected to the source of the switching select transistor, and the other electrode is connected to a plate line for driving the ferroelectric capacitor. On the other hand, the drain of the switch selection transistor is connected to the bit line to form one unit cell. That is, as shown in Fig. 3, the unit cell MCx is composed of a bit line BL, a switch selection transistor Tx, a ferroelectric capacitor Cx, a word line WL, and a plate line PL.

These unit cells are arranged horizontally (X direction) and connected to different bit lines BL ₀ and BL ₁ , as shown in FIG. 4, and several cells listed horizontally (X direction) have the same word line and plate. (WL ₀ , PL ₀ ) are connected to the lines, respectively, to form one small block SB. These small blocks are arranged in the longitudinal direction (Y direction) as shown in Fig. 4, and several switching select transistors for each bit line are connected in parallel to form one large block.

In one large block, each bit line extends longitudinally (Y direction) to form one large block bit line, and each bit line BL ₀ , BL ₁ is a sense amplifier (Fig. 5). The other electrode of the sense amplifier S / A is connected to the reference voltage bit line bar BL , which provides a reference voltage, while being connected to the bit line BL of S / A, forming a pair of bit lines. do. The bit line bar BL providing the reference voltage is connected to the circuit for generating the reference voltage. The pair of bit lines BL and BL seeks to optimize circuit operation in an open bit line structure or a folded bit line structure.

According to the semiconductor memory device according to the present invention, as shown in Fig. 4, the plate line is connected to a signal generator for driving the plate line, and connected to a circuit for supplying a signal necessary for the operation of reading data. Fig. 5 is connected to form one sense circuit. One or more such sense amplifiers are arranged as shown in Fig. 4 (S / A0, S / A1) to form one large block. An output terminal of each sense amplifier is connected with the data bus line (DLx, DL x), the cell array side is a data signal generated in the ferroelectric capacitor is associated with a selection transistor for bit line switches are input to the input terminal of the sense amplifier Amplified by the sense amplifier and advanced to the output through the selected data bus line.

In addition, the word lines WL ₀ and WL _{1 in} Fig. 4 are respectively connected to a word line selection circuit and a signal generator for inputting signals to the word line and a control circuit for commanding the drive of the signal generator. In the same way as the line, it is connected to the plate select circuit, the drive circuit and the control circuit which commands the drive.

The signal generator should be able to adjust the shape and period of the signal so as to optimize the size of the data signal generated in the unit cell, and the control circuit for commanding the drive may also optimize the size of the signal generated in the unit cell. The time required must be adjusted.

Since these large blocks are gathered together to form a memory product, the location of the blocks, the arrangement of the connection lines, and the overall configuration of the block must be optimized according to the overall driving conditions. Optimization criteria can consider the choice of circuits needed for driving, and shared use, based on drive time, power consumption and footprint. Common uses include signal generators, sense amplifiers ...

(action)

In the structure of the semiconductor memory device and the driving method thereof used in the present invention, the reading and writing method may be driven in the same manner as the conventional method, as shown in Figs. What is going to be implemented in the present invention relates to a method of recovering and storing the stored data more completely.

First, in the reading method, as shown in Fig. 7, the bit line is precharged first, and the voltage of the bit line is held at the level of the standby state before reading the data. In this bit line state, a high (Hi) is applied to the word line during T0 and T1 to turn on the switch selection transistor to an "on" state to electrically connect the ferroelectric capacitor and the bit line. Then, high (Hi) is applied to the plate line to generate polarization of the ferroelectric material. In this case, when the data stored as shown in FIG. 9 is D0, it reacts along the path of state 2 from state 1 of FIG. 9, while D1 reacts to state 1 through state 2 from state 4 Done. In this case, in the case of D0, charges are generated as much as the difference between state 1 and state. In case of D1, charges are generated by the difference between state 1 and state 4, so that D1 transfers more charge to the bit line than D0. The voltage level of the bit line is read and read into D0 and D1.

When the charge is transferred in this way, the amount of charge transferred varies depending on the capacitance of the ferroelectric capacitor and the bit line. Thus, as shown in FIG. 9, the word line is electrically interrupted between T1 and T2 for a short time to connect the multiple lines connected in parallel to the plate line. The influence of the load on the two ferroelectric capacitors can be minimized, thereby maximizing the charge transferred to the bit line. The minute voltage delivered to the bit line is read and amplified by the sense amplifier during T2 and T3, D1 is amplified toward the high V _DD level, and D0 is amplified toward the low Vss level. The amplified signal is transmitted to the data bus line, and the signal is transmitted to the output through the amplification stage of the selected data bus line.

Next, in the write operation, as shown in FIG. 6, when the selected bit line is pre-charged and the high voltage is applied to the word line, the ferroelectric capacitor is applied. A low voltage is applied to the bottom electrode of and the source of the switch selection transistor. At this time, if the driving signal Hi is applied to the plate line, the state becomes upward polarization. As shown in Fig. 9, the polarization state becomes the state 1 position, and D0 is recorded. If the word line is made high after applying the low voltage and applying the bit line to the high voltage, the lower electrode of the ferroelectric capacitor is electrically connected to the bit line, so that the polarization state of the ferroelectric capacitor is shown in FIG. As shown in Fig. 6, the position becomes the position of state 4 in the downward polarization state, and D1 is recorded.

Next, the storage data recovery operation, which is the present invention, will be described. As shown in Fig. 7, a high voltage is applied to a word line and a high voltage is also applied to a plate line. As in .9, D0 acts along the characteristic curve from state 1 to state 2 on curve 1, while D1 characterizes state 1 through state 2 through state 2 on curve 1 Run along the curve. In the process, D0 and D1 respectively transfer different amounts of charge to the bit lines according to the polarization state of the ferroelectric material. The transferred charges generate different levels of voltage on the bit lines. The interval between T1 and T2 in Fig. 8 represents this operation, which plays a very important role for data recovery. This is because by adjusting the timing of this section, the imprint phenomenon occurring in the D1 or D0 state can be minimized. Experimentally, data corruption stored in ferroelectric capacitors is degraded in the direction that D0 data increases and D1 decreases due to imprint effect when data is read after switching to the opposite polarization state after storing D1 or D0 for a long time. Happens. Therefore, this section is adjusted as much as possible to prevent the data from being stored in the same polarization state for a long time in D1 or D0, thereby preventing data corruption. The core of this invention is here. The signal generated on the bit line during this period is amplified to D0 in a low state and D1 in a high state during the periods of T2 and T3 as shown in Fig. 8, and the driving voltage of the sense amplifier is V _DD . It is fully amplified to the voltage level of Vss. In the data recovery operation, it is very important to properly adjust the level of the amplified signal to recover the data signal. This is because the voltage must be high enough to make the polarization state 1 or state 4 in the period between T3 and T4. That is, during this period, when a low voltage is applied to the plate line and a high voltage is applied to the bit line to apply the voltage across the ferroelectric capacitor, -Vx is applied across the ferroelectric capacitor as shown in FIG. Results. As a result, data is rewritten during the periods T3 and T4, and as shown in Fig. 9, the cell of D0 is restored from the state 3 to the state 1 and the state is reduced to the state D0, while D1 is restored from the state 1 to the state 5. Through this, the polarization state becomes state 4, and D1 is restored and written again. This entire process, from T0 to T4, is called data recovery by refreshing the data again. The core of the present invention is the addition of this data recovery function, which periodically refreshes the stored data to preserve the state of storage.

(Example)

The structure and driving method thereof of a semiconductor memory device according to an embodiment of the present invention will be described with reference to Figs. Fig. 4 is composed of a 2 × 2 array composed of two lines, a word line, a plate line and a bit line. There are two bit lines, and two switch select transistors MC0 and MC2 for each bit line are connected in parallel to the same bit line in the longitudinal direction (Y direction). Ferroelectric memories C0 and C2 are connected, and each capacitor is connected to different plate lines PL ₀ and PL ₁ . Thus, one row is formed in the longitudinal direction (Y direction), and one or more rows are arranged in the horizontal direction (X direction) to form one large block.

On the other hand, as shown in Fig. 4, the word line and the plate line (WL ₀ and PL ₀ , WL ₁ and PL ₁ ) are arranged side by side in a row, each in a row, and each pair is selected for a switch in a horizontal (X direction) direction. The transistors and ferroelectric capacitors MC0 and C0, MC1 and C1 are arranged side by side in the X direction. At this time, the drain of the select transistor for the switch has a different bit line (BL ₀ or BL ₁ ), the source is connected to one electrode of the ferroelectric electrode, each of the other electrode of the ferroelectric capacitor is a plate line (PL ₀ or PL ₁ ). These unit cells form one row horizontally (in the X direction) (MC0 and C0, MC1 and C1), and another unit cell, MC2 and C2, MC3 and C3, forms another row. It is formed in parallel with this species (Y direction). Such a memory configuration forms an even number of bit lines, an even number of word lines and a plate line to form one large block, and a plurality of blocks constitutes an entire memory. In the memory array thus formed, the bit line is transferred to the output via the sense amplifier and the signal amplifier of the data bus line.

Next, an operation of writing data and a reading and storing method of the semiconductor memory device according to the embodiment will be described.

First, the writing operation will first be described in the case where data is written into the ferroelectric capacitor C0 of the memory cell MC0 in the small block SB of the memory cell in the first column of FIG. When writing data, a high voltage signal voltage is applied to the switch select transistor gate WL ₀ to turn the switch select transistor on. At this time, the switch selection transistors "MC1" for one column are also turned on at the same time. On, the ferroelectric capacitors C0 and C1 are electrically connected to the bit lines BL ₀ and BL ₁ , respectively, so that the polarization state is upward depending on the potential state of the bit lines and the plate lines. Is D0, or is written as D1, which is in a downward polarization state. That is, as shown in Fig. 6, the source of the switch selection transistor, to which the lower electrode of the ferroelectric capacitor is connected, is designated at a low voltage which is the same potential as the potential of the bit line, and is connected to the upper electrode of the capacitor. The plate line is designated with a high voltage, so that the ferroelectric capacitor is in an upward polarization state and D0 is written. On the other hand, when the high voltage of the bit line is applied to the lower electrode through the select transistor in the state where the plate line, which is the upper electrode, is precharged to the low voltage, the ferroelectric capacitor is converted to the downward polarization state to D1. The state is written.

Due to this polarization phenomenon, D0 or D1 is written to C0. The other capacitor C1 in column ₁ is applied to BL ₁ with the same voltage as the plate line, and electrical conditions are stored in C1 to prevent polarization. The data remains unchanged. That is, after a low voltage is applied to BL ₀ , a high voltage is applied to BL ₁ , a high voltage is applied to the plate line, and then a high voltage is applied to the word line “WL ₀ ”. When voltage is applied, the switch selection transistors CM0 and CM1 are turned on at the same time, and C0 becomes D0 and there is no change in the stored data.

On the other hand, to write D1 to C3 in the two columns of Fig. 4, BL ₀ is a low voltage, BL ₁ is precharged to a high voltage, as shown in Fig. The low voltage is applied to PL ₁ , the plate line. Next, when a high voltage is applied to the word lines WL ₁ of two columns, the voltage difference between the bit line and the plate line, which is applied first, causes C3 to be in a downward polarization state, so that D1 is written to C3, and voltage between C2 is applied to C2. There is no difference, so writing operation does not occur. On the other hand, after applying a high voltage to the bit line BL _{0 and} a low voltage to BL ₁ and applying a high voltage to the plate line, the high voltage is applied to the corresponding word line WL ₁ . When is applied, upward polarization phenomenon appears at C3, and D0 is input.

Next, the read operation will be described. First, the operation of reading the data of C0 in the first column of Fig. 4 will be described. As shown in Fig. 7, first, bit lines BL ₀ and BL _{1 are set} to a low voltage in a precharge state. Next, a high input Hi is applied to the word line WL ₀ to electrically connect the bit line and the source of the select transistor for the switch, which is a lower electrode of the ferroelectric. Finally, when high is applied to the plate line, a high voltage is applied to the upper electrode of the ferroelectric capacitor and a low voltage is applied to the lower electrode. As shown in Fig. 9, the polarization reaction state of the ferroelectric capacitor is performed. D0 reacts along the path of state 2 in state 1 and D1 reacts along the path of 1 through state 2 in state 4. Thus, D0 produces less charge and D1 generates relatively more charge, so that less charge is D0 and more charge is read as D1. After the data is read to C0 through this process, the polarization state of the originally stored polarization state D0 remains unchanged, but the polarization state of D1 is reversed. That is, D1 changes to the state of D0.

At this time, the data must be rewritten through a process of rewriting to restore the original data. This operation is performed between T1 and T3 in FIG. That is, after the data signal is transferred to the bit line between T1 and T2, the D1 data signal is increased toward V _DD which is high by the sense amplifier and the D0 data signal is reduced toward the voltage of Vss. The signals amplified sufficiently between T2 and T3 are then applied to the bottom electrode of the ferroelectric capacitor, which is connected to its source via a switch select transistor. At this time, the plate line, which is another electrode of the capacitor, is applied at a low voltage, and -Vx is applied to FIG. In this process, D0 maintains state 1 in a polarized state, as shown in Fig. 9, and D1 returns to its position through the path of states 1 → 3 → 5 → 4. The data destroyed in the reading process is rewritten and restored.

Next, a recovery function of the data stored in the embodiment will be described. While the data is stored in the ferroelectric capacitor C2, the data recovery function is performed as shown in FIG. This function is possible in the same manner as shown in FIG. The difference between this function and the readout is that, as described above, the readout must be driven to read the stored data as quickly as possible, so that all sections from T0 to T4 in Fig. 7 should be made as short as possible. On the other hand, since the imprint is prevented at the inversion of the polarization state (D1↔D0) occurring between T1 and T2 of FIG. 8, the data recovery function should be adjusted to maintain the polarization function as much as possible. . In addition, in order to restore the polarization function, a sufficient electric field must be applied between the both ends of the capacitor, and thus, the T3 and T4 sections must be optimized so that sufficient voltage is applied to the bit line. That is, the level of the amplified bit line signal should be adjusted to the level of the voltage of V _DD or Vss so that the sections T2 and T3 can be sufficiently amplified.

In general, in conventional memory, the bit line signal is not sufficiently amplified to the V _DD and Vss voltages by the bit line sense amplifier during the read operation. This is because the transistors constituting the sense amplifier are small in size, so that a sufficiently large current cannot be realized in a limited area.

For example, assume that D0 is recorded in C2. As shown in Fig. 8, after pre-charging BL ₀ and BL ₁ in Fig. 4, a high voltage is applied to the word line of the switch select transistor to make it ON, and the plate line is also turned on. When a high voltage is applied, as shown in Fig. 8, the data stored in the ferroelectric capacitor C2 is read. At this time, only a negligible signal is generated in the bit line during the periods T1 and T2 of FIG. (BL) is applied to the reference voltage, the voltage of the bit lines (BL) are recognized below the reference voltage, the level of the bit line (BL) to access the voltage Vss. As a result, as shown in Fig. 8, the bit line BL becomes the potential of D0. At this time, as shown in Fig. 9, the ferroelectric capacitor develops the operation from the state 3 of the polarization state to the state 1, so that no change occurs in the D0 state of C2.

On the other hand, in the case of D1, as shown in Fig. 9, it reacts in the process of polarization state 4 → 2 → 1, but if a certain time is placed at the position of inversion 1, it occurs at the position of state 4 in the downward polarization state. Imprint phenomenon is prevented. That is, the imprint phenomenon occurring in the polarization state D1 is prevented by using the inverted polarization state of D0, and in the case of D0, the deterioration phenomenon is prevented by utilizing the D1 state. This is to minimize the influence of the polarized strong electric field causing the imprint inside the material to minimize the disturbance of the polarization of the material. To this end, as shown in Fig. 8, it is necessary to optimize the time between T1 and T2 to minimize the imprint phenomenon. Then, if data is recorded again between T2 and T3, good data with the imprint effect is minimized. Through this process, it is possible to secure a memory that satisfies commercially required operating conditions. Therefore, in this invention, it is very important to optimize the period of T1 and T2 that influence the data recovery function.

It is possible to integrate and implement different characteristics and operations of DRAM, pseudo-SRAM, and SRAM memory into one memory, and to solve the operating characteristics and operational weaknesses of each, and ultimately integrate nonvolatile memory in the future. There is an effect for in-memory implementation.

First of all, the memory of the present invention can be driven at a significantly lower power than the current non-volatile memory due to the characteristics of the operation, and thus it is possible to innovatively reduce the power consumption. That is, it can be stored for more than 1000 times longer than the refresh time of the current DRAM data storage time (hundreds of ms), which is about several hours or longer, and tens of hours are sufficient. Therefore, the signal must be input periodically every 15.6us per unit word line and the data must be periodically rewritten every 64ms per unit block to overcome the limitation of rewriting data. As shown in Fig. 11, at least once every several hours. The frequency of data recovery can be used, which significantly reduces the power consumption required to maintain the stored data. In other words, it may be assumed that one data recovery cycle per hour or one cycle per day is used as the data recovery cycle. In this case, the current consumption in the self-refresh operation of the DRAM and the pseudo-SRAM is reduced to several uA compared to several mA and several tens of uA, respectively, so that data can be preserved even under 1% of conventional memory power consumption. This is a suitable property as a memory suitable for mobile communication using batteries.

In addition, the conventional memory has a fatal disadvantage that data stored by radiation such as alpha light particles or cosmic rays from the outside is damaged and requires a rather complicated and difficult technology to prevent this, but the memory of the present invention is an external incident wave It has a strong resistance to, and works reliably in spacecraft or alien space. In other words, since satellites or spacecraft can be used stably without a separate device, there is no need for a separate heavy and large Tungsten box that is currently in use, thereby reducing costs.

In addition, the memory of the present invention has a simple manufacturing technology, which can solve the manufacturing difficulties of the conventional DRAM technology. That is, to maintain a capacity such as 30fF to 25fF per unit capacitor in DRAM. As the stack height of the stack structure corresponding to 40 of 12 and 13 increases, the current height of the capacitor reaches about 1.8 μm. This is a huge burden in the 0.1 μm process. The height of this high capacitor is reduced to 0.3μm to solve manufacturing difficulties. Memory technology has enormous equipment investment and development costs to solve these manufacturing problems, which can reduce these costs and generate more profit. In addition, the inventive memory technology has a simple unit cell structure compared to a conventional memory, and thus has the advantage of enabling higher integration than DRAM and SRAM using the same technology. Therefore, Pseudo-SRAM, which is currently used as a communication memory, can be easily implemented at a lower cost.

In addition, the memory of the present invention can integrate conventional volatile memories having various structures, thereby simplifying the manufacturing and development process of DRAM, SRAM, and pseudo-SRAM. Therefore, not only the development and manufacturing cost can be reduced, but also various functions can be implemented as a single memory structure, thereby simplifying the manufacturing cost and the process. That is, one product can be applied to various systems, thereby reducing the cost and enhancing the efficiency of the semiconductor industry.

Finally, in the situation where conventional ferroelectric memory is less interested in development due to the limitation of reliability despite the superiority of its expected characteristics, the memory of the present invention is consumable because it generates profit with the technology of conventional ferroelectric memory. It can also break development reality. Furthermore, the generated profits provide the investment for research, making it easier to develop ferroelectric technology, thus enabling the foundation for the completion of the ideal memory.

Claims (18)

A patent on a structure of a memory semiconductor device and a driving method thereof, comprising: a memory device based on a select transistor for a switch and a ferroelectric capacitor formed on a semiconductor substrate; A structure of a memory unit cell based on the switch selection transistor and a ferroelectric capacitor and a driving method thereof; A structure of a memory block in which the unit bundles of the unit cells or the memory are regularly arranged horizontally and vertically; A driving method including a method of writing data into the ferroelectric capacitor-based memory device and a method of recovering stored data; Detecting a signal of a plurality of bit line pairs in which data signals in a plurality of cells in the unit cell or a block are output at the same time, and selecting and reading one of these signals; And a memory based on the selection transistor and the ferroelectric capacitor as part of the semiconductor product. The semiconductor device of claim 1, wherein the semiconductor device comprises one of silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), and germanium. The semiconductor device of claim 1, wherein the semiconductor is composed of one of a metal oxide silicon field effect transistor (MOSFET), a bipolar junction transistor (BJT), and a field effect transistor (FET) formed in a mutual compensation process (CMOS) process. Device. The ferroelectric material in the structure of the ferroelectric capacitor, PZT (Pb _w Zr _x O _y Ti _z ), SBT (Sr _w Bi _x Ta _y O _z ), BST (Bi _w Sr _x Ta _y O _z ) A semiconductor device comprising any ferroelectric material having a polarization phenomenon including a series of materials, and at least one oxide film or metal material having electrical conductivity as an electrode. The structure according to claim 1, wherein in the structure of the unit cell, one electrode of the ferroelectric capacitor is connected to the source of the selection transistor, and the other electrode is connected to the plate line. A semiconductor device in which the above ferroelectric capacitors are connected in series using a common source, and each ferroelectric capacitor has a separate plate line. In the above fifth, in the driving method of the unit cell, each plate line is driven independently of each other, a drive signal is input to the plate line corresponding to the selected ferroelectric capacitor, and the other plate line in the standby state is open. Reads through a common selection transistor and a bit line for a common switch in a waiting manner. The semiconductor device of claim 1, wherein the unit cells are arranged horizontally in the form of one block and have one block structure among NOR, OR, NAND, and AND formats. 2. A method of writing data in a unit cell according to claim 1, wherein the polarization state corresponding to one or more data is written in the same capacitor, and two or more data including D0 and D1 are recorded. 9. The method of claim 8, wherein a plurality of pieces of data are recorded by adjusting a level of voltage of an input signal of a plate line or a bit line to generate a polarization state corresponding to different voltages. How to record. The method according to claim 1, wherein the data stored in the ferroelectric capacitor is preserved or retained by inputting a signal through a plate line to read the stored data of the ferroelectric capacitor, and amplifying the signal through a bit line and a sense amplifier. A method of rewriting the amplified signal back to the ferroelectric capacitor. The method of claim 1, further comprising: a method of preserving data stored in the ferroelectric capacitor, the method of reading data from the ferroelectric capacitor to be read and rewriting the data into an amplified signal, wherein the cell is periodically rested in the standby state during the operation period. How to read and rewrite data, and how to drive the two together. In the method of regularly storing data in the cell waiting in the above paragraph 11, one or more plate lines and bit lines are driven simultaneously to recover data in any number of cells associated with these two types of lines simultaneously. How to preserve. 12. The method of claim 11, wherein the method of preventing deterioration by imprinting includes switching to a polarization state opposite to a polarization state of a state in which data is written and resting the cell data in the state. The method of claim 13, wherein the waiting time in the polarization state opposite to the stored data is adjusted in a manner of minimizing the degree of degradation by imprint. 12. The semiconductor device using the control circuit and the signal generating circuit required to drive one or more plate lines in the above 12. The method of claim 1, wherein in a structure in which one or more pairs of bit lines are arranged horizontally, a pair of bit lines are selected from a plurality of bit lines, and then connected to a common sense amplifier to amplify the data. Way. 15. The method of claim 14, wherein the signal level of the bit line is amplified to adjust the level of the signal, applying a sense circuit to the level of the bit line signal, and using the result to adjust the amplification degree of the sense amplifier. The composite semiconductor device according to claim 1, wherein any composite semiconductor device including a portion of a memory having a data storage and recovery function based on the ferroelectric capacitor and the select transistor for the stitch.