KR20040029146A - Method for producing a semiconductor device having an edge structure - Google Patents

Abstract

In cell power MOSFET devices and other semiconductor devices in accordance with the present invention, one wide connection across the perimeter of the active device region 120 is replaced by a plurality of narrow conductive fingers 111. These fingers 111 are used as follows in providing the required doped edge area 50 under the connection. Dopants are injected and diffused into the spaces 112 between and adjacent the fingers 111 to form a single continuous region 15a extending below and between the spaces 112 between the fingers 111. This doped edge region can be, for example, a deep guard ring at the edge termination of the power MOSFET or an extension of its channel receiving region. The trench gate network 11 of the MOSFET is connected to the gate bond pad and / or field plate 114 by the conductive finger 111.

Description

Semiconductor device and manufacturing method therefor {METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVING AN EDGE STRUCTURE}

Trench gate power MOSFETs include an active device cell containing an trench gate and an insulated gate trench that extends through the channel receiving region from the source region to the drain region existing below the MOSFET. Is a well known semiconductor device. The trench gate is dielectrically coupled to the channel receiving region by an intermediate gate dielectric layer (typically an oxide) at the sidewall of the gate trench.

Specific examples of trench gate power MOSFETs are disclosed in published European patent application EP-A-1009 035, which relates in particular to improving the breakdown characteristics of the device in the device termination region. To this end, a method is taken to relax the electric field at the top edge UE and bottom edge BE of the gate trench, where the gate connection is connected to the gate pad and / or field plate beyond the active cell region of the device. The entire contents of EP-A-1 009 035 are incorporated herein by reference.

In the peripheral zone around the active zone, the channel receiving region and the gate trench network terminate in the edge region of the first conductivity type. This termination promotes breakdown voltage at the bottom end edge BE of the gate trench. The edge region may be an extension of the channel receiving region or may be a deeper and heavily doped region than the channel receiving region. In each case, a gate trench is provided after providing the edge region and the channel receiving region. A gate connection is then provided over this edge region.

EP-A-1 009 035 discloses various gate connection schemes for mitigating and / or removing the electric field in the insulating film at the upper end edge UE of the gate trench. In particular, the gate connection is away from the upper end edge UE of the gate trench. Applicants note that in some of these embodiments (FIGS. 46, 57, 61, and 67 of EP-A-1 009 035), the resulting gate connection is electrically conductive by providing space around the parallel trench gate ends. Note that it includes parallel fingers.

The present invention is based on a different approach in that FIG. 1 of the present invention illustrates an experimental trench gate MOS transistor structure that has not been previously disclosed. This figure is for example a simplified MOS transistor with its source region 13 and source electrode 23 omitted. In this case, insulated trench gates 11 and 16 are formed before the so-called "P body implantation" which provides the p-type channel receiving region 15 to this n-channel device. This order is advantageous for optimizing the channel profile in the trench gate MOSFET.

Thus, in order to optimize the channel profile, formation of the gate dielectric 16 (usually formed by oxidation) is preferably performed prior to P body implantation. This provides greater freedom in the thermal budget used to form the channel receiving region 15 (P body), which results in lower channel resistance. However, P body implantation (and any deeper P implantation) may not be performed immediately after forming the gate oxide 16, since this would undesirably prevent dopants in the bottom portion of the trench gate 20. Because it is injected. Therefore, this implantation is performed after the deposition and patterning of the gate 11. Furthermore, performing P body implantation (and any deeper P implantation) after trench gate 11 formation is desirable to reduce external diffusion of P dopant during growth of sacrificial oxide and gate oxide in trench 20. Do.

However, due to the order in which the implantation is performed after the isolation trench gates 11 and 16 are formed, these implants may not exist in the edge region of the MOSFET as shown in FIG. 1. Thus, no P body (or deeper P region) is included below the gate connection 110 at the edge termination of the device active region 120, for example to the gate bond pad 114 and / or the field plate 114. . Due to the absence of this P body (or deeper P region), voltage breakdown occurs too early and ruggedness is lost.

Thus, FIG. 1 shows the last generated end RE of the P body 15 at the periphery of the active region 120 of the trench gate MOS transistor. This end RE does not extend as far as the outer trench 12 of the device periphery of FIG. 1. Thus, there is a high electric field at the base of these peripheral trenches 12 without any P body 15. As a result, an early yield phenomenon occurs as illustrated by a star-shaped BD in FIG. 1.

Summary of the Invention

It is an object of the present invention to generally overcome the aforementioned disadvantages in semiconductor devices and MOSFETs. It is also an object of an important embodiment of the present invention to provide a trench gate MOSFET having better breakdown voltage characteristics.

In a first aspect of the invention, a method of fabricating a semiconductor device is provided that includes an electrically conductive connection extending on an edge region of an active region of the device, wherein the electrical connection comprises parallel electrically conductive fingers. (A) forming the fingers on a region where the edge region is to be provided, (b) subsequently injecting a dopant of a first conductivity type to the edge region through the spaces between the fingers; c) diffusing the dopant under the fingers to form the edge region as at least a substantially continuous region of the first conductivity type extending below the space between the fingers and the fingers.

This use of contact fingers and their associated spaces can advantageously provide an edge region by diffusing a dopant under the fingers after formation of the connection (and thus after trench gate formation in trench gate device fabrication). .

The invention advantageously provides an edge region (such as a channel receiving region and / or a termination extension of a guard-ring and / or ruggedness region) under the gate connection of the MOSFET device. Can be used. The present invention is advantageously used in trench gate cell power MOSFETs. Particular trench gate features are proposed in claims 3-7 and 13 and 14. However, the present invention may advantageously be used to provide a connection on the edge region in other types of semiconductor devices such as bipolar transistors or even integrated circuits.

The values for the specific parameter of the fingers and the specific parameter of the dopant diffusion can be broad depending on the specific device region, device feature size, and the specific fabrication technique used.

Dopant diffusion step (c) may be performed in one or more stages after or during the doping step (b). Diffusion can occur, for example, for a period of from 5 minutes to 200 minutes, typically about 10 to 100 minutes. This diffusion can be carried out at a temperature of at least about 950 ° C and preferably at a temperature of at least about 1,050 ° C. Typically, the dopant for the P type region is boron.

The fingers (as defined in step (a)) have a width, for example, in the range of 0.1 to 20 μm, preferably in the range of approximately 0.6 to 2 μm. These fingers are substantially parallel to each other to form a connection of dense width. The gap (space) between adjacent fingers is 1 to 50 μm, preferably 2 to 17 μm. The width of these spaces is preferably at least about three times the width of the finger, for example about 4-15 μm. These fingers have a length to width ratio of 2: 1 to 40: 1, typically 15: 1 to 20: 1.

Typically, electrically conductive fingers are formed of conductively doped polysilicon. This conductive doping may be performed in a specific step in the case of polysilicon and / or in the doping step used for the device region. The conductivity of the polysilicon fingers can be improved by changing at least a portion of the polysilicon into metal silicides. This silencing step may be performed before or after the doping step (b) for the edge region. However, other materials may be used for the fingers. For example, the fingers can be formed by a heat resistant metal and / or a combination of several materials.

In fabricating the trench gate device, the finger defining step (a) is preferably performed after the formation of the trench gate network and preferably after the growth of the gate oxide region in the trench gate network.

In one example, finger defining step (a) preferably comprises (ai) depositing a finger forming material, (a.ii) defining a pattern for the electrically conductive finger as a mask, (a.iii) the Etching the deposited material so that the fingers defined by the mask remain.

This finger defining step may be performed in the same process used to etch back (planarize) the trench gate in the gate trench. Thus, step (a.iii) involves etching the electrically conductive finger and planarizing the trench gate. If this etching step (a.iii) poses a risk of damaging the exposed area of the gate dielectric, step (a) preferably comprises (a.iv) after the planarization step (a.iii) Regrowing the damaged area.

The pattern defined by the mask in step (a.ii) can include fingers as well as other parts of the device to be made of polysilicon.

The edge region is a deeper and more heavily doped region than the channel receiving region. Preferably, in this case, the doping step (b) is accomplished with a ruggedness implant. Thus, step (b) comprises (bi) defining a pattern for rigid implantation into the mask in the active zone, and (b.ii) performing the rigid implantation to form a rigid region in the window of the mask and the active Forming a guard-ring edge-region around the region, and (b.iii) removing the mask.

Channel implantation (to provide the channel receiving region) is a maskless implant.

However, channel injection can be used to provide the edge region at the edge of the trench gate network where no active device channel is formed (preferably around the entire periphery of the trench gate network).

The fingers are self-standing on the edge region and extend between end gates and trench gate networks, such as gate pads or field plates. Such standalone fingers can be created by etching material away from under the fingers.

The capacitance between the gate and the source of the MOSFET can be advantageously reduced by making the fingers stand on their own.

These standalone fingers comprise a second layer of conductive material in contact with the first layer providing the gate network of the trench gate MOSFET. Alternatively, these fingers may not be connected to the trench gate network. The second layer is intermittently present.

In another example, finger defining step (a) preferably comprises forming the electrically conductive material into sidewall spacers by etching back a contour-deposited material.

In another example of such a trench gate MOSFET fabrication, step (a) comprises (ai) depositing a sacrificial layer (eg, an oxide) and patterning the sacrificial layer with a first mask to define the shape of the fingers; a.ii) depositing material for the fingers on the patterned sacrificial layer, and (a.iii) etching back the finger material to form the fingers as sidewall spacers in the patterned sacrificial layer. And (a.iv) removing the sacrificial layer to leave the fingers.

In step (a.iii) the loop shaped fingers can be etched and formed.

In a second aspect of the invention, there is provided a semiconductor device comprising an electrically conductive connection extending on an edge region of an active region of the device, wherein the electrical connection comprises parallel electrically conductive fingers, the edge region being At least a substantially continuous region of a first conductivity type extending below the space between the fingers and the fingers, wherein the edge region defines a diffusion dopant profile below the fingers consisting of dopant diffused from below the space between the fingers. Have

Other advantageous features according to the first and / or second aspect of the invention are proposed in the appended claims. All of the features described herein can be combined with any other features of the first or second aspect.

Specific embodiments of the present invention will now be described by way of example with reference to the accompanying drawings.

The present invention relates to a semiconductor device in which an electrically conductive connection extends over an edge region of an active region of the device and a method of manufacturing the same. In particular, the present invention relates to forming gate connections at the periphery of MOSFETs (i.e., insulated gate field effect transistors), such as, for example, trench gate power MOSFETs.

1 is a cross-sectional view of a portion of a non-traditional (unpublished) self-aligned trench gate MOSFET with no edge region under its gate connection, FIG.

2 is a scanning electron microscope (SEM) photograph of a particular example of one embodiment of the present invention, wherein an edge region is formed below a gate connection including a conductive finger;

3A is a cross-sectional view of a portion of a trench gate MOSFET embodiment of the present invention taken on a line along a conductive finger of a gate connection;

3B is a cross-sectional view of a portion of the trench gate MOSFET of FIG. 3A taken on a line that exists along the space between the conductive fingers of the gate connection;

4 is a cross-sectional view taken on the X-X line of FIGS. 3A and 3B, showing an example of a continuous edge region under conductive fingers;

5 is a cross-sectional view taken on the X-X line of FIGS. 3A and 3B showing an example of a substantially continuous edge region under conductive fingers;

6 and 7 are cross-sectional views of the device portion of FIG. 3A (or FIG. 3B) in two successive stages in device fabrication according to the first embodiment of the present invention;

Fig. 8 is a plan view of the next fabrication stage for defining a pattern of conductive fingers using a mask in this first embodiment,

9-11 are cross-sectional views of the device portion of FIG. 7 in successive stages during device fabrication in accordance with a first embodiment of the present invention, where FIG. 9A is taken on a line along conductive fingers and FIGS. 9B, FIG. 10 and 11 are views taken on a line existing along the space between conductive fingers,

FIG. 12 is a modified photograph of the SEM photograph of FIG. 2 showing conductive fingers extending as standalone fingers standing themselves on an active device region in a particular example of another embodiment of the present invention;

13-16 are cross-sectional views of a device portion of a series of fabrication stages in a second embodiment of the present invention in which conductive fingers are formed as sidewall spacers;

FIG. 17 is a plan view of a device portion in the stage of FIG. 16, FIG. 16 taken on line C-C in FIG. 17, FIG.

18 and 19 are cross-sectional views and top views, respectively, corresponding to FIGS. 16 and 17 at successive stages during device fabrication according to the second embodiment, and FIG. 18 is a view taken on line C-C in FIG. 19;

20 is a sectional view at another stage in the device manufacture of the second embodiment;

Except for the SEM photographs of FIGS. 2 and 12, all figures are schematic. Accordingly, the relative sizes and ratios of the various parts of these figures have been enlarged or reduced in size for purposes of clarity of explanation. Like reference numerals refer to corresponding similar features in the modified and other embodiments as well as in FIG. 1.

First, reference is made to the semiconductor device features shown in FIG. 2. In general, the present invention includes the manufacture of a conductive device that includes an electrically conductive connection 110 extending over the edge region 15a of the device zone 120. This connection 110 includes parallel electrically conductive fingers 111. The edge region 15a is an at least substantially continuous region of the first conductivity type that extends under the fingers 111 and below the space 112 next to and between the fingers 111. Unlike the edge regions disclosed in the prior art (eg EP-A-1 009 035), the edge region 15a in the device according to the invention has a dopant profile diffused under the fingers 111. This dopant profile consists of dopant diffused from below the space 112 next to and between the fingers 111.

2 shows a first type of manufacturing method in which the pattern of the fingers 111 is defined by a photolithography mask. An example of this first type of process embodiment will be described with reference to FIGS. 3 to 11. A second type of process embodiment will be described with reference to Figs. 13-20, in which a pattern of fingers is defined as sidewall spacers. These two types of process embodiments according to the present invention generally comprise the steps of (a) forming the fingers 111 on the region 50 where the edge region 15a is to be provided (Figs. 2, 8, 9a, 9b, 18 and 19) and (b) implanting a dopant of a first conductivity type for the edge region 15a through the space 112 between the fingers 111 (FIG. 10 and 20) and (c) at least substantially of the first conductivity type extending below the fingers 111 and below the space 112 between the fingers by diffusing the dopant under the fingers 111. To form the edge region 15a as a continuous region (see FIGS. 3A, 3B and 11 and 20).

A particular device embodiment of FIG. 2 is a power MOSFET with a trench gate network 111 in the active cell region 120. Connection 110 (which typically includes polysilicon) connects this trench gate network to field plate 114 or gate pad 114 on field oxide 60 around the MOSFET periphery. Due to the polysilicon fingers 111 of the contacts, dopants are injected into the gaps between the fingers and the dopants are diffused to form a single continuous region under the fingers, thereby forming the doped region 15a below the contacts 110. It may be formed in the device substrate 10.

All particular device embodiments (FIGS. 2-20) are trench gate power MOSFETs in which connection 110 is a gate connection on edge region 15a at the MOSFET periphery. The basic MOSFET structure of these device embodiments includes a number of active device cells in the cell region 120 of the semiconductor body 10, which is commonly silicon, as is known. These cells are connected in parallel between the source and drain electrodes 23, 24 at the rear and front major surfaces of the body 10, respectively (see FIG. 3).

Each active device cell is a channel of a first conductivity type (p type in this particular example) between a surface adjacent source region 13 that is of a second conductivity type (n type in this particular example) and a drain region 14 below it. It has a receiving area 15. Typically region 14 is a lightly doped (n) drain drift region on the more heavily doped (n +) drain electrode region 14d. An insulated gate trench 20 containing trench gate 11 extends from source region 13 through channel receiving region 15 to drain region 14 below it. The trench gate 11 is dielectrically connected to the region 15 by an intermediate gate dielectric layer 16 (typically an oxide) at the sidewall of the gate trench 20. This creates a conductive channel 12 in the region 15 between the source and drain regions 13 and 14 in the on state of the MOSFET (see FIG. 3).

The active device cell of this trench gate MOSFET has any known layout geometry, such as a densely packed hexagonal or square matrix or long stripe. 2, 12, 17, and 19 illustrate a hexagonal trench network, and FIG. 8 illustrates a square matrix. Around the periphery of the active cell zone 120, each MOSFET embodiment has an annular termination structure comprising a guard ring 15a in the form of an edge region and a field insulator 60. The gate connection 110 (including the finger 111) is the guard ring region at the device termination between the gate bond pad and / or field plate 114 and the trench gate network 11 of the active cell region 120. Extend on (15a).

The invention is used in each of the embodiments of FIGS. 2-20 so that the guard ring region 15a can be provided in steps (b) and (c) after the finger structure of the gate connection 110 is formed. Different dopant implants are used to provide different shaped regions 15a. By way of example, these two different forms will be described in the specific embodiment of FIGS. 3-11 and the specific embodiment of FIGS. 13-20.

3 to 11 embodiment

In this power MOSFET embodiment, the edge region 15a is formed by so-called AP implantation that is deeper and has a higher dose than the P body (channel) implantation forming the channel receiving region 15. Typically, the AP implant with a high dose of boron (about 2 * 10 ¹⁵ cm ⁻² ) is a P + rigid region 15b within the active device region 120 of at least some cells, as shown in FIGS. 3A and 3B. Is used to provide Here, stiffness is the ability of a MOSFET device to consume energy when operating in an avalanche condition.

This eliminates the need for an early separate guard ring injection (DP) that forms a prior art interface between the active zone 120 and the device edge termination (eg, as in EP-A-1 009 035). Thus, the existing three photomask process flows DP / OD / AP (guard ring injection / field oxide etch / rigid injection) contain only OD mask and AP mask (2 photomask process flow: field oxide etch / guard ring And rigid injection).

This process flow will now be described with reference to FIGS. 6-11.

First, a thick oxide layer (eg, up to a thickness of approximately 0.8 to 0.9 micrometers) is grown on the silicon wafer surface 14a and patterned by etching in an OD mask stage to form the field oxide 16 around the active device region 120. ). Thereafter, a TR mask is provided to define a network of interconnected trenches 20 which are then etched into the epitaxial region 14. The cross section of the structure thus produced is shown in FIG. 6, where a TR mask still exists. The cell pitch, denoted CP, is determined by the TR mask in active region 120. The trench network defined by this TR mask includes a peripheral trench around the periphery of the zone 120 (see FIG. 8) and will form an area 15a in this portion.

After removing the TR mask, the gate oxide layer 16 is grown. This layer 16 grows by thermally oxidizing the exposed silicon surface of the device region 120, including the trench network 20. Polysilicon layer 24 is then deposited to provide gate 11, gate bus-bars and connections 110, and gate pads and field plates 114. In this particular embodiment, by way of example, each of the device portions 11, 110, 114 is formed of a polysilicon layer 24 deposited at this stage. The conductivity of the polysilicon 24 is determined by the degree of doping and the degree of annealing. In this particular embodiment, the gate and its connections are retained as conductively doped polysilicon. However, polysilicon may be silicided to reduce electrical resistance and heat resistant metals may be used.

The next stage is the PS mask step as shown in FIG. At this stage, a photoresist mask PS is provided on the polysilicon layer 24 region that is retained to form the gate bus bars and connections 110 and the gate pads and field plates 114. Subsequently, layer 24 is etched in the area without the mask. This etching step defines the polysilicon finger pattern of the connection 110, ie its fingers 111 and the space 112. This etching step also etches back the layer 24 in the region 120, mostly maskless, leaving planarized polysilicon in the trench network 20, which forms the trench gate 11. Gate oxides on the body surface (of the areas not covered by the polysilicon fingers 111) are exposed during this etching step and any areas damaged by the etching are recovered by the regrowth step.

9A and 9B are cross-sectional views taken along lines AA and BB of FIG. 8, respectively, after the PS mask is removed. These two figures show the planarized polysilicon gate 11 in the active device trench 20. 9A shows a gate polysilicon finger 111 (as defined after the PS etch step) extending from the polysilicon gate 11 in the peripheral trench. As shown in FIG. 9B, the polysilicon of the portion of the peripheral trench 20 present between these polysilicon fingers 111 is planarized. The SEM photograph of FIG. 2 was taken at this stage and this photograph was created after PS etching and planarization but in this particular example shows a polysilicon pattern with hexagonal cell trench network.

2 and 9A and 9B show the simplest structure, wherein the polysilicon finger 111 is connected to the active zone through the peripheral trench 20 inside the zone 50 in which the guard ring region 15a is to be provided. It is connected to the trench gate network 11 near the edge. These fingers 111 may extend on the dielectric layer 16 over the region 50 in which the edge region 15a will be formed. Typically, the polysilicon fingers 111 have a width in the range of 0.6 to 2 μm. These fingers 111 are deliberately made small so that the implanted AP dopant 150 can diffuse under these fingers 111.

The next stage is a mask AP stiff injection of the dopant 150 (in this example a high dose amount of boron ions), as shown in FIG. An AP mask, typically a photoresist, defines the dopant 150 implantation for the P + rigid region 15b in the active device region 120 and defines the implantation region 50 for the edge guard ring region 15a. . As shown in FIG. 10, the inner periphery of the guard ring region 15a is defined by an AP mask and the outer periphery of this region 15a is defined by the inner edge of the field oxide 60.

Fingers 111 prevent AP dopant 150 from being injected directly under the fingers (except that dopant ions are scattered in the semiconductor crystal lattice) due to their thickness. However, the fingers 111 are narrow (e.g., 1 to 2) such that the AP implanted dopant 150 is diffused thereunder to form at least a substantially continuous region 15a in accordance with the present invention. Μm range). Such diffusion is typically carried out for approximately 10 to 100 minutes at a temperature of at least 1,050 ° C. 4 shows a continuous region 15a in which a dopant 150 injected into an adjacent space 120 penetrates under the finger 111. 5 shows a substantially continuous region 15a having a very small gap 14x between adjacent diffused consecutive portions of region 15a. This very small gap (smaller than the depth of the region 15a) has no effect on the guard ring operation of the region 15a. Therefore, the distribution of the depletion layer 40 from the PN junction 45 between the drain region 14 and the substantially continuous region 15a is not affected by the presence of the gap 14x.

Since the AP implantation and its dopant diffusion are performed after the growth of the gate oxide 16, the implanted dopant 150 can be diffused regardless of this oxide growth. AP implantation and dopant diffusion thereof may even be performed after depositing and etching polysilicon material for the gate 11 and its connections 110. Thus, the present invention can be used to provide the guard ring region 15a irrespective of the step of providing the insulated trench gate 11 and the gate connection 110 with a rigid AP implant and its dopant diffusion.

More specifically, as shown in FIGS. 10 and 11, the AP process sequence is as follows. The photoresist mask AP is applied. AP injection 150 is then performed and the AP mask is removed. At this stage, annealing and diffusing the implanted AP dopant 150 is optional before performing channel implantation. This optional step enables separate optimization of stiffness and channel injection thermal budget.

Maskless channel (P body) implantation is performed after AP implantation in FIG. 10 to provide a channel receiving region 15 within the device cell, as shown at the left of FIG. This annealing of the P body implantation (and of course subsequent diffusion of the AP implanted dopant 150) proceeds for approximately 10 to 100 minutes.

The remaining stages of this process are conventional. Accordingly, subsequent process steps include implanting a source using a mask to form source region 13, depositing and etching oxide layers 61 and 62 to form a source contact window, depositing and Etching to form the source electrode 23, vaporizing the metal at the back of the wafer to form the drain electrode 24, and dividing the wafer into individual MOSFET bodies. This deposited oxide forms an interlevel insulator 62 between the insulating cap 61 on the trench gate and the source electrode 23 present thereon and the connection 110 and field plate 114 present below it. However, more complex processes based on self-alignment techniques are advantageous when including finger contacts 110 and transversely spread regions 15a in these process sequences. Examples of such self-aligning technology embodiments will be described below with reference to FIGS. 13-20.

12 embodiment

12 shows a variation of this embodiment.

In this embodiment, each of the device portions 11, 110, 114 is formed of the same polysilicon layer 24 as shown in FIG. 7. In the embodiment of FIG. 12, the trench gate 11 is formed by depositing and planarizing the first polysilicon layer 24 without using a mask, and then the higher level portions 110, 114 are formed of the second polysilicon layer ( 124 can be formed by depositing and etching using a mask.

In the embodiment of FIG. 7, the polysilicon layer 24 was adjacent to the thin gate oxide layer 16 on the wafer surface 14a outside the trench network 20 and in the trench network 20. The variant embodiment of FIG. 12 enables the formation of stand-alone polysilicon fingers 111 that stand on their own. Thus, for the embodiment of FIG. 12, a sacrificial layer (preferably thicker than thin layer 16) is provided on zone 50. The fingers 111 can then be formed by depositing a polysilicon layer 124 on this sacrificial layer and masking and etching the polysilicon as in the previous embodiment. Subsequently, before or after AP implantation, the sacrificial layer is removed from below the fingers 111 to form an air gap below the fingers 111. This air gap (and the space 112 in the finger structure 111) allows for reduction of capacitance between the connection 110 and the edge region 15a underlying it. This serves to reduce the Cgs capacitance in the MOSFET where the connection is a gate connection and the source electrode is in contact with the source region 13 and the channel receiving region 15. Thus, this air gap improves the switching performance of the device.

In addition, as shown in FIG. 12, the independent fingers 111 formed from the second polysilicon layer 124 may extend as independent gate bus bars 121 across the active cell region 120. This gate bus bar may be in intermittent contact with the trench gate network 20 as shown in FIG.

13 to 20 embodiment

FIG. 20 illustrates a trench gate MOSFET embodiment in which the edge region 15a (under the gate connection 110) is provided as an extension of the channel receiving region 15 beyond the cell active region 120. Thus, in this embodiment, the edge region 15a is provided in the same process step as the channel receiving region (P body) 15, that is, the same depth and the same dopant dose amount. In the gate junction region 50, the P body dopant is diffused under the finger 111 to form at least a substantially continuous region 15a. This region 15a is not an active channel region because a source region 13 which is then provided in region 15 is not provided in region 15a.

This embodiment uses sidewall spacer technology to provide the connection 110 with a polysilicon finger 111 having a much narrower width than the above embodiment. The use of this very narrow polysilicon finger 111 facilitates dopant diffusion down the finger, which is also compatible with smaller device features that can be obtained using self-aligned trench gate technology. Using self aligned trench gate technology, the contact window and source region 13 for the source electrode 23 are self aligned with respect to the narrow gate trench 20. For example, various self-alignment techniques can be used as disclosed in pending UK (GB) Patent Application No. 0101695.5 (Philips Reference No. PHNL 010060) with a priority date of January 23, 2001, which is incorporated herein by reference.

The novel process sequence according to the invention will now be described with reference to FIGS. 13 to 20.

After etching the trench gate network 20 and gate oxide, polysilicon 24 is deposited and etched back to the level of the silicon oxide layer 60. The polysilicon 24 is then etched back to the level of the silicon wafer surface 14a in the active device region 120 using a mask on the peripheral region. This fills the trench window in oxide layer 60 with polysilicon 24 only at the periphery of the device (ie, edge region 50 shown in FIG. 13).

Thereafter, a relatively thin nitride layer 236 is deposited followed by a second polysilicon 238. This polysilicon layer 238 is then anisotropically etched back down to the nitride surface as shown in FIG. The nitride polysilicon structures 236 and 238 are used to cap the trench gate 11 instead of the oxide layer 61 of the previous embodiment.

A relatively thick TEOS layer 240 is then deposited and etched with a mask defining oxide fingers 242 as shown in FIGS. 16 and 17. However, it is generally useful to create as many oxide fingers 242 as possible. This further reduces the gate resistance.

The TEOS etch forming oxide finger 242 stops on the nitride layer 236 bottom. Subsequently, the region of the nitride layer 236 not masked by the oxide 240 is removed as shown in FIG. 15.

Subsequently, the third polysilicon layer 244 is contour deposited and the gate pad and / or field plate 114 is anisotropically etched back while masking the required area. By this etching back, loop-shaped polysilicon fingers 111 are formed as polysilicon spacers on the sidewalls of the oxide fingers 242 as shown in FIGS. 16 and 17.

The oxide layer 60, oxide finger 242 and intermediate nitride layer 236 are then anisotropically etched back to the wafer surface 14a, except for the areas masked by the polysilicon portions 111, 114. 18 and 19 show the structure finally produced at this stage.

Then, as shown in FIG. 20, P body implantation 151 is performed to provide a dopant for the channel receiving region in the active region 120 and for the edge region extension 15a in the gate junction region 50. Provide dopants. Thereafter, the implanted dopant is diffused to form at least substantially continuous region 15a under polysilicon finger 111. The continuity of this region 15a can be easily achieved without requiring a long diffusion time because the width of the polysilicon spacer finger 111 is very narrow, as shown in FIG.

This polysilicon spacer technology can produce a narrower finger than the fingers produced using a mask, thereby providing an advantage in self-alignment options. However, such spacer technology may also be advantageously used for gate connections in conventional trench gate MOSFET processes. This offers the opportunity to perform P body implantation and AP implantation later in the process, which is desirable for an optimized P body doping profile. A suitable process for a typical trench gate MOSFET example is as follows.

After the epitaxial layer for the drift region has grown, the gate trench is etched. The gate oxide grows and then deposits a polysilicon layer and is etched back to the silicon surface. Next, a relatively thin layer of nitride is deposited followed by a relatively thick TEOS layer. Thereafter, the TEOS layer is etched back with a mask defining oxide fingers. TEOS etching is stopped on the nitride layer bottom and this nitride protects the gate oxide during TEOS etching. The nitride layer is then removed. The polysilicon layer is then deposited and anisotropically etched back using a mask to form polysilicon spacers on the sidewalls of the oxide fingers. Thereafter, all oxide and thin nitride layer bottoms (including oxide fingers) are anisotropically etched back down to the silicon surface. Then, AP injection is performed and diffused to perform P body injection. The subsequent process is the same as a conventional process flow, i.e., including the source injection and annealing step, the TEOS deposition step, the CO contact window etching step and the like as described above.

2-20 disclose an advantageous method of using polysilicon fingers to connect a trench gate network to a field plate or gate pad. The use of such a finger allows P body implantation or AP implantation to be implanted after the finger is formed and then diffused under the finger, thereby forming a continuous P type edge region. This spreading is possible because of the narrow width of the fingers.

Upon reading the above disclosure of the present invention, it will be understood that other modifications and variations are possible to those skilled in the art. Such modifications and variations are known in the semiconductor device manufacturing arts and may include other features that may be used in place of or in combination with the features disclosed herein.

In the foregoing disclosure, p type implantation has been referred to to form n channel devices. Of course, n type implantation may be used to form a p type channel device. Thus, the specific example described above is an n-channel device where the source and drain regions 13 and 14 are n-type conductive and the regions 32 and 26 are p-type and the electron inversion channel 12 is made active by the trench gate. Create within 32. By using the opposite conductivity type dopant, p-channel devices can also be manufactured in accordance with the present invention. In this case, the source and drain regions 13 and 14 are p-type conductive and the regions 32 and 26 are n-type and create a hole inversion channel 12 in the active region 32 by trench gates. Reference to each of the channel (N body) injections and the rigid / guard ring (AN) injections can be found in the description of P body injection and AP injection.

The invention is also applicable to power MOSFETs of planar DMOS type (instead of trench gate type) where the MOS gate is on a dielectric layer on the body surface (instead of inside the trench). The invention can be used to solve the same problem in other semiconductor devices such as bipolar transistors (instead of MOSFETs). The device active zone of such a device may or may not be present on the cell. Thus, the present invention can generally be used to provide a connection (in the form of a conductive finger) from an active device region on an edge region, where the edge region injects dopants between the fingers and implanted dopants under the fingers. Is diffused in the device body.

Although the claims have been written for specific combinations of features, the disclosure of the present invention is also subject to any novelty whether or not in conjunction with the same inventions present within this claim and whether or not the invention addresses the same problems solved. It includes any feature or any novel combination of features explicitly or implicitly disclosed herein or any generalization thereof.

Accordingly, it should be noted that new claims may be made for any other application or combination of the above features and / or any such feature during the examination of the present application derived from the present application.

Claims (19)

A method of manufacturing a semiconductor device, wherein the semiconductor device includes an electrically conductive connection extending on an edge region of the active zone and the electrical connection includes parallel electrically conductive fingers. (a) forming the fingers on a region where the edge region is to be provided; (b) subsequently injecting a dopant of a first conductivity type for the edge region through the spaces between the fingers; (c) diffusing the dopant under the fingers to form the edge region as at least a substantially continuous region of the first conductivity type extending below the space between the fingers and the fingers. Semiconductor device manufacturing method. The method of claim 1, The active device region comprises insulated gate field effect type active device cells having a gate network in a cell active region, Each of the active device cells includes an insulated gate adjacent a channel receiving region of the first conductivity type between a drain region and a source region of a second conductivity type, The connection with its fingers is provided as a gate connection from the gate network in the cell active area, Thereafter, the edge area is provided in steps (b) and (c) to terminate the channel receiving area around the periphery of the cell active area. Semiconductor device manufacturing method. The method of claim 2, The device is a trench gate type device having its gate in a trench extending from a surface adjacent source region to a portion of the drain region existing below and through the channel receiving region, By providing an insulating layer on the sidewalls of the gate trench, the gate is dielectrically connected to the channel receiving region, The trench gate network is formed prior to providing the edge region, Thereafter, the edge region is provided at a position where the gate trench network terminates at the periphery of the cell active region. Semiconductor device manufacturing method. The method of claim 3, wherein The edge regions provided in steps (b) and (c) are deeper and more heavily doped than the channel receiving region. Semiconductor device manufacturing method. The method of claim 4, wherein The edge region is provided to a depth deeper than the gate trench in steps (b) and (c). Semiconductor device manufacturing method. The method according to any one of claims 3 to 5, The channel receiving region is provided after the trench gate formation and after the edge region formation. Semiconductor device manufacturing method. The method of claim 3, wherein The edge area is provided as an extension of the channel receiving area beyond the cell active area and in the same process step as the channel receiving area. Semiconductor device manufacturing method. The method according to any one of claims 1 to 7, The diffusion step (c) is carried out in one or more stages at a temperature of at least 950 ℃ Semiconductor device manufacturing method. The method according to any one of claims 1 to 8, The electrically conductive fingers are formed of polysilicon and / or silicide and / or a refractory metal. Semiconductor device manufacturing method. The method according to any one of claims 1 to 9, The fingers have a width in the range of 0.1 to 2 μm. Semiconductor device manufacturing method. The method according to any one of claims 1 to 10, The space between adjacent fingers among the fingers formed in step (a) is at least three times wider than the finger width. Semiconductor device manufacturing method. The method according to any one of claims 1 to 11, Step (a) is, (a.i) depositing the finger forming material; (a.ii) providing a mask on the deposited material to define a pattern for the fingers; (a.iii) etching the deposited material leaving behind the fingers defined by the mask. Semiconductor device manufacturing method. The method of claim 12, The device is a trench gate field effect type device having its gate dielectrically connected to the channel receiving region by an intermediate gate dielectric layer provided on the sidewall of the gate trench, The gate is provided in the gate trench by a material deposited in step (a.i) and etched back in step (a.iii), The mask provided in step (a.ii) is not present on the gate trench in the active device region, Any area damaged by the etching in the gate dielectric layer is regrown in step (a.iv) Semiconductor device manufacturing method. The method according to any one of claims 1 to 13, The device is a trench gate field effect type device, A first gate material layer is deposited and etched back in the gate trench leaving the trench gate inside the gate trench, A second layer of material is then deposited and etched in step (a) to provide the fingers of the connection to the trench gate. Semiconductor device manufacturing method. The method according to any one of claims 1 to 14, A mask is provided on the active area of the device prior to step (b) to mask the dopant implanted for the edge area, The mask is removed after performing step (b). Semiconductor device manufacturing method. The method according to any one of claims 1 to 15, The deposited material is etched away from under the fingers of the connection such that the fingers stand on themselves at least a portion of their length. Semiconductor device manufacturing method. The method according to any one of claims 1 to 11, Step (a) is, (a.i) depositing a sacrificial layer and patterning the sacrificial layer with a first mask to provide an outline for the desired pattern of fingers; (a.ii) depositing material for the fingers on the patterned sacrificial layer; (a.iii) etching back the finger material to form the fingers as sidewall spacers in the patterned sacrificial layer; (a.iv) removing the sacrificial layer to leave the fingers Semiconductor device manufacturing method. A semiconductor device, wherein the semiconductor device includes an electrically conductive connection extending on an edge region of the active zone and the electrical connection includes parallel electrically conductive fingers. The edge region is at least a substantially continuous region of a first conductivity type extending below the space between the fingers and the fingers, The edge region has a diffusion dopant profile under the fingers, consisting of dopants diffused from below the space between the fingers. Semiconductor device. The method of claim 18, 18. Having any of the additional device features in the method according to any of claims 2 to 17. Semiconductor device.