KR20040025800A - Method for forming a gate line in a semiconductor damascene structure - Google Patents

Method for forming a gate line in a semiconductor damascene structure Download PDF

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KR20040025800A
KR20040025800A KR1020020056401A KR20020056401A KR20040025800A KR 20040025800 A KR20040025800 A KR 20040025800A KR 1020020056401 A KR1020020056401 A KR 1020020056401A KR 20020056401 A KR20020056401 A KR 20020056401A KR 20040025800 A KR20040025800 A KR 20040025800A
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South Korea
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gate line
gate
forming
nitride film
nitride layer
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KR1020020056401A
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Korean (ko)
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서영훈
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아남반도체 주식회사
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Publication of KR20040025800A publication Critical patent/KR20040025800A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

PURPOSE: A method for forming a gate line using a semiconductor damascene structure is provided to avoid a notch phenomenon and a foot phenomenon by controlling critical dimension by a nitride layer etch process and a sidewall nitride layer etch process, and to generate a stable profile by performing an ion implantation process after a vertical profile is formed. CONSTITUTION: A tunneling oxide layer(2) is deposited on a silicon substrate(1). A nitride layer(6) is deposited on the tunneling oxide layer. After photoresist(5) is formed on the nitride layer, a gate pattern is formed. The nitride layer is etched. After a nitride layer is deposited, a sidewall etch process is performed. After polysilicon is deposited in a hole line of the nitride layer, photoresist is applied to form a gate pattern. A gate etch process and a cleaning process are performed to form a final gate line.

Description

반도체 다마신 구조를 이용한 게이트 라인 형성 방법{METHOD FOR FORMING A GATE LINE IN A SEMICONDUCTOR DAMASCENE STRUCTURE}Gate line formation method using semiconductor damascene structure {METHOD FOR FORMING A GATE LINE IN A SEMICONDUCTOR DAMASCENE STRUCTURE}

본 발명은 반도체 로직 디바이스(Logic Device)에서의 게이트 제조 기술에 관한 것으로, 특히, 노치(notch) 또는 풋(foot) 현상이 없는 수직적(vertical)인 프로파일(profile)이 가능하며 미세 패턴의 형성 없이도 높은 CD(Critical Dimension)를 갖는 게이트 라인을 형성하는데 적합한 반도체 다마신(Damascene) 구조를 이용한 게이트 라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to gate fabrication techniques in semiconductor logic devices, and in particular, allows for a vertical profile without notches or foot phenomena and without the formation of fine patterns. A method of forming a gate line using a semiconductor damascene structure suitable for forming a gate line having a high critical dimension (CD).

반도체 제조 공정 기술의 발달과 함께, 디바이스의 고집적화 정도는 점점 더 높아지고 있으며, 이에 비례하여 게이트 크기 역시 점차 축소되고 있다.With the development of semiconductor manufacturing process technology, the degree of high integration of devices is increasing, and the gate size is gradually decreasing in proportion.

도 1은 종래의 전형적인 게이트 라인의 제조 과정을 나타낸 단면도이다.1 is a cross-sectional view showing a conventional manufacturing process of a typical gate line.

도 1에 도시한 바와 같이, 실리콘 기판(1)상에 게이트 산화막(2)을 형성한 후, 폴리실리콘(3)을 증착한다.As shown in FIG. 1, after the gate oxide film 2 is formed on the silicon substrate 1, polysilicon 3 is deposited.

이후, 게이트 라인을 형성하기 위하여 BARC(Bottom of Anti Reflection Coating : 하부 반사방지막)(4)를 코팅하고 포토레지스트(5)를 도포하여 게이트 패턴을 형성한다.Thereafter, BARC (Bottom of Anti Reflection Coating) 4 is coated to form a gate line, and a photoresist 5 is applied to form a gate pattern.

게이트 패턴을 형성한 다음, 상술한 BARC(4)를 먼저 식각한 후 식각 장비, 예를 들어, EPD(End Point Detection) 장비(도시 생략됨)를 이용하여 폴리실리콘(3)을 식각한다.After forming the gate pattern, the above-described BARC 4 is first etched, and then the polysilicon 3 is etched using an etching apparatus, for example, an end point detection (EPD) apparatus (not shown).

이때, 게이트 라인의 CD는 BARC(4)의 오버에칭 시간을 조절함으로써 달성될 수 있다.At this time, the CD of the gate line can be achieved by adjusting the overetching time of the BARC 4.

그런데, 이와 같은 방법은 게이트 라인 폭이 0.13㎛ 정도까지는 BARC 또는 DARC(Dielectric of Anti Reflection Coating : 유전체 반사방지막)와 같은 물질을 통하여 게이트 라인의 형성이 가능하나, 그 폭이 더 줄어들게 되면 패턴 마진이 줄어들게 되어 새로운 패턴 장비와 방법의 필요성이 증가하게 되는데, 현행 기술로는 이러한 요구를 만족시키기 어려워 0.1㎛ 이하의 게이트 라인이 있는 공정 진행이 어려워진다는 문제점이 발생한다.By the way, the gate line may be formed through a material such as BARC or DARC (Dielectric of Anti Reflection Coating) until the gate line width is about 0.13 μm, but if the width is further reduced, the pattern margin is increased. As a result, the need for new pattern equipment and methods increases, which makes it difficult to meet these requirements with current technology, making it difficult to process a gate line having a gate line of 0.1 μm or less.

즉, 종래의 게이트 라인 제조 공정 기술에서는, 게이트 크기의 극소화로 인해 패턴 공정만으로 게이트 라인을 형성하는 데에는 어느 정도 한계가 있을 뿐만 아니라, 게이트 CD가 감소함에 따라 실리사이드(Silicide) 저항이 증가할 수 있다는 문제가 제기되었다.That is, in the conventional gate line fabrication process technology, the gate line is minimized to form the gate line only by the pattern process due to the minimization of the gate size, and the silicide resistance may increase as the gate CD decreases. The question was raised.

게다가, 단순한 BARC 오버에칭 시간을 이용하여 게이트 라인 CD를 조절하는 경우, 오버에칭 시간이 과도하여 게이트 라인이 불균일하게 형성될 수 있다는 문제가 제기되었다.In addition, when adjusting the gate line CD using a simple BARC overetching time, a problem has been raised that the overetching time may be excessive and the gate line may be formed unevenly.

본 발명은 상술한 문제를 해결하기 위해 안출한 것으로, 질화막 식각 공정과 측벽 질화막 식각 공정을 통해 CD를 제어하여 노치와 풋 현상을 방지하고 수직적인 프로파일 생성 후 이온 주입(Implant) 공정을 진행함으로써, 안정된 프로파일을 생성할 수 있으며 트랜지스터 특성을 결정하는 하부(bottom) CD와는 달리 상부(top) CD를 크게 제어하여 실리사이드 저항을 감소시키는 게이트 라인을 형성하도록 한 반도체 다마신 구조를 이용한 게이트 라인 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, by controlling the CD through the nitride film etching process and the sidewall nitride film etching process to prevent notches and foot phenomenon, by proceeding the ion implantation (Implant) process after generating a vertical profile, Unlike the bottom CD, which can generate a stable profile and determine the transistor characteristics, a gate line forming method using a semiconductor damascene structure is formed so that the top CD is largely controlled to form a gate line that reduces silicide resistance. The purpose is to provide.

이러한 목적을 달성하기 위하여 본 발명은, 반도체 다마신 구조를 이용한 게이트 라인 형성 방법에 있어서, 실리콘 기판 상에 터널링 산화막을 증착하는 제 1 단계와; 터널링 산화막 상에 질화막을 증착하는 제 2 단계와; 질화막 상에 포토레지스트를 도포한 후 게이트 패턴을 형성하고, 질화막을 식각하는 제 3 단계와; 질화막을 증착시킨 후, 측벽 식각 공정을 실시하는 제 4 단계와; 제 4 단계에서 형성된 질화막의 홀 라인내에 폴리실리콘을 증착시킨 다음, 포토레지스트를 도포하여 게이트 패턴을 형성하는 제 5 단계와; 게이트 식각 및 세정 공정을 실시하여 최종 게이트 라인을 형성하는 제 6 단계를 포함하는 것을 특징으로 하는 반도체 다마신 구조를 이용한 게이트 라인 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a gate line forming method using a semiconductor damascene structure, comprising: a first step of depositing a tunneling oxide film on a silicon substrate; Depositing a nitride film on the tunneling oxide film; A third step of forming a gate pattern after applying the photoresist on the nitride film and etching the nitride film; A fourth step of performing a sidewall etching process after depositing a nitride film; Depositing polysilicon into the hole line of the nitride film formed in the fourth step, and then applying a photoresist to form a gate pattern; It provides a gate line forming method using a semiconductor damascene structure comprising a sixth step of performing a gate etching and cleaning process to form a final gate line.

도 1은 종래의 전형적인 반도체 게이트 라인 형성 과정을 설명하기 위한 공정 단면도,1 is a cross-sectional view illustrating a process of forming a typical semiconductor gate line in the related art;

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 반도체 다마신 구조를 이용한 게이트 라인 형성 과정을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a process of forming a gate line using a semiconductor damascene structure according to a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 : 실리콘 기판 2 : 터널링 산화막1 silicon substrate 2 tunneling oxide film

3 : 폴리실리콘 4 : BARC3: polysilicon 4: BARC

5, 5' : 포토레지스트 6 : 질화막5, 5 ': photoresist 6: nitride film

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

설명에 앞서, 본 발명의 핵심 기술 요지는, 질화막 식각 공정과 측벽 질화막 식각 공정을 이용하여 게이트 라인을 형성함에 있어서, 초기 형성되는 질화막의 두께를 조절하여 측벽 식각 공정시 공간 조절이 가능하므로 게이트 형성을 보다 미세하게 구현한다는 것으로, 이러한 기술 사상으로부터 본 발명에서 목적으로 하는 바를 용이하게 구현할 수 있을 것이다.Prior to the description, a key technical gist of the present invention is to form a gate line by forming a gate line by using a nitride film etching process and a sidewall nitride film etching process, so that the space can be adjusted during the sidewall etching process by adjusting the thickness of the nitride film that is initially formed. By implementing the finer, it will be able to easily implement the purpose of the present invention from this technical idea.

도 2a 내지 도 2d는 본 발명의 바람직한 실시예에 따른 다마신 구조를 이용한 게이트 라인 형성 과정을 설명하기 위한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a process of forming a gate line using a damascene structure according to a preferred embodiment of the present invention.

먼저, 도 2a에 도시한 바와 같이, 실리콘 기판(1)상에 터널링 산화막(2)을 증착하고, 이 터널링 산화막(2)상에 질화막(6)을 증착한다.First, as shown in FIG. 2A, the tunneling oxide film 2 is deposited on the silicon substrate 1, and the nitride film 6 is deposited on the tunneling oxide film 2.

이후, 이러한 질화막(6) 상에 포토레지스트(5)를 도포한 후 게이트 패턴을 형성하고, 질화막(6)을 EPD 장비를 이용하여 식각한다.Thereafter, after the photoresist 5 is coated on the nitride film 6, a gate pattern is formed, and the nitride film 6 is etched using an EPD device.

도 2b에서는, 다시 질화막(6)을 증착시킨 후, 측벽 식각, 즉, 에치백 공정을 실시한다.In FIG. 2B, after the nitride film 6 is deposited again, sidewall etching, that is, an etch back process is performed.

도 2c에서는, 상술한 도 2b 공정에 의해 형성된 질화막 홀 라인내에 폴리실리콘(3)을 증착시킨 다음, 포토레지스트(5')를 도포하여 게이트 패턴을 형성한다.In FIG. 2C, polysilicon 3 is deposited in the nitride film hole line formed by the above-described FIG. 2B process, and then a photoresist 5 'is applied to form a gate pattern.

도 2d에서는, 게이트 식각 및 세정 공정을 실시하여 최종 게이트 라인을 형성한다.In FIG. 2D, gate etching and cleaning processes are performed to form a final gate line.

이후의 공정은 일반적인 공정 순서에 따라 진행된다.The subsequent process proceeds according to the general process sequence.

즉, 본 발명은 반도체 디자인 룰이 줄어듦에 따라 0.25㎛, 0.18㎛, 0.10㎛로 점차 줄어드는 게이트 라인의 감소시 발생할 수 있는 패턴 형성의 어려움과 같은 게이트 크기 내에서 가질 수 있는 실리사이드 저항을 줄임으로써 좀 더 안정적인 디바이스 제어를 구현하도록 한 것이다.In other words, the present invention reduces the silicide resistance that may have within the gate size, such as the difficulty of pattern formation that may occur when the gate line is gradually reduced to 0.25 μm, 0.18 μm, and 0.10 μm as the semiconductor design rule decreases. It is to realize more stable device control.

이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 그 요지를 벗어나지 않는 범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.

따라서, 본 발명은 향후 측벽 식각 후 형성될 게이트의 폭을 고려하여 초기에 증착되는 질화막의 두께를 조절함으로써 타겟으로 하는 게이트 라인을 다양하게 형성할 수 있다는 장점을 지니고 있으며, 모트(moat)와 폴리실리콘의 절연을 위하여 사용하는 측벽 공정을 생략할 수 있는 효과가 있다.Accordingly, the present invention has the advantage that the target gate line can be variously formed by controlling the thickness of the nitride film initially deposited in consideration of the width of the gate to be formed after the sidewall etching in the future. There is an effect that the sidewall process used for the insulation of silicon can be omitted.

Claims (3)

반도체 다마신(Damascene) 구조를 이용한 게이트 라인 형성 방법에 있어서,In the gate line forming method using a semiconductor damascene structure, 실리콘 기판 상에 터널링 산화막을 증착하는 제 1 단계와;Depositing a tunneling oxide film on the silicon substrate; 상기 터널링 산화막 상에 질화막을 증착하는 제 2 단계와;Depositing a nitride film on the tunneling oxide film; 상기 질화막 상에 포토레지스트를 도포한 후 게이트 패턴을 형성하고, 상기 질화막을 식각하는 제 3 단계와;A third step of forming a gate pattern after applying a photoresist on the nitride film and etching the nitride film; 상기 질화막을 증착시킨 후, 측벽 식각 공정을 실시하는 제 4 단계와;A fourth step of performing a sidewall etching process after depositing the nitride film; 상기 제 4 단계에서 형성된 질화막의 홀 라인내에 폴리실리콘을 증착시킨 다음, 포토레지스트를 도포하여 게이트 패턴을 형성하는 제 5 단계와;Depositing polysilicon into the hole line of the nitride film formed in the fourth step, and then applying a photoresist to form a gate pattern; 게이트 식각 및 세정 공정을 실시하여 최종 게이트 라인을 형성하는 제 6 단계를 포함하는 것을 특징으로 하는 반도체 다마신 구조를 이용한 게이트 라인 형성 방법.And a sixth step of forming a final gate line by performing a gate etching and cleaning process. 제 1 항에 있어서,The method of claim 1, 상기 방법은,The method, 상기 게이트 형성시 상기 질화막과 측벽 식각 공정을 통하여 게이트 라인 폭을 조절하는 것을 특징으로 하는 반도체 다마신 구조를 이용한 게이트 라인 형성 방법.The gate line forming method using the semiconductor damascene structure, characterized in that for adjusting the gate line width through the nitride film and sidewall etching process when forming the gate. 제 1 항에 있어서,The method of claim 1, 상기 제 6 단계는,The sixth step, 상기 최종 게이트 라인의 형성에 있어서 상기 폴리실리콘 라인 옆에 상기 질화막을 잔류시켜 모트(Moat)와 폴리실리콘의 절연을 실시하는 단계인 것을 특징으로 하는 반도체 다마신 구조를 이용한 게이트 라인 형성 방법.And forming the final gate line to insulate the nitride and the polysilicon by remaining the nitride film next to the polysilicon line.
KR1020020056401A 2002-09-17 2002-09-17 Method for forming a gate line in a semiconductor damascene structure KR20040025800A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
KR20010065914A (en) * 1999-12-30 2001-07-11 박종섭 A method for fabricating damascene gate type mos transistor
KR20030000123A (en) * 2001-06-22 2003-01-06 주식회사 하이닉스반도체 Transistor and method for manufacturing the same
KR20040007951A (en) * 2002-07-15 2004-01-28 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
KR20010065914A (en) * 1999-12-30 2001-07-11 박종섭 A method for fabricating damascene gate type mos transistor
KR20030000123A (en) * 2001-06-22 2003-01-06 주식회사 하이닉스반도체 Transistor and method for manufacturing the same
KR20040007951A (en) * 2002-07-15 2004-01-28 주식회사 하이닉스반도체 Method for fabricating semiconductor device

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