KR20040013813A - Multi synchronous and multi resolution interpolation method in digital dynamic convergence control system - Google Patents

Abstract

PURPOSE: A method for interpolating multi-synch and multi-resolution in a digital dynamic convergence control system is provided to adjust a compensation voltage corresponding to changes of synch frequencies and a change of resolution without operating data of a memory or increasing capacity of the memory. CONSTITUTION: A change in the number of horizontal synchronous signals is detected and recognized during one period of vertical synchronous signals. A change quantity of the horizontal synchronous signals is calculated. The number of increment lines and increment data of interpolation data are calculated according to the change quantity. The interpolation data are changed based on the calculated number of increment lines and increment data to output a compensation voltage.

Description

Multi synchronous and multi resolution interpolation method in digital dynamic convergence control system

The present invention relates to a digitally controlled convergence correction device for correcting a convergence error of a screen in a CRT imager used for a monitor and a TV. In particular, it is possible to recognize a change in sync frequency and a change in resolution. In order to adjust the convergence on the screen in response to the change of the sync frequency and the change of resolution, the data of the sync frequency can be adjusted without measuring or increasing the memory to obtain new data by adding a certain weight to the data. The present invention relates to a multi-sync and multi-resolution interpolation method in a digital dynamic convergence control system for adjusting convergence on a screen by creating convergence data corresponding to a change and a change in resolution.

In general, a deflection yoke (DY) in a CRT imager performs a function of deflecting R, G, and B electron beams to reach a desired position on a screen. As the screen is getting finer, it is not possible to achieve the desired convergence performance of the screen with the deflection yoke alone. Therefore, it is common to mount several compensators on the deflection yoke.

Above all, the magnetic pole adjustment coils of Convergence Purity Magnet (CPM) operation principle are attached to the neck of the deflection yoke to move the R and B beams relative to the G beam. Dynamic Convergence Controllers, which dynamically adjust the convergence state of the screen, are widely used.

In particular, in accordance with the advent of digital TV broadcasting, it is essential to apply a dynamic convergence correction device to implement a high-definition screen at the HDTV level for text information transmission and graphic processing.

The circuit of the conventional dynamic convergence correction device for deflection yoke described above is composed of a plurality of resistors, inductors, capacitors, diodes, and the like. It is a method to correct the convergence error of the screen by adjusting.

With this type of adjustment circuit, only a current waveform of a predetermined type can be applied to the magnetic field adjustment coil, and therefore, there is a technical limitation that only a limited number of convergence errors are corrected. In addition, when the miss convergence error of one region of the screen is corrected, the miss convergence error of the other region is also changed in response so that it is very difficult to correct all the miss convergence errors of the entire screen.

In addition, the operator visually checks the degree of convergence error and empirically adjusts and adjusts the adjustment means appropriately based on this, so that the convergence of the screen is desired for a large screen, a full plane, and an ultra wide-angle CRT imager. It is almost impossible to match with.

Therefore, in the conventional method described above, a method proposed to overcome the limitations of the method of measuring the degree of error of convergence with the naked eye of the operator is a display device such as a color CRT, a liquid crystal display (LCD) or a color plasma display panel (PDP). A display characteristic measuring apparatus for measuring display characteristics such as convergence of is proposed.

This display characteristic measuring apparatus is configured to capture an image of each color component of an image of each color component of R (red) G (green) B (blue). An image processing apparatus which performs predetermined processing after the processing, and a display apparatus which displays the measurement result.

For example, as shown in Japanese Patent Application Laid-Open No. 8 (1996) -307898, the convergence measuring device displays a predetermined white measurement pattern displayed on a color CRT to be measured by a camera equipped with a color gamut sensor such as a CCD. During image pick-up, the luminance center of each picked-up image of each color component R, G, and B is calculated during image processing, and the relative displacement of this luminance center is displayed in the amount of miss convergence.

Therefore, the miss convergence measuring device calculates the light emission position (light emission center position) of the measurement pattern of each color component on the display surface of the color CRT measured by the measurement pattern image formation position (luminance center position) of each color component on the image plane of the color camera. The relative variation in the light emission position of each color component is calculated.

However, this technique is calibrated using a special calibration chart before measurement as shown in the accompanying FIG. 1 due to its own problems, that is, the measurement accuracy easily changes with changes in temperature and humidity.

In the calibration method shown in FIG. 1, a calibration chart 103 (chart with a cross hatching pattern 105 drawn on an opaque white plate) illuminated by a fluorescent lamp 104 is displayed on the imaging device 101 of the convergence measurement device 100. Correction data indicating the relative positional relationship of each area sensor is calculated using the captured image. The calculated calibration data is stored in a memory in the apparatus main body 102 and used as data for correcting the shift of the luminance center position of each color component measurement pattern at the time of convergence measurement.

According to the conventional method for correcting the relative variation of the area sensor, the position (absolute position) of each area sensor in the reference coordinate system in the convergence measurement system is determined by using respective color component image data obtained by photographing a special calibration chart. The relative variation of the area sensor is calculated by this calculation result. As a result, many computational parameters (parameters) increase, which requires a lot of computational time.

Moreover, because a special calibration chart is used rather than the measurement pattern displayed on the CRT to be measured, a problem arises that it is inconvenient and difficult to calibrate the convergence measurement system in the production line.

A recent technique proposed to overcome the above-mentioned problems is a technique described in Korean Patent Laid-Open No. 1999-013780, which is an apparatus for automatically measuring convergence of a color CRT shown in FIG.

1 is a schematic block diagram of the convergence measuring device 1 of the color CRT, the convergence measuring device 1 including an imaging device 2 and a measuring device 3.

The imaging device 2 captures a predetermined measurement pattern (e.g., cross hatching pattern, dot pattern, etc.) displayed on the display surface of the color display 4 to be measured, and detects an image by stereoscopic vision. A pair of imaging cameras 21 and 22 are provided.

The measuring device 3 calculates the miss convergence amount of the color display 4 using the image data of the measurement pattern obtained by the imaging device 2, and displays the result of the calculation on the display device 36.

The imaging camera 21 in the imaging device 2 is provided with a dichroic prism 212 that decomposes light into three colors behind the imaging lens 211, and the respective colors R, G, and B rays appear. A solid-state image pickup device 213R, 213G, or 213B including a CCD area sensor is disposed at a position facing the exit surface of the dichroic prism 212, and is a three-plate type color image pickup device. The imaging camera 22 is also a three-plate color imaging device similar to the imaging camera 21.

The imaging camera 21 has an imaging controller 214 for controlling the operation of each of the solid state imaging elements (hereinafter referred to as CCD) 213R, 213G, and 213B, and the imaging lens 211 to be driven automatically. The focus control circuit 215 which adjusts the focus by the camera and the signal processing circuit 216 which performs predetermined image processing on the image signals transmitted from the CCDs 213R, 213G and 213B and outputs them to the measuring device 3 It is installed. In this manner, the imaging controller 224, the focus control circuit 225, and the signal processing circuit 226 are provided in the imaging camera 22.

The imaging controller 214 is controlled by an imaging control signal sent from the measuring apparatus 3, and controls the imaging operation (charge accumulation operation) of the CCDs 213R, 213G, and 213B by this imaging control signal. The imaging controller 224 is controlled by an imaging control signal sent from the measuring device 3, and controls the imaging operation of the CCDs 213R, 213G, and 213B by this imaging control signal.

The focus control circuit 215 is controlled by the focus control signal sent out from the measuring device 3 and drives the front group 211A of the imaging lens 211 by this focus control signal, thereby displaying the color display 4. The optical image of the measurement pattern displayed on the surface is imaged on the imaging surface of CCD (213R, 213G, 213B).

Similarly, the focus control circuit 225 is controlled by the focus control signal transmitted from the measuring device 3, and drives the front group 221A of the imaging lens 221 by the focus control signal, thereby displaying the color display. The optical image of the measurement pattern displayed on the display surface of (4) is imaged on the imaging surface of CCD (213R, 213G, 213B).

Focus control is performed by a signal from the controller 33, for example, by a climbing method. Specifically, for example, in the case of the imaging camera 21, the control unit 33 extracts the green image high frequency component (end of the measurement pattern) picked up by the CCD 213G so that the high frequency component is maximized (of the measurement pattern). The focus control signal is output to the focus control circuit 215 so that the end is clearer.

The focus control circuit 215 moves the front and rear groups 211A of the imaging lens 211 forward and backward to reduce the distance of movement gradually in accordance with the focus control signal so as to reduce the moving distance. Finally it is set.

Focus control is performed using the image picked up in this embodiment. However, for example, the imaging cameras 21 and 22 are provided with distance sensors, and the imaging lenses 211 and 221 are display surfaces of the imaging cameras 21 and 22 and the color display 4 detected by the distance sensors. Can be driven using distance data between.

The measuring device 3 comprises analog / digital (A / D) converters 31A and 31B, image memories 32A and 32B, a control unit 33, a data input device 34, a data output device 35 and a display. Device 36.

The color display 4 to be measured includes a color CRT 4 for displaying a video image and a drive control circuit 42 for controlling the driving of the color CRT. The video signal of the measurement pattern generated by the pattern generator 5 is input to the drive control circuit 42 of the color display 4, which in turn drives the deflection circuit of the color CRT 41 by means of the video signal to the display surface. For example, the cross hatching measurement pattern is displayed as displayed in FIG. 3.

In this convergence measuring device 1, the measurement pattern images displayed on the color display 4 are stereoscopically picked up by the imaging cameras 21 and 22 of the imaging device 2, and the amount of miss convergence is reduced. It measures using the image data obtained by 22).

That is, the accompanying FIG. 3 is a diagram showing the cross hatching pattern 6 displayed on the color CRT 41, and the cross hatching pattern 6 is made by crossing a plurality of vertical lines and a plurality of horizontal lines. The display surface 41a of the color CRT 41 is displayed in a suitable size so that a plurality of intersection points are included. The miss convergence amount measuring regions A (1) to A (n) are set at arbitrary positions in the display surface 41a to have at least one intersection point.

In each measurement area A (r) (r = 1, 2, ... n), the image of the vertical line in which the horizontal (X direction in the XY coordinate system) miss convergence amount ΔDX is included in this measurement area A (r) The image is calculated by the image, and the vertical (Y direction in the XY coordinate system) miss convergence amount ΔDY is calculated by the captured image of the horizontal line.

Even though accurate data on miss convergence is secured by the recent technology as described above, the object of controlling the convergence is ultimately limited to the deflection yoke, so it is possible to adjust the error of the total convergence when adjusting the deflection yoke. The fundamental problem is that only some areas of convergence cannot be adjusted independently.

That is, it is common to adjust the convergence of one part so that the convergence of other parts related to each other is also changed, so that the correction of the miss convergence to the most optimal state as a whole is performed.

In particular, in the high-definition screen such as HDTV, the difficulty is more serious.

The method proposed to solve the above-mentioned problems is a digital operation convergence method proposed by the present applicant. Referring to the accompanying FIGS. 4 and 5, the attached FIG. 4 is a digital dynamic convergence control method proposed in the prior art. As an exemplary view for explaining the concept of the measurement and correction system according to the present invention, in FIG. 4, the digital convergence controller receives correction data for intersections of the cross hatch pattern screen from the outside and stores the correction data in the memory according to a predetermined recording address. Then, by receiving the horizontal and vertical synchronization signals obtained from the image signal supplied to the CRT image device, the extraction address of the corresponding memory is generated in synchronization with the scanning time of the intersection points, and the correction data stored in the memory is read according to the extraction address. Drives magnetic field adjustment coil by converting and amplifying to control voltage or control current Device.

Here, the correction data are voltage values or current values to be applied to each of the two-pole, four-pole, and six-pole magnetic field adjustment coils for the control points defined as the crossing points on the screen of the cross hatch pattern as shown in FIG. 5. As shown in FIG. 4, the screen convergence error measured by the convergence measuring device is calculated in the control computer through the control logic and the beam trajectory analysis and transferred to the digital dynamic convergence controller.

In addition, the recording address and the extraction address are configured by combining the vertical position number, the horizontal position number of each control point and the magnetic field adjustment coil number to be output from the control point, through which the individual access and adjustment of the convergence of each control point is possible.

In this manner, convergence can be adjusted independently for each of the control points MCP11 to MCP55 of FIG. 5. That is, the method of controlling the current amount of each of the two-pole, four-pole, and six-pole magnetic field adjustment coils at the positions of the respective screen control points of FIG. 5 attached thereto. It can be seen that the convergence of the electron beam can be adjusted to any state. For reference, the operation principle of the magnetic field adjustment coil is conceptually the same as the operation principle of the convergence purity magnet mounted on the neck of the deflection yoke.

The attached screen automatic calibration system of FIG. 4 is a closed loop structure, and repeatedly performs the above-described calibration process several times to achieve the desired convergence performance, and then the final calibration data is stored in the EEPROM inside the digital dynamic convergence controller. Only the portions marked with dotted lines in FIG. 4 attached thereto can be operated independently.

That is, when power is supplied with the combination of digital dynamic convergence controller, magnetic field adjustment coil, deflection yoke, and CRT separated from the automatic screen calibration system, the digital dynamic convergence controller is stored in the EEPROM. It works as an open loop structure that reads calibration data to correct for screen convergence errors.

By carrying out the determination of the correction data as described above with reference to FIG. 4 at a control computer external to the digital synchronization controller, the internal microcontroller of the digital synchronization is only responsible for the data transfer and storage processing and some control. High performance is not required, and the correction data should be made in real time in synchronization with the scanning of the image at the screen control points, which is suitable as a structure for outputting only the data stored in the memory with little internal calculation process.

In this case, the prior art digital dynamic convergence system is configured to perform horizontal and vertical resolution correction and interpolation, but each sink frequency / resolution is to be applied to a product that can change vertical / horizontal resolution in one set, such as a monitor. Convergence error corresponding to, should be measured, and the method of storing data in memory should be applied.

In addition, if the sync frequency / resolution changes so much that each screen mode is to be coped with, the measurement error needs to be measured for each corresponding mode, and a lot of measurement time is required. Capacity will also increase. However, since the convergence error is measured for each data, the error displayed on the screen has the advantage of minimizing.

However, even if the convergence error of the product is minimized, it is pointed out as a problem because the production yield is lowered as the production yield is lowered.

An object of the present invention for solving the above problems relates to a digital control method of the same convergence correction device for correcting the convergence error of the screen in a CRT imager used for a monitor and a TV, in particular, In addition to recognizing changes in resolution, you can manipulate data in memory to adjust on-screen convergence in response to changes in sync frequency and resolution, or measure to obtain new data by adding a certain weight to the data. The present invention provides a multi-sync and multi-resolution interpolation method in a digital dynamic convergence control system for adjusting convergence on a screen by generating convergence data corresponding to changes in sync frequency and resolution without increasing memory.

1 is an exemplary diagram of a measurement apparatus for generating a conventional automatic miss convergence correction value.

2 is an illustration of an improved miss convergence measurement apparatus of the technique shown in FIG.

3 is an illustration of an image pattern for application of the technique shown in FIG.

4 is an exemplary system for explaining a prior art digital dynamic convergence control method.

FIG. 5 is an exemplary diagram of an image pattern for applying the technique of FIG. 4. FIG.

6 is an exemplary block diagram of a digital dynamic convergence control system in FIG. 4;

7 is an exemplary block diagram of the address generator of FIG. 6.

8 is a block diagram illustrating the correction / interpolator of FIG. 6.

FIG. 9 is an exemplary diagram for explaining an example of a cloth pattern and definition of each term used in the technique illustrated in FIG. 6. FIG.

10 is an exemplary waveform diagram for explaining a horizontal correction according to the present invention.

11 is an exemplary waveform diagram for explaining vertical-side interpolation according to the present invention.

12 is an explanatory diagram for explaining generation of a correction voltage according to the present invention;

A feature of the multi-sync and multi-resolution interpolation method in the digital dynamic convergence control system according to the present invention for achieving the above object is to store individual miss convergence correction data and interpolation data for each intersection of the cross hatch pattern screen. Nonvolatile external memory; A control unit for extracting correction and interpolation data stored in the memory connected to a memory address bus and a data bus and generating a control signal for performing correction and interpolation of each area of the screen; Reference clock generating means for generating a clock signal according to an arbitrary reference frequency corresponding to the clock control signal inputted from the controller; The setting signal and the interrupt signal for the correction interpolation area in the display area are determined by the horizontal and vertical synchronization signals extracted from the input image signal, the control signal output from the controller, and the clock signal output from the reference clock generating means. An address generator that generates; An internal memory configured to store miss convergence correction and interpolation data input to the controller according to the recording address; And magnetic field adjustment for correcting the deflection degree of the electron beam by converting misconvergence correction and interpolation data output from the memory into current or voltage according to a control signal of the controller according to a setting signal generated by the address generator. A digital dynamic convergence control device comprising: an output unit applied to a coil, comprising: a first step of detecting and recognizing a change in the number of horizontal synchronization signals during one period of a vertical synchronization signal; Calculating a change amount of the horizontal synchronization signal number; A third step of calculating the interpolation data recorded in the internal memory by changing the number of increment lines and the increment data in accordance with the change amount calculated in the second step; And a fourth process of outputting a correction voltage by changing interpolation data based on the calculated incremental number of lines and the incremental data.

As an additional feature of the multi-sync and multi-resolution interpolation method in the digital dynamic convergence control system according to the present invention for achieving the above object, the third process is limited to a vertical interval and a section not output on the actual screen. The number of horizontal synchronization signals (N) for each section is Wow Changing to a first step; Based on the data changed through the first step A second step of changing the incremental data; Correction voltage Calculating a third step; Correction voltage at the time of change Calculating a fourth step; Incremental data Δv 'is calculated based on the correction voltage and the modified correction voltage calculated through the third and fourth steps. It is characterized by consisting of a fifth step of calculating and defining.

The above object and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, the configuration and operation of the digital dynamic convergence system to which the present invention is applied will be briefly described. FIG. 6 is a block diagram of the digital dynamic convergence control system, except for the reference numeral 12. Implemented in one chip but divided by module in terms of its function, a control unit comprising a microcontroller 11, a storage unit consisting of an EEPROM 12 and RAMs 13A and 13B, a phase-locked loop 14 and an address An extracting address generator comprising a generator 16, an output comprising a correction / interpolator 17 and a D / A converter (DAC) 18.

Highly integrated digital dynamic convergence controller has three modes of "FIRM", "HOME" and "TEST" according to the external control signal input.

Therefore, first, the microcontroller 11 of the control unit receives a preset mode signal from an external source and is currently in closed loop (FIRM) mode for generating miss convergence correction / interpolation data, or miss convergence correction stored in the EEPROM 12. Determine whether you are in open mode (TEST) mode or in test mode that processes interpolated data.

If the mode signal is the closed loop mode, the microcontroller 11 of the control unit receives an externally corrected data and a control command signal to create a recording address to be stored in the memory. The address generator 16 is operated so that the log recording address is transmitted to the address ports of the RAM 13A and 13B, and then the correction data given together with the WE (Write Enable) signal is sent to the data ports of the RAM 13A and 13B. To store the correction data in the RAMs 13A and 13B. If the convergence correction is completed and the completion signal is given as the external control signal, the correction data stored in the RAMs 13A and 13B is stored in the EEPROM 12 connected to the outside.

If the mode signal is in the open loop mode, the microcontroller 11 extracts the correction data stored in the EEPROM 12 and transfers the recorded data to the RAMs 13A and 13B.

After the correction data is written to the RAM 13A and 13B, a control signal is generated so that the address output from the address generator 16 is transferred to the address ports of the RAM 13A and 13B, and at the same time, RE ( The read enable signal is sent to the RAMs 13A and 13B to make the RAMs 13A and 13B read.

At this time, the first RAM actually referred to by reference number 13A and the second RAM referred to by reference number 13B have different characteristics of the stored data. Looking at the characteristics of the stored data, the first RAM 13A includes The correction data is stored and the interpolation data is stored in the second ram 13B.

Here, the interpolation data is a vertical section between the intersection point and the intersection point of the difference between the correction data of each correction data and the control point located immediately below each of the screen control points defined as the intersection points in the cross hatch pattern screen of FIG. 5. This value is divided by the number of horizontal scan lines included in the image, and corresponds to an increment of correction data to be increased or decreased as the horizontal scan lines increase within a vertical section.

Therefore, when the microcontroller 11 is an external control signal and the completion signal, the microcontroller 11 operates the address generator 16 using the control signal, and the recording address output from the microcontroller 11 is the first RAM 13A and the second RAM. After the address bus is connected to the address port of 13B, correction data is stored in the first RAM 13A, and interpolation data is stored in the second RAM 13B. Thereafter, when the completion signal is input, the correction data and the interpolation data are stored in an external EEPROM referred to by reference numeral 12.

If the mode signal is in the open loop mode, the microcontroller 11 reads correction data and interpolation data stored in the EEPROM 12 and transfers them to the corresponding RAMs 13A and 13B, respectively.

Thereafter, when both the correction data and the interpolation data are recorded and stored in the RAM 13A and 13B, a control signal is generated to extract the address of the address generator 16 to the addresses of the first RAM 13A and the second RAM 13B. Simultaneously transferred to the bus, both the first and second RAMs 13A and 13B are read by a RE signal.

At this time, the address generator 16 receives the horizontal and vertical synchronization signals and outputs the extracted addresses of the correction data and interpolation data stored in the first and second RAMs 13A and 13B in synchronization with the scanning points of the respective screen control points. do.

Thereafter, the correction / interpolator 17 uses the correction data and the interpolation data simultaneously output from the first and second RAMs 13A and 13B according to the memory extraction address of the address generator 16 in one vertical section. It generates the correction and interpolation data according to the horizontal scan line number countered by.

That is, if the above process is further described, the highly integrated digital dynamic convergence controller has three modes of "FIRM", "HOME", and "TEST" according to the external control signal input.

First, in the "FIRM" mode, the microcontroller 11 receives control signals and data necessary for correction / interpolation from an external control computer via RS-232C or I2C communication, and stores the data according to the received control signal. 13B) or to an external EEPROM 12 provided via any communication means including I2C communication, and to read data from the EEPROM 12, if necessary, to RAM 13A and 13B. It may be.

In addition, I2C communication may receive a current mode state of the CRT set and output a control signal. Then, the control signal is output to the address generator 16 according to the received control signal, and the interpolation control signal is output to the correction / interpolator 17.

On the other hand, in the "HOME" mode, the microcontroller 11 reads the data of the EEPROM 12 in I2C communication and stores the data in the RAMs 13A and 13B, and the address generator 16 and the correction / interpolator 17 ) And a control signal and an interpolation control signal, respectively, and wait for the interrupt signal of the address generator 16 and the CRT set. The control signal and the interpolation control signal may be changed according to the interrupt signal generated by the address generator 16 and the CRT set.

Finally, in the "TEST" mode, the address generator 16, the RAMs 13A, 13B, the compensator / interpolator 17, and the PLL 14 are tested according to the program of the microcontroller 11. do.

Regardless of the above three modes, the PLL can output clocks from 20 MHz to 280 MHz, depending on the frequency set from the microcontroller.

After the mode is decided as above, each designated operation is made and after the operation is completed, a constant address and control signal are made by the address generator, and the data is output from the RAM position indicated by the address to correct / interpolate. Part, and the correction / interpolator part generates new data according to the method determined by the control signal and outputs it to the DAC.

The detailed configuration of the address generator 16 and the correction / interpolator 17, which are the most important components for the overall operation, will be described with reference to FIGS. 7 and 8.

7 is a detailed block diagram of the address generator, wherein the address generator is configured to display the number of clocks counting the output signal " FVCO " clock of the PLL 14 generated according to the control signal of the controller for one period of the horizontal synchronization signal. The control unit 11 generates and outputs a control signal based on the number of clocks, and counts the number of clocks of the FVCO for one period of a horizontal synchronous signal, outputs "NCNT", receives the output "NCNT", and " Counter 1 (C1) and comparator 1 (CO1), which generate an interrupt signal according to the change in clock number when there is a variation in the number of horizontal synchronization signals, and the "NCP", and "skip" among the control signals output from the controller 11. Divides the remaining portion of the horizontal synchronous signal after subtracting the number of " skip number " by the " skip number " clock in one period of the horizontal synchronous signal and divides the remaining portion of the horizontal synchronous signal according to the " dividing ratio 1 " Divider to generate a signal 1 (D1), counter 2 (C2) for generating a horizontal address signal by counting the horizontal control signal generated by the divider 1 (D1), and " skip number " of the control signals outputted from the controller 11; A minute that receives the "dividing ratio 1" and subtracts the number of horizontal synchronizing signals equal to the "pass number" in one period of the vertical synchronizing signal and divides the remaining portion of the vertical synchronizing signal according to the "dividing ratio 2" to generate a vertical control signal. Counter 2 (C3) for generating a vertical address signal by counting the period 2 (D2), the vertical control signal generated in the divider 2 (D2), and counting the number of clocks of the horizontal synchronization signal during one period of the vertical synchronization signal. Counter 4 (C4) outputting the count value, and the count value output from the counter 4 (C4) is inputted, and each time there is a difference between the previous count number and the vertical synchronization signal, an interrupt signal is output if there is a difference. Interrupt output from the comparator 1 (CO1) If the funny signal only consists of the comparator 2 (CO2) for outputting an interrupt signal output.

In addition, the correction interpolator illustrated in FIG. 8 includes RAM1-1 (18A) for outputting corresponding correction data which receives and stores a horizontal vertical address signal, and corresponding interpolation data for receiving and storing a horizontal vertical address signal. RAM2-1 (18B) for outputting the data, the vertical control signal and horizontal synchronization signal input from the address generator 16 and the number of lines of interpolation data from the RAM2-1 (18B) is received between the vertical control signal A counter 18C for counting the number of horizontal synchronization signals to be skipped and counting the number of lines of the interpolation data by skipping, and the counter 18C according to an enable signal according to the number of interpolation data lines from the RAM2-1 (18B). The multiplier 18D receives the counting value and the interpolation data from the control unit 11 and multiplies the interpolated data, and receives the data output from the RAM2-1 (18B) and recognizes the sign of the corresponding signal. A code bit reader 18G for outputting another operation signal, and data output from the RAM1-1 18A and RAM2-1 (18B) and receiving an output signal of the multiplier 18D from the code bit reader 18G. And an adder 18E and a subtractor 18F which add or subtract according to the operation signal of the "

The apparatus further includes a MUX 18H for selectively outputting the outputs of the subtractor 18F and the adder 18E, and a latch 18I for temporarily storing the output signal of the MUX 18H and for delaying time. .

At this time, the clock FVCO of the PLL 14 generated according to the control signal is input to the address generator. The input FVCO does not change even if the horizontal and vertical synchronization signals change. When the FVCO returns the number of clocks counted for one period of the horizontal synchronization signal to the microcontroller 11, the microcontroller 11 has the number of clocks and the number of skips, passes, division ratio 1, division ratio 2, and comparator 1 clocks. Produce a control signal of. These values may be specified arbitrarily.

In addition, the divider 1 (D1) receives the skip number and the division ratio 1 and divides the remaining portion of the horizontal synchronous signal according to the division ratio 1 by subtracting the FVCO clock number equal to the skip number in one period of the horizontal synchronization signal. Make The horizontal control signal thus produced is counted in counter 2 (C2) to form a horizontal address signal.

In addition, divider 2 (D2) receives the number of passes and the division ratio 2, and divides the remaining portion of the vertical synchronization signal according to the division ratio 2 by subtracting the number of horizontal synchronization signals equal to the number of passes in one period of the vertical synchronization signal. Make a signal. The vertical control signal thus produced is counted at count 3 (C3) to create a vertical address signal.

In addition, counter 1 (C1) outputs NCNT by counting the number of clocks of FVCO during one period of horizontal synchronization signal, and accordingly, when comparator 1 (CO1) receives this NCNT and has a previously existing NCNT and horizontal synchronization signal. The signal is output when the difference is greater than the number of one comparator by comparison. This operation is a method of generating an interrupt signal in response to the change of the horizontal synchronization signal.

In addition, counter 4 (C4) counts the number of clocks of the horizontal synchronization signal during one period of the vertical synchronization signal and outputs the count to comparator 2 (C2), and comparator 2 (C2) receives the count and compares the previous count with the previous count. Whenever there is a vertical synchronization signal, it compares and outputs an interrupt signal when there is a difference. However, comparator 2 (C2) outputs an interrupt output signal only when there is an interrupt output signal from comparator 1 (C1).

At this time, look at the nature and supply of each signal as follows.

First, the "horizontal synchronization signal", "vertical synchronization signal" and "screen mode conversion signal" are input from a TV set, and "Serial communication (RS-232C)" is connected to an external control computer to exchange data. .

The "external control signal" is an input signal for determining the mode of 1 chip, and the control signal (input determined by the producer) input from the microcontroller 11 to the address generator 16 is "dividing ratio 1", It is composed of "skip number", "division ratio 2", "pass number", "comparator 1 clock number", and "MUX control signal".

Further, the control signal input from the microcontroller 11 to the PLL 14 is a frequency setting value, and the control signal input from the microcontroller 11 to the correction / interpolator 17 is an interpolation control signal (interpolation data structure). Change signal).

Referring to FIG. 13, in the address generator 16, a control signal output from the microcontroller 11, that is, "skip number", "division ratio 1", "pass number", "division ratio 2", and "comparator 1" The number of clocks, "FVCO", "vertical sync signal" and "horizontal sync signal" generate NCNT, horizontal address, vertical address, horizontal control, vertical control signal and interrupt signal. Therefore, as shown in Fig. 15, the signal of the address generator portion is set.

In addition, the output frequency of the PLL 14, i.e., FVCO, is determined by the frequency setting value sent from the microcontroller 11 to the PLL 14, and this value is determined by the counter 1 and minutes indicated by reference numerals D1 and C1. It is input in period 1.

In the frequency divider 1 (D1), FVCO is counted and subtracted by "skip number" in one period of the horizontal synchronous signal, and the remaining horizontal synchronous signal is divided according to the division ratio 1 (D1) to make a horizontal control signal. The signal is counted at counter 2 (C2) to create a horizontal address.

In the divider 2 (D2), the horizontal synchronous signal is counted and subtracted by "pass number" in one period of the vertical synchronous signal, and the remaining vertical synchronous signal is divided according to the "dividing ratio 2" to make a vertical control signal. The control signal is counted at counter 3 (C3) to create a vertical address.

As shown in FIG. 10, the counter 1 (C1) counts the FVCO input every cycle of the horizontal synchronization signal, and outputs the NCNT value. Therefore, when the number of clocks of the comparator 1 (C1) is greater than that, an interrupt signal is generated to inform the microcontroller 11 that the frequency of the horizontal synchronization signal has changed.

In addition, in the counter 4 referred to by reference number C4, after the frequency of the horizontal synchronizing signal is changed, the horizontal synchronizing signal inputted during one period of the vertical synchronizing signal is counted and sent to the comparator 2 (CO2). ), When the number is different from the number of horizontally synchronized signals initially set, an interrupt signal is generated to inform the microcontroller 11 that the resolution has been changed.

This interrupt generation is first generated by the horizontal synchronization frequency conversion, and after the interruption by the horizontal synchronization frequency conversion, the interruption by the resolution conversion readout can be generated.

First, when an interrupt occurs due to horizontal synchronization frequency conversion, the microcontroller 11 calculates the frequency change amount of the horizontal synchronization signal, and accordingly resets the values of skip number, division ratio 1, and comparator 1 clock number to output to the address generator. When an interrupt occurs due to a change in resolution, the number of pass and the division ratio 2 are reset according to the number of horizontal synchronization signals, and the result is output to the address generator.

Each of the terms shown in the drawings is as shown in FIG. 9. That is, the interval between the horizontal address and the vertical address forming the cloth pattern on the screen is represented by the division ratio, where the division ratio 1 represents the horizontal side and the division ratio 2 represents the vertical side.

Also, the number of skips is for defining a blank area between the area displayed on the actual screen and the image signal recognized by the horizontal synchronization signal, and the number of passes is the image signal recognized due to the area displayed on the actual screen and the vertical synchronization signal. It is to define the blank area between.

Accordingly, as described above, when an interruption occurs due to the horizontal synchronization frequency conversion, the microcontroller 11 calculates the frequency change amount of the horizontal synchronization signal, and resets the values of the skip number, the division ratio 1, and the comparator 1 clock number accordingly. When the interrupt occurs due to the change of resolution, the frequency of the horizontal synchronous signal changes according to the number of the horizontal synchronous signals and the frequency ratio 2 is reset and output to the address generator. Even if the resolution is changed, it creates an address where the set correction / interpolation can occur at the designated position.

In addition, the address generator 16 generates a horizontal control signal, a vertical control signal, a horizontal address, and a vertical address according to the reset control data.

The first RAM referred to by reference number 13A stores correction data of a designated correction point, and the second RAM referred to by reference number 13B stores interpolation data for correction between correction points without correction data.

The data stored in the RAMs 13A and 13B outputs data by the address generated by the address generator, and outputs data corresponding to the address whenever the address is changed. Interpolation data is composed of code bits, number of lines and interpolation amount.

The counter, referred to as reference number 18C, counts the number of horizontal sync signals between the vertical control signals, as shown in Figure 11, which counts by skipping the number of lines of interpolation data. The counted value is transferred to the multiplier referred to by reference number 18D, multiplied by the interpolation amount, and output to the adder 18E and the subtractor 18F.

The adder 18E and the subtractor 18F determine the operation according to the sign bit of the interpolation data, and add or subtract the correction data and the data output from the multiplier.

Therefore, the section not scanned on the actual screen according to the horizontal / vertical control signal is controlled by placing the MUX 18H so as to output an arbitrary value set by the user. Before the horizontal synchronous signal is started and the first horizontal control signal is output, the correction data to be output in the first horizontal section is output as it is.The value set by the user before the vertical synchronous signal is started and the first vertical control signal is output. Will print In other words, the section set by the pass number outputs a value set by the user, and the section set by the skip number outputs a value to be output after the skip number.

The interpolation data stored in the RAM 18B may change the number of bits of the data depending on the resolution. Since the number of horizontal synchronous signals changes when the resolution is changed, the number of lines of interpolation data and the amount of interpolation must be adjusted, so that the data values that can be represented also change, thereby changing the number of lines and the number of bits constituting the interpolation amount.

Therefore, if the resolution is changed and interrupted, the microcontroller outputs the control signal again according to the changed resolution. The bit representation and calculation of the counter, multiplier, adder, and subtractor are changed according to the control signal.

In this case, although the digital dynamic convergence system operating as described above performs some correction interpolation, as described above, when the sync frequency / resolution changes so much that each screen mode is to be coped with, each corresponding mode Since it is necessary to measure the convergence error every time, it takes a lot of measurement time, and also the memory capacity increases because each memory mode needs to be added.

Therefore, in the present invention, when the change in the sync frequency is detected by recognizing the change of the reference clock number (hereinafter, NCNT) for one period of the horizontal synchronization signal, as shown in FIG. 10, the change amount of the NCNT value is recognized after the change is recognized. Calculate the horizontal control signal and reset the value.

In this case, as shown in FIG. 11, the change in resolution is recognized by detecting a change in the number of horizontal synchronization signals during one period of the vertical synchronization signal. At this time, the amount of change in the number of horizontal synchronization signals is calculated, and the interpolation data recorded in the memory is calculated according to the amount of change. The interpolation data consists of a sign bit, an incremental line number (Δn) and an incremental data (Δv) .When the resolution is changed, the incremental data is reset by calculating the incremental line number and the incremental data or the weight is increased when the incremental data is output. To reset the incremental data.

The incremental data is calculated according to the change amount as follows.

The number N of horizontal synchronous signals during one section PASS and one vertical section not actually displayed on the screen is changed to PASS 'and N' as shown in Equations 1 and 2, respectively.

As shown in Equation 1 and Equation 2, if the number N of horizontal synchronous signals during one section PASS and one vertical section that is not actually displayed on the screen changes, the number of incremental lines is It is changed as shown in 3.

The incremental data is changed based on the calculation values according to the above equations, and the correction voltage is defined as Equation 4 below.

At this time, the correction voltage at the newly changed time point is calculated as in Equation 5 below.

At this time, the original correction voltage and the correction voltage value at the changed time should be the same.

Therefore, the relationship as shown in Equation 6 below is set.

The incremental data is calculated based on the relational expression according to Equation 6 described above. When the relational expression of Equation 6 is solved based on Equations 4 and 5, Equation 7 can be changed.

In addition, when the equation (7) is arranged based on the incremental data Δv ', the equation (7) is arranged as shown in equation (8),

By rearranging Equation 8, Equation 9 below can be obtained.

Accordingly, as shown in FIG. 10, when the skip number is adjusted according to the control signal, the correction voltage is output by changing the interpolation data with the changed increment number and increment data through the above-described mathematical process.

An example is shown in FIG. 12 attached.

While the invention has been shown and described in connection with specific embodiments thereof, it is well known in the art that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

According to the multi-sync and multi-resolution interpolation method in the convergence control system of the present invention according to the above-described process, by recognizing the change of the sync frequency and the change of the resolution, the convergence on the screen is adjusted according to the change of the sync frequency and the change of the resolution. Adjusting convergence does not store the data of convergence in memory for each mode, but changes the sync frequency and resolution without increasing the memory by manipulating the data in the memory or adding a certain weight to the data. In response to this, the correction voltage can be adjusted.

Therefore, it can be used in devices that can synchronize sync frequency and resolution like monitor, so that convergence can be adjusted in response to changes in sync frequency and resolution.

Claims (2)

A nonvolatile external memory for storing individual miss convergence correction data and interpolation data for each intersection of the cross hatch pattern screen; A control unit for extracting correction and interpolation data stored in the memory connected to a memory address bus and a data bus and generating a control signal for performing correction and interpolation of each area of the screen; Reference clock generating means for generating a clock signal according to an arbitrary reference frequency corresponding to the clock control signal inputted from the controller; The setting signal and the interrupt signal for the correction interpolation area in the display area are determined by the horizontal and vertical synchronization signals extracted from the input image signal, the control signal output from the controller, and the clock signal output from the reference clock generating means. An address generator that generates; An internal memory configured to store miss convergence correction and interpolation data input to the controller according to the recording address; And magnetic field adjustment for correcting the deflection degree of the electron beam by converting misconvergence correction and interpolation data output from the memory into current or voltage according to a control signal of the controller according to a setting signal generated by the address generator. In a digital dynamic convergence control device comprising an output unit for applying to the coil: A first step of detecting and recognizing a change in the number of horizontal synchronization signals during one period of the vertical synchronization signal; Calculating a change amount of the horizontal synchronization signal number; A third step of calculating the interpolation data recorded in the internal memory by changing the number of increment lines and the increment data in accordance with the change amount calculated in the second step; And And a fourth process of outputting a correction voltage by changing interpolation data based on the calculated incremental number of lines and the incremental data. The method of claim 1, In the third process, the number P of horizontal synchronization signals during one section PASS and one section vertically not actually displayed on the screen are respectively displayed. Wow Changing to a first step; Based on the data changed through the first step A second step of changing the incremental data; Correction voltage Calculating a third step; Correction voltage at the time of change Calculating a fourth step; Incremental data Δv 'is calculated based on the correction voltage and the modified correction voltage calculated through the third and fourth steps. The multi-sync and multi-resolution interpolation method of the digital dynamic convergence control system, characterized in that it comprises a fifth step of calculating.