KR20040010493A - The method and apparatus of multi channel controller for high speed memory - Google Patents

Abstract

PURPOSE: A multi channel controller apparatus using a high speed memory and a method thereof are provided to reduce its cost and fails by reducing the number of memories required in designing a system through increasing efficiency of data transmission. CONSTITUTION: According as designing a semiconductor related with a number of data input/output channel controls like a number of audio or video input/output signal channels using a memory(1) transmitting more than two data during one clock period like a DDR SD RAM and a RAMBUS DRAM, more than two memory transmission channel signals(for example, 16 camera inputs in case of a 16 channel video DVR system) are transmitted to a data signal line bus of the above memory during one clock period. The number requiring data transmission is output to a memory controller(3) and thus the memory controller performs data transmission below the above number.

Description

Device and method for multi channel controller using high speed memory {The method and apparatus of multi channel controller for high speed memory}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus and method using a memory (hereinafter, referred to as a speedup memory) for transmitting two or more data during one clock period, such as a double data rate (DDR) SD ram and a Rambus DRAM. The present apparatus and method relate to a memory bandwidth improving apparatus for inputting and outputting more data on the same bus width and clock by improving a conventional apparatus capable of sending only limited data per unit time, which has been a problem in a conventional SDRAM controller.

Memory control semiconductor devices for CCTV video, such as DVRs and multiplexers, have been used for signal processing using existing SDRAM control devices. In a conventional multi-channel video controller device, one data is transmitted per clock. See Figures 11 and 12. As a result, when the input / output amount of data increases, the data bus width is widened or signal processing is performed using a plurality of memories. In addition, when the memory controller needs data service of multiple channels, data transmission efficiency per channel is reduced by setting the number of units for each channel. See Figure 2 of 13. As shown in 13 of Fig. 2, each channel is allocated to each channel for signal processing. In addition, by forcibly allocating time for a channel that does not require data transmission, the transmission efficiency by the interface of the memory controller per unit time is reduced. As shown in 13 of Figure 2, during the service of each channel, memory transfer time division services were allocated to channels that do not require memory transfer in some cases, which required unnecessary memory control time.

The present invention increases the data transfer efficiency by using a high speed memory and improves a signal processing method, thereby reducing the number of memories required for system design, thereby achieving cost reduction, failure reduction, and the like. The technical problem to be achieved in the present invention is as follows.

(end). Increased transmission efficiency with faster memory.

This signal processing device uses a high-speed memory that reads and writes two or more pieces of data per clock. See 14, 15 in Figure 3. Quoted from DDR SDRAM control unit. In addition, by transmitting the number of data requiring memory transfer to the memory controller during memory input / output signal processing, the data number is arbitrarily adjusted by the number of data requiring transfer, thereby increasing the data transfer efficiency generated during control.

(I). How to adjust the number of memory transfers

When channel switching occurs during memory transfer control, the memory bus needs an unnecessary time (dummy cycle) that is not related to data transfer (by RAS, CAS, Refresh, etc.) by specifying an address before data transfer. In the conventional method, since the number of data to be transmitted for each channel is constant, the ratio of dummy cycles increases. See Figure 16 of 16. In Figure 13, the same service time is allocated for each channel to each channel.

In this signal processing device, the memory controller devices such as 4 and 5 of FIG. 1 output the number of data to be transmitted to the memory controller of 3 so that the number of data transmissions can be transferred to a random number less than the number to be transmitted to the memory controller. It was. This increases the efficiency of data transmission by not limiting the number of units to be transmitted. In other words, in the example of 13 and 16 of FIG. 2, in the conventional apparatus, as shown in FIG. 13, a constant time is allocated to each channel, and a certain number of data is allocated to a certain time regardless of the amount of data to be processed in the memory controller. Could only transfer. As shown in Fig. 16, the device checks the number of data transfers of the memory control device according to each channel situation.If the number of data transfers required is large, such as channel 1 in 16, the data transfer time allocated to channel 1 is allocated for a long time. We adjusted the number and made it possible to allocate a smaller transmission time when the data to be transmitted is small, such as channel 3.

(All). How to adjust the memory transfer channel

In the device of Figure 2.13, data transmission efficiency is reduced by allocating time to each channel as in the example of Figure 2.13, although data transmission is not necessary in the order of data transmission. That is, in the conventional apparatus as shown in the example of FIG. 2, even if there is no transmission data allocated to channel 2, the data service period is allocated. In the device, as shown in Fig. 16, in Figure 3, after the channel 1, the conventional method allocates the transmission time to channel 2, but the device skips channel 2, which does not require data transmission. A method of transmitting the data was used. Therefore, in this device, the transmission efficiency is increased by skipping data transmission when any channel does not need data transmission in order at the present channel.

1 is an overall configuration diagram of a memory control device

2 is a memory control scheme in a conventional apparatus

3 is a memory control scheme in the apparatus of the present invention.

Explanation of symbols on the main parts of the drawings

01. ---- High speed memory such as DDR, RamBus

02. ---- I / O memory operation signal

Ex). RAS, CAS, WE, Clock, Address, Data Bus Etc.

03. ---- Memory Control Unit

04. ---- Memory data input device input to the memory controller

05. ---- Memory data output device output from memory controller

06. ---- Semiconductor with memory control input / output device

07. ---- Multi channel input signal constituting memory input signal

08. ---- I / O signal between memory controller and memory data input device

09. ---- I / O signal between memory controller and memory data output device

10. ---- Multi channel output signal constituting memory output signal

11.14 ---- Memory and Memory Controller Drive Clock

12.15 ---- Memory control signal and address control signal and data bus I / O occupation signal

13.16 ---- Transfer time and sequence comparison example for each data transfer channel of memory controller

The structure of the present invention comprises the input / output channel blocks (4) and (5) to be transmitted by the speedup memory 1, the memory controller 3, and the memory controller. The input / output channel blocks 4 and 5 output the number of data to be transmitted to the memory controller 3 so that the memory controller can determine whether data transmission is necessary and calculate the number of data transfer possible.

The memory controller uses memory control signals, such as RAS (; Row Access Strobe), CAS (; Column Acess Strobe), WE (; Write Enable), and Address and Data DQ BUS signals to the high-speed memory. Perform signal processing.

The application of the present invention has the following effects in designing a multi-channel memory controller system that must process multiple memory inputs and outputs simultaneously.

First, by transmitting two or more data per one clock, it is possible to increase the amount of data transmitted per unit time in the same clock.

Second, by arbitrarily adjusting the number of data to be transferred to the memory, unnecessary time is reduced (dummy cycle not related to data transmission such as RAS, CAS).

Third, the transmission efficiency is increased by skipping channels that do not need to be input or output to memory. Accordingly, the number of memories to be used can be reduced by increasing the data transfer efficiency. As a result, cost reduction and failure factor reduction can be obtained.

Claims (3)

In designing semiconductors related to multiple data input / output channel control such as audio or video input / output signals of multiple channels using memory that transmits two or more data during one clock period such as double data rate (DDR) and Rambus DRAM , By transmitting two or more memory transmission channel signals (e.g., 16 camera inputs in the case of a 16-channel video DVR system) to the data signal line bus (hereinafter referred to as the bus) of the memory for two clock data for one clock period. , Apparatus and method for increasing memory data transfer efficiency. In designing semiconductors related to multiple data input / output channel control such as audio or video input / output signals of multiple channels using memory that transmits two or more data during one clock period such as double data rate (DDR) and Rambus DRAM , By outputting the number that needs data transfer to the memory controller, the memory controller transfers the memory data any number below the above number, Apparatus and method for increasing memory data transfer efficiency. In designing semiconductors related to multiple data input / output channel control such as audio or video input / output signals of multiple channels using memory that transmits two or more data during one clock period such as double data rate (DDR) and Rambus DRAM , By outputting the number that needs to be transferred to the memory controller, or by outputting a dedicated signal for transfer request, the memory controller uses this to jump the corresponding channel when there is no transfer request. Apparatus and method for increasing memory transfer efficiency.